test_rtt_413/MDK_405_dr/board/board.c

/*
 * Copyright (c) 2006-2021, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
 * 2018-11-06     SummerGift   first version
 */

#include "board.h"

/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

  /** Configure the main internal regulator output voltage
  */
  __HAL_RCC_PWR_CLK_ENABLE();
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLM = 4;
  RCC_OscInitStruct.PLL.PLLN = 168;
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
  RCC_OscInitStruct.PLL.PLLQ = 7;
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
  {
    Error_Handler();
  }

  /** Enables the Clock Security System
  */
  HAL_RCC_EnableCSS();
}

#include "shell.h"
INIT_APP_EXPORT(finsh_system_init);

extern void fal(uint8_t argc, char **argv);
MSH_CMD_EXPORT(fal, FAL (Flash Abstraction Layer) operate.);

extern int fal_init(void);
INIT_COMPONENT_EXPORT(fal_init);

#include <stdlib.h>
static void reset_fc(int argc, char **argv)
{
    int second = 20; // default 20s

    if (argc > 1)
    {
        second = atoi(argv[1]);
    }

    rt_kprintf("\n the system will be reset after %ds\n", second);
    rt_thread_delay(1000 * second);

    rt_hw_cpu_reset();
}
MSH_CMD_EXPORT(reset_fc, resetfc cmd);

int elm_init(void);
INIT_COMPONENT_EXPORT(elm_init);

int rt_hw_sdio_init(void);
INIT_DEVICE_EXPORT(rt_hw_sdio_init);

int stm_usbd_register(void);
INIT_DEVICE_EXPORT(stm_usbd_register);

int rt_soft_rtc_init(void);
INIT_DEVICE_EXPORT(rt_soft_rtc_init);

int cplusplus_system_init(void);
INIT_COMPONENT_EXPORT(cplusplus_system_init);

int rt_usbd_class_list_init(void);
INIT_BOARD_EXPORT(rt_usbd_class_list_init);

int rt_usbd_msc_class_register(void);
INIT_PREV_EXPORT(rt_usbd_msc_class_register);

int rt_hw_spi_init(void);
INIT_BOARD_EXPORT(rt_hw_spi_init);

#include "drv_spi.h"
static int init_spi_devices(void)
{
	// PB11 -> CS1
	rt_hw_spi_device_attach("spi2", "spi20", GPIOB, GPIO_PIN_11);
	// PA1 -> CS2
	rt_hw_spi_device_attach("spi2", "spi21", GPIOA, GPIO_PIN_1);

	return 0;
}
INIT_DEVICE_EXPORT(init_spi_devices);