调整 413 rtt 结构，预备添加 405 主工程

Signed-off-by: a1012112796 <1012112796@qq.com>
2024-07-23 16:31:02 +08:00
parent 9e281ac636
commit 007ad1dda6
32 changed files with 254 additions and 3865 deletions
--- a/MDK_413/board/board.c
+++ b/MDK_413/board/board.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#include "board.h"
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 8;
+  RCC_OscInitStruct.PLL.PLLN = 200;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Enables the Clock Security System
+  */
+  HAL_RCC_EnableCSS();
+}
+
+// init ports
+extern int cplusplus_system_init(void);
+INIT_COMPONENT_EXPORT(cplusplus_system_init);
+
+extern void fal(uint8_t argc, char **argv);
+MSH_CMD_EXPORT(fal, FAL (Flash Abstraction Layer) operate.);
+
+extern int fal_init(void);
+INIT_COMPONENT_EXPORT(fal_init);
+
+extern int iap_main_entry(void);
+INIT_ENV_EXPORT(iap_main_entry);
+
+#include <stdlib.h>
+static void reset_fc(int argc, char **argv)
+{
+    int second = 20; // default 20s
+
+    if (argc > 1)
+    {
+        second = atoi(argv[1]);
+    }
+
+    rt_kprintf("\n the system will be reset after %ds\n", second);
+    rt_thread_delay(1000 * second);
+
+    rt_hw_cpu_reset();
+}
+MSH_CMD_EXPORT(reset_fc, resetfc cmd);
+
+extern int ulog_console_backend_init(void);
+INIT_PREV_EXPORT(ulog_console_backend_init);
+
+extern int rt_hw_can_init(void);
+INIT_BOARD_EXPORT(rt_hw_can_init);
+
+extern int stm32_pwm_init(void);
+INIT_DEVICE_EXPORT(stm32_pwm_init);
+
+extern int stm32_adc_init(void);
+INIT_BOARD_EXPORT(stm32_adc_init);
+
+extern int stm32_capture_init(void);
+INIT_DEVICE_EXPORT(stm32_capture_init);
+
+extern int rt_wdt_init(void);
+INIT_BOARD_EXPORT(rt_wdt_init);