87
libraries/HAL_Drivers/config/f2/adc_config.h
Normal file
87
libraries/HAL_Drivers/config/f2/adc_config.h
Normal file
@@ -0,0 +1,87 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-06 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_H__
|
||||
#define __ADC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
#ifndef ADC1_CONFIG
|
||||
#define ADC1_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
|
||||
.Init.Resolution = ADC_RESOLUTION_12B, \
|
||||
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
|
||||
.Init.ScanConvMode = DISABLE, \
|
||||
.Init.EOCSelection = DISABLE, \
|
||||
.Init.ContinuousConvMode = DISABLE, \
|
||||
.Init.NbrOfConversion = 1, \
|
||||
.Init.DiscontinuousConvMode = DISABLE, \
|
||||
.Init.NbrOfDiscConversion = 0, \
|
||||
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
|
||||
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
|
||||
.Init.DMAContinuousRequests = DISABLE, \
|
||||
}
|
||||
#endif /* ADC1_CONFIG */
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
#ifndef ADC2_CONFIG
|
||||
#define ADC2_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC2, \
|
||||
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
|
||||
.Init.Resolution = ADC_RESOLUTION_12B, \
|
||||
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
|
||||
.Init.ScanConvMode = DISABLE, \
|
||||
.Init.EOCSelection = DISABLE, \
|
||||
.Init.ContinuousConvMode = DISABLE, \
|
||||
.Init.NbrOfConversion = 1, \
|
||||
.Init.DiscontinuousConvMode = DISABLE, \
|
||||
.Init.NbrOfDiscConversion = 0, \
|
||||
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
|
||||
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
|
||||
.Init.DMAContinuousRequests = DISABLE, \
|
||||
}
|
||||
#endif /* ADC2_CONFIG */
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
#ifndef ADC3_CONFIG
|
||||
#define ADC3_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC3, \
|
||||
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
|
||||
.Init.Resolution = ADC_RESOLUTION_12B, \
|
||||
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
|
||||
.Init.ScanConvMode = DISABLE, \
|
||||
.Init.EOCSelection = DISABLE, \
|
||||
.Init.ContinuousConvMode = DISABLE, \
|
||||
.Init.NbrOfConversion = 1, \
|
||||
.Init.DiscontinuousConvMode = DISABLE, \
|
||||
.Init.NbrOfDiscConversion = 0, \
|
||||
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
|
||||
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
|
||||
.Init.DMAContinuousRequests = DISABLE, \
|
||||
}
|
||||
#endif /* ADC3_CONFIG */
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ADC_CONFIG_H__ */
|
||||
171
libraries/HAL_Drivers/config/f2/dma_config.h
Normal file
171
libraries/HAL_Drivers/config/f2/dma_config.h
Normal file
@@ -0,0 +1,171 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-01-02 zylx first version
|
||||
* 2019-01-08 SummerGift clean up the code
|
||||
*/
|
||||
|
||||
#ifndef __DMA_CONFIG_H__
|
||||
#define __DMA_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* DMA1 stream0 */
|
||||
#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
|
||||
#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
|
||||
#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
|
||||
#define SPI3_RX_DMA_INSTANCE DMA1_Stream0
|
||||
#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0
|
||||
#define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn
|
||||
#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
|
||||
#define UART5_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
|
||||
#define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
|
||||
#define UART5_RX_DMA_INSTANCE DMA1_Stream0
|
||||
#define UART5_RX_DMA_CHANNEL DMA_CHANNEL_4
|
||||
#define UART5_RX_DMA_IRQ DMA1_Stream0_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA1 stream1 */
|
||||
#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
|
||||
#define UART3_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler
|
||||
#define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
|
||||
#define UART3_RX_DMA_INSTANCE DMA1_Stream1
|
||||
#define UART3_RX_DMA_CHANNEL DMA_CHANNEL_4
|
||||
#define UART3_RX_DMA_IRQ DMA1_Stream1_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA1 stream2 */
|
||||
#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
|
||||
#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
|
||||
#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
|
||||
#define SPI3_RX_DMA_INSTANCE DMA1_Stream2
|
||||
#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0
|
||||
#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn
|
||||
#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
|
||||
#define UART4_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
|
||||
#define UART4_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
|
||||
#define UART4_RX_DMA_INSTANCE DMA1_Stream2
|
||||
#define UART4_RX_DMA_CHANNEL DMA_CHANNEL_4
|
||||
#define UART4_RX_DMA_IRQ DMA1_Stream2_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA1 stream3 */
|
||||
#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
|
||||
#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
|
||||
#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
|
||||
#define SPI2_RX_DMA_INSTANCE DMA1_Stream3
|
||||
#define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0
|
||||
#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA1 stream4 */
|
||||
#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
|
||||
#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
|
||||
#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
|
||||
#define SPI2_TX_DMA_INSTANCE DMA1_Stream4
|
||||
#define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0
|
||||
#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA1 stream5 */
|
||||
#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
|
||||
#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler
|
||||
#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
|
||||
#define SPI3_TX_DMA_INSTANCE DMA1_Stream5
|
||||
#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0
|
||||
#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn
|
||||
#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
|
||||
#define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler
|
||||
#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
|
||||
#define UART2_RX_DMA_INSTANCE DMA1_Stream5
|
||||
#define UART2_RX_DMA_CHANNEL DMA_CHANNEL_4
|
||||
#define UART2_RX_DMA_IRQ DMA1_Stream5_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA1 stream6 */
|
||||
|
||||
/* DMA1 stream7 */
|
||||
#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
|
||||
#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
|
||||
#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
|
||||
#define SPI3_TX_DMA_INSTANCE DMA1_Stream7
|
||||
#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0
|
||||
#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA2 stream0 */
|
||||
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
|
||||
#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
|
||||
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define SPI1_RX_DMA_INSTANCE DMA2_Stream0
|
||||
#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
|
||||
#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA2 stream1 */
|
||||
|
||||
/* DMA2 stream2 */
|
||||
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
|
||||
#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
|
||||
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define SPI1_RX_DMA_INSTANCE DMA2_Stream2
|
||||
#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
|
||||
#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
|
||||
#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
|
||||
#define UART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
|
||||
#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define UART1_RX_DMA_INSTANCE DMA2_Stream2
|
||||
#define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4
|
||||
#define UART1_RX_DMA_IRQ DMA2_Stream2_IRQn
|
||||
#elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
|
||||
#define UART6_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
|
||||
#define UART6_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define UART6_RX_DMA_INSTANCE DMA2_Stream2
|
||||
#define UART6_RX_DMA_CHANNEL DMA_CHANNEL_5
|
||||
#define UART6_RX_DMA_IRQ DMA2_Stream2_IRQn
|
||||
#endif
|
||||
/* DMA2 stream3 */
|
||||
|
||||
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
|
||||
#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler
|
||||
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define SPI1_TX_DMA_INSTANCE DMA2_Stream3
|
||||
#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
|
||||
#define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA2 stream4 */
|
||||
|
||||
/* DMA2 stream5 */
|
||||
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
|
||||
#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler
|
||||
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define SPI1_TX_DMA_INSTANCE DMA2_Stream5
|
||||
#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
|
||||
#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn
|
||||
#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
|
||||
#define UART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
|
||||
#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define UART1_RX_DMA_INSTANCE DMA2_Stream5
|
||||
#define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4
|
||||
#define UART1_RX_DMA_IRQ DMA2_Stream5_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA2 stream6 */
|
||||
|
||||
/* DMA2 stream7 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __DMA_CONFIG_H__ */
|
||||
68
libraries/HAL_Drivers/config/f2/pwm_config.h
Normal file
68
libraries/HAL_Drivers/config/f2/pwm_config.h
Normal file
@@ -0,0 +1,68 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-13 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __PWM_CONFIG_H__
|
||||
#define __PWM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM2
|
||||
#ifndef PWM2_CONFIG
|
||||
#define PWM2_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM2, \
|
||||
.name = "pwm2", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM2_CONFIG */
|
||||
#endif /* BSP_USING_PWM2 */
|
||||
|
||||
#ifdef BSP_USING_PWM3
|
||||
#ifndef PWM3_CONFIG
|
||||
#define PWM3_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM3, \
|
||||
.name = "pwm3", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM3_CONFIG */
|
||||
#endif /* BSP_USING_PWM3 */
|
||||
|
||||
#ifdef BSP_USING_PWM4
|
||||
#ifndef PWM4_CONFIG
|
||||
#define PWM4_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM4, \
|
||||
.name = "pwm4", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM4_CONFIG */
|
||||
#endif /* BSP_USING_PWM4 */
|
||||
|
||||
#ifdef BSP_USING_PWM5
|
||||
#ifndef PWM5_CONFIG
|
||||
#define PWM5_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM5, \
|
||||
.name = "pwm5", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM5_CONFIG */
|
||||
#endif /* BSP_USING_PWM5 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PWM_CONFIG_H__ */
|
||||
44
libraries/HAL_Drivers/config/f2/sdio_config.h
Normal file
44
libraries/HAL_Drivers/config/f2/sdio_config.h
Normal file
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-13 BalanceTWK first version
|
||||
*/
|
||||
|
||||
#ifndef __SDIO_CONFIG_H__
|
||||
#define __SDIO_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SDIO
|
||||
#define SDIO_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SDIO, \
|
||||
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
|
||||
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
|
||||
.dma_rx.Instance = DMA2_Stream3, \
|
||||
.dma_rx.channel = DMA_CHANNEL_4, \
|
||||
.dma_rx.dma_irq = DMA2_Stream3_IRQn, \
|
||||
.dma_tx.Instance = DMA2_Stream6, \
|
||||
.dma_tx.channel = DMA_CHANNEL_4, \
|
||||
.dma_tx.dma_irq = DMA2_Stream6_IRQn, \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SDIO_CONFIG_H__ */
|
||||
|
||||
|
||||
|
||||
133
libraries/HAL_Drivers/config/f2/spi_config.h
Normal file
133
libraries/HAL_Drivers/config/f2/spi_config.h
Normal file
@@ -0,0 +1,133 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-06 SummerGift first version
|
||||
* 2019-01-05 SummerGift modify DMA support
|
||||
*/
|
||||
|
||||
#ifndef __SPI_CONFIG_H__
|
||||
#define __SPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SPI1
|
||||
#ifndef SPI1_BUS_CONFIG
|
||||
#define SPI1_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI1, \
|
||||
.bus_name = "spi1", \
|
||||
.irq_type = SPI1_IRQn, \
|
||||
}
|
||||
#endif /* SPI1_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI1 */
|
||||
|
||||
#ifdef BSP_SPI1_TX_USING_DMA
|
||||
#ifndef SPI1_TX_DMA_CONFIG
|
||||
#define SPI1_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI1_TX_DMA_RCC, \
|
||||
.Instance = SPI1_TX_DMA_INSTANCE, \
|
||||
.channel = SPI1_TX_DMA_CHANNEL, \
|
||||
.dma_irq = SPI1_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI1_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI1_RX_USING_DMA
|
||||
#ifndef SPI1_RX_DMA_CONFIG
|
||||
#define SPI1_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI1_RX_DMA_RCC, \
|
||||
.Instance = SPI1_RX_DMA_INSTANCE, \
|
||||
.channel = SPI1_RX_DMA_CHANNEL, \
|
||||
.dma_irq = SPI1_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI1_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI2
|
||||
#ifndef SPI2_BUS_CONFIG
|
||||
#define SPI2_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI2, \
|
||||
.bus_name = "spi2", \
|
||||
.irq_type = SPI2_IRQn, \
|
||||
}
|
||||
#endif /* SPI2_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI2 */
|
||||
|
||||
#ifdef BSP_SPI2_TX_USING_DMA
|
||||
#ifndef SPI2_TX_DMA_CONFIG
|
||||
#define SPI2_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI2_TX_DMA_RCC, \
|
||||
.Instance = SPI2_TX_DMA_INSTANCE, \
|
||||
.channel = SPI2_TX_DMA_CHANNEL, \
|
||||
.dma_irq = SPI2_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI2_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI2_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI2_RX_USING_DMA
|
||||
#ifndef SPI2_RX_DMA_CONFIG
|
||||
#define SPI2_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI2_RX_DMA_RCC, \
|
||||
.Instance = SPI2_RX_DMA_INSTANCE, \
|
||||
.channel = SPI2_RX_DMA_CHANNEL, \
|
||||
.dma_irq = SPI2_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI2_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI2_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI3
|
||||
#ifndef SPI3_BUS_CONFIG
|
||||
#define SPI3_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI3, \
|
||||
.bus_name = "spi3", \
|
||||
.irq_type = SPI3_IRQn, \
|
||||
}
|
||||
#endif /* SPI3_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI3 */
|
||||
|
||||
#ifdef BSP_SPI3_TX_USING_DMA
|
||||
#ifndef SPI3_TX_DMA_CONFIG
|
||||
#define SPI3_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI3_TX_DMA_RCC, \
|
||||
.Instance = SPI3_TX_DMA_INSTANCE, \
|
||||
.channel = SPI3_TX_DMA_CHANNEL, \
|
||||
.dma_irq = SPI3_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI3_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI3_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI3_RX_USING_DMA
|
||||
#ifndef SPI3_RX_DMA_CONFIG
|
||||
#define SPI3_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI3_RX_DMA_RCC, \
|
||||
.Instance = SPI3_RX_DMA_INSTANCE, \
|
||||
.channel = SPI3_RX_DMA_CHANNEL, \
|
||||
.dma_irq = SPI3_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI3_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI3_RX_USING_DMA */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SPI_CONFIG_H__ */
|
||||
|
||||
|
||||
|
||||
89
libraries/HAL_Drivers/config/f2/tim_config.h
Normal file
89
libraries/HAL_Drivers/config/f2/tim_config.h
Normal file
@@ -0,0 +1,89 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-11 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __TIM_CONFIG_H__
|
||||
#define __TIM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef TIM_DEV_INFO_CONFIG
|
||||
#define TIM_DEV_INFO_CONFIG \
|
||||
{ \
|
||||
.maxfreq = 1000000, \
|
||||
.minfreq = 3000, \
|
||||
.maxcnt = 0xFFFF, \
|
||||
.cntmode = HWTIMER_CNTMODE_UP, \
|
||||
}
|
||||
#endif /* TIM_DEV_INFO_CONFIG */
|
||||
|
||||
#ifdef BSP_USING_TIM2
|
||||
#ifndef TIM2_CONFIG
|
||||
#define TIM2_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM2, \
|
||||
.tim_irqn = TIM2_IRQn, \
|
||||
.name = "timer2", \
|
||||
}
|
||||
#endif /* TIM2_CONFIG */
|
||||
#endif /* BSP_USING_TIM2 */
|
||||
|
||||
#ifdef BSP_USING_TIM3
|
||||
#ifndef TIM3_CONFIG
|
||||
#define TIM3_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM3, \
|
||||
.tim_irqn = TIM3_IRQn, \
|
||||
.name = "timer3", \
|
||||
}
|
||||
#endif /* TIM3_CONFIG */
|
||||
#endif /* BSP_USING_TIM3 */
|
||||
|
||||
#ifdef BSP_USING_TIM4
|
||||
#ifndef TIM4_CONFIG
|
||||
#define TIM4_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM4, \
|
||||
.tim_irqn = TIM4_IRQn, \
|
||||
.name = "timer4", \
|
||||
}
|
||||
#endif /* TIM4_CONFIG */
|
||||
#endif /* BSP_USING_TIM4 */
|
||||
|
||||
#ifdef BSP_USING_TIM5
|
||||
#ifndef TIM5_CONFIG
|
||||
#define TIM5_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM5, \
|
||||
.tim_irqn = TIM5_IRQn, \
|
||||
.name = "timer5", \
|
||||
}
|
||||
#endif /* TIM5_CONFIG */
|
||||
#endif /* BSP_USING_TIM5 */
|
||||
|
||||
#ifdef BSP_USING_TIM7
|
||||
#ifndef TIM7_CONFIG
|
||||
#define TIM7_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM7, \
|
||||
.tim_irqn = TIM7_IRQn, \
|
||||
.name = "timer7", \
|
||||
}
|
||||
#endif /* TIM7_CONFIG */
|
||||
#endif /* BSP_USING_TIM7 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __TIM_CONFIG_H__ */
|
||||
235
libraries/HAL_Drivers/config/f2/uart_config.h
Normal file
235
libraries/HAL_Drivers/config/f2/uart_config.h
Normal file
@@ -0,0 +1,235 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-10-30 SummerGift first version
|
||||
* 2019-01-03 zylx modify dma support
|
||||
*/
|
||||
|
||||
#ifndef __UART_CONFIG_H__
|
||||
#define __UART_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_UART1)
|
||||
#ifndef UART1_CONFIG
|
||||
#define UART1_CONFIG \
|
||||
{ \
|
||||
.name = "uart1", \
|
||||
.Instance = USART1, \
|
||||
.irq_type = USART1_IRQn, \
|
||||
}
|
||||
#endif /* UART1_CONFIG */
|
||||
|
||||
#if defined(BSP_UART1_RX_USING_DMA)
|
||||
#ifndef UART1_DMA_RX_CONFIG
|
||||
#define UART1_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART1_RX_DMA_INSTANCE, \
|
||||
.channel = UART1_RX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART1_RX_DMA_RCC, \
|
||||
.dma_irq = UART1_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART1_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART1_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART1_TX_USING_DMA)
|
||||
#ifndef UART1_DMA_TX_CONFIG
|
||||
#define UART1_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART1_TX_DMA_INSTANCE, \
|
||||
.channel = UART1_TX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART1_TX_DMA_RCC, \
|
||||
.dma_irq = UART1_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART1_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART1_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
#ifndef UART2_CONFIG
|
||||
#define UART2_CONFIG \
|
||||
{ \
|
||||
.name = "uart2", \
|
||||
.Instance = USART2, \
|
||||
.irq_type = USART2_IRQn, \
|
||||
}
|
||||
#endif /* UART2_CONFIG */
|
||||
|
||||
#if defined(BSP_UART2_RX_USING_DMA)
|
||||
#ifndef UART2_DMA_RX_CONFIG
|
||||
#define UART2_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART2_RX_DMA_INSTANCE, \
|
||||
.channel = UART2_RX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART2_RX_DMA_RCC, \
|
||||
.dma_irq = UART2_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART2_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART2_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART2_TX_USING_DMA)
|
||||
#ifndef UART2_DMA_TX_CONFIG
|
||||
#define UART2_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART2_TX_DMA_INSTANCE, \
|
||||
.channel = UART2_TX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART2_TX_DMA_RCC, \
|
||||
.dma_irq = UART2_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART2_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART2_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#if defined(BSP_USING_UART3)
|
||||
#ifndef UART3_CONFIG
|
||||
#define UART3_CONFIG \
|
||||
{ \
|
||||
.name = "uart3", \
|
||||
.Instance = USART3, \
|
||||
.irq_type = USART3_IRQn, \
|
||||
}
|
||||
#endif /* UART3_CONFIG */
|
||||
|
||||
#if defined(BSP_UART3_RX_USING_DMA)
|
||||
#ifndef UART3_DMA_RX_CONFIG
|
||||
#define UART3_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART3_RX_DMA_INSTANCE, \
|
||||
.channel = UART3_RX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART3_RX_DMA_RCC, \
|
||||
.dma_irq = UART3_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART3_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART3_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART3_TX_USING_DMA)
|
||||
#ifndef UART3_DMA_TX_CONFIG
|
||||
#define UART3_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART3_TX_DMA_INSTANCE, \
|
||||
.channel = UART3_TX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART3_TX_DMA_RCC, \
|
||||
.dma_irq = UART3_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART3_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART3_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART3 */
|
||||
|
||||
#if defined(BSP_USING_UART4)
|
||||
#ifndef UART4_CONFIG
|
||||
#define UART4_CONFIG \
|
||||
{ \
|
||||
.name = "uart4", \
|
||||
.Instance = UART4, \
|
||||
.irq_type = UART4_IRQn, \
|
||||
}
|
||||
#endif /* UART4_CONFIG */
|
||||
|
||||
#if defined(BSP_UART4_RX_USING_DMA)
|
||||
#ifndef UART4_DMA_RX_CONFIG
|
||||
#define UART4_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART4_RX_DMA_INSTANCE, \
|
||||
.channel = UART4_RX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART4_RX_DMA_RCC, \
|
||||
.dma_irq = UART4_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART4_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART4_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART4_TX_USING_DMA)
|
||||
#ifndef UART4_DMA_TX_CONFIG
|
||||
#define UART4_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART4_TX_DMA_INSTANCE, \
|
||||
.channel = UART4_TX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART4_TX_DMA_RCC, \
|
||||
.dma_irq = UART4_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART4_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART4_RX_USING_DMA */
|
||||
#endif /* BSP_USING_UART4 */
|
||||
|
||||
#if defined(BSP_USING_UART5)
|
||||
#ifndef UART5_CONFIG
|
||||
#define UART5_CONFIG \
|
||||
{ \
|
||||
.name = "uart5", \
|
||||
.Instance = UART5, \
|
||||
.irq_type = UART5_IRQn, \
|
||||
}
|
||||
#endif /* UART5_CONFIG */
|
||||
|
||||
#if defined(BSP_UART5_RX_USING_DMA)
|
||||
#ifndef UART5_DMA_RX_CONFIG
|
||||
#define UART5_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART5_RX_DMA_INSTANCE, \
|
||||
.channel = UART5_RX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART5_RX_DMA_RCC, \
|
||||
.dma_irq = UART5_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART5_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART5_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART5_TX_USING_DMA)
|
||||
#ifndef UART5_DMA_TX_CONFIG
|
||||
#define UART5_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART5_TX_DMA_INSTANCE, \
|
||||
.channel = UART5_TX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART5_TX_DMA_RCC, \
|
||||
.dma_irq = UART5_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART5_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART5_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART5 */
|
||||
|
||||
#if defined(BSP_USING_UART6)
|
||||
#ifndef UART6_CONFIG
|
||||
#define UART6_CONFIG \
|
||||
{ \
|
||||
.name = "uart6", \
|
||||
.Instance = USART6, \
|
||||
.irq_type = USART6_IRQn, \
|
||||
}
|
||||
#endif /* UART6_CONFIG */
|
||||
|
||||
#if defined(BSP_UART6_RX_USING_DMA)
|
||||
#ifndef UART6_DMA_RX_CONFIG
|
||||
#define UART6_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART6_RX_DMA_INSTANCE, \
|
||||
.channel = UART6_RX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART6_RX_DMA_RCC, \
|
||||
.dma_irq = UART6_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART6_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART6_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART6_TX_USING_DMA)
|
||||
#ifndef UART6_DMA_TX_CONFIG
|
||||
#define UART6_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART6_TX_DMA_INSTANCE, \
|
||||
.channel = UART6_TX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART6_TX_DMA_RCC, \
|
||||
.dma_irq = UART6_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART6_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART6_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART6 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user