From 43963583eab203155daf5332c390b88cb929b16d Mon Sep 17 00:00:00 2001 From: a1012112796 <1012112796@qq.com> Date: Fri, 14 Oct 2022 11:16:02 +0800 Subject: [PATCH] =?UTF-8?q?=E7=BC=96=E8=AF=91=20lib=20=E5=88=9D=E6=AD=A5?= =?UTF-8?q?=E5=AE=9E=E7=8E=B0?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: a1012112796 <1012112796@qq.com> --- applications/SConscript | 12 - applications/main.c | 36 - libraries/HAL_Drivers/drv_common.c | 2 +- libraries/HAL_Drivers/drv_usart.c | 4 - .../Src/stm32f4xx_hal_uart.c | 28 +- move_lib.bat | 1 + project.uvoptx | 302 ++- project.uvprojx | 24 +- rt-thread/libcpu/arm/AT91SAM7S/AT91SAM7S.h | 293 --- rt-thread/libcpu/arm/AT91SAM7S/SConscript | 23 - rt-thread/libcpu/arm/AT91SAM7S/context_gcc.S | 90 - rt-thread/libcpu/arm/AT91SAM7S/context_rvds.S | 103 -- rt-thread/libcpu/arm/AT91SAM7S/cpu.c | 38 - rt-thread/libcpu/arm/AT91SAM7S/interrupt.c | 87 - rt-thread/libcpu/arm/AT91SAM7S/serial.c | 383 ---- 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a/applications/SConscript +++ /dev/null @@ -1,12 +0,0 @@ -import rtconfig -from building import * - -cwd = GetCurrentDir() -CPPPATH = [cwd, str(Dir('#'))] -src = Split(""" -main.c -""") - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/applications/main.c b/applications/main.c deleted file mode 100644 index aff1f2a..0000000 --- a/applications/main.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-11-06 SummerGift first version - */ - -#include -#include -#include - -/* defined the LED1 pin: PB0 */ -#define LED1_PIN GET_PIN(C, 13) -/* defined the LED2 pin: PB7 */ -#define LED2_PIN GET_PIN(B, 7) -/* defined the LED3 pin: PB14 */ -#define LED3_PIN GET_PIN(B, 14) -/* defined the USER KEY pin: PC13 */ -#define KEY_PIN GET_PIN(C, 13) - -int main(void) -{ - /* set LED1 pin mode to output */ - rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - - while (1) - { - rt_pin_write(LED1_PIN, PIN_HIGH); - rt_thread_mdelay(500); - rt_pin_write(LED1_PIN, PIN_LOW); - rt_thread_mdelay(500); - } -} diff --git a/libraries/HAL_Drivers/drv_common.c b/libraries/HAL_Drivers/drv_common.c index 07ac152..2f08260 100644 --- a/libraries/HAL_Drivers/drv_common.c +++ b/libraries/HAL_Drivers/drv_common.c @@ -164,7 +164,7 @@ void rt_hw_us_delay(rt_uint32_t us) /** * This function will initial STM32 board. */ -RT_WEAK void rt_hw_board_init(void) +void rt_hw_board_init(void) { #ifdef BSP_SCB_ENABLE_I_CACHE /* Enable I-Cache---------------------------------------------------------*/ diff --git a/libraries/HAL_Drivers/drv_usart.c b/libraries/HAL_Drivers/drv_usart.c index addd5da..d3f7561 100644 --- a/libraries/HAL_Drivers/drv_usart.c +++ b/libraries/HAL_Drivers/drv_usart.c @@ -422,10 +422,6 @@ static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag) static void uart_isr(struct rt_serial_device *serial) { struct stm32_uart *uart; -#ifdef RT_SERIAL_USING_DMA - rt_size_t recv_total_index, recv_len; - rt_base_t level; -#endif RT_ASSERT(serial != RT_NULL); uart = rt_container_of(serial, struct stm32_uart, serial); diff --git a/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c b/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c index 36b7317..b32dacc 100644 --- a/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c +++ b/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c @@ -701,20 +701,20 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) return HAL_OK; } -/** - * @brief UART MSP Init. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_MspInit could be implemented in the user file - */ -} +// /** +// * @brief UART MSP Init. +// * @param huart Pointer to a UART_HandleTypeDef structure that contains +// * the configuration information for the specified UART module. +// * @retval None +// */ +// __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +// { +// /* Prevent unused argument(s) compilation warning */ +// UNUSED(huart); +// /* NOTE: This function should not be modified, when the callback is needed, +// the HAL_UART_MspInit could be implemented in the user file +// */ +// } /** * @brief UART MSP DeInit. diff --git a/move_lib.bat b/move_lib.bat new file mode 100644 index 0000000..9d7bee6 --- /dev/null +++ b/move_lib.bat @@ -0,0 +1 @@ +copy .\build\*.lib ..\F405_Sharelib\lib \ No newline at end of file diff --git a/project.uvoptx b/project.uvoptx index c822972..a95cb73 100644 --- a/project.uvoptx +++ b/project.uvoptx @@ -117,26 +117,6 @@ Segger\JL2CM3.dll - - 0 - ARMRTXEVENTFLAGS - -L70 -Z18 -C0 -M0 -T1 - - - 0 - DLGTARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) - - - 0 - ARMDBGFLAGS - - - - 0 - DLGUARM - - 0 JL2CM3 @@ -160,12 +140,12 @@ 0 0 - 1 + 0 0 0 0 0 - 1 + 0 0 0 0 @@ -207,7 +187,7 @@ - Applications + Compiler 0 0 0 @@ -219,34 +199,14 @@ 0 0 0 - applications\main.c - main.c - 0 - 0 - - - - - Compiler - 0 - 0 - 0 - 0 - - 2 - 2 - 1 - 0 - 0 - 0 rt-thread\components\libc\compilers\armlibc\syscall_mem.c syscall_mem.c 0 0 - 2 - 3 + 1 + 2 1 0 0 @@ -257,8 +217,8 @@ 0 - 2 - 4 + 1 + 3 1 0 0 @@ -269,8 +229,8 @@ 0 - 2 - 5 + 1 + 4 1 0 0 @@ -281,8 +241,8 @@ 0 - 2 - 6 + 1 + 5 1 0 0 @@ -293,8 +253,8 @@ 0 - 2 - 7 + 1 + 6 1 0 0 @@ -305,8 +265,8 @@ 0 - 2 - 8 + 1 + 7 1 0 0 @@ -317,8 +277,8 @@ 0 - 2 - 9 + 1 + 8 1 0 0 @@ -337,8 +297,8 @@ 0 0 - 3 - 10 + 2 + 9 1 0 0 @@ -349,8 +309,8 @@ 0 - 3 - 11 + 2 + 10 1 0 0 @@ -361,8 +321,8 @@ 0 - 3 - 12 + 2 + 11 1 0 0 @@ -373,8 +333,8 @@ 0 - 3 - 13 + 2 + 12 2 0 0 @@ -385,8 +345,8 @@ 0 - 3 - 14 + 2 + 13 1 0 0 @@ -405,8 +365,8 @@ 0 0 - 4 - 15 + 3 + 14 1 0 0 @@ -417,8 +377,8 @@ 0 - 4 - 16 + 3 + 15 1 0 0 @@ -429,8 +389,8 @@ 0 - 4 - 17 + 3 + 16 1 0 0 @@ -441,8 +401,8 @@ 0 - 4 - 18 + 3 + 17 1 0 0 @@ -453,8 +413,8 @@ 0 - 4 - 19 + 3 + 18 1 0 0 @@ -465,8 +425,8 @@ 0 - 4 - 20 + 3 + 19 1 0 0 @@ -477,8 +437,8 @@ 0 - 4 - 21 + 3 + 20 1 0 0 @@ -489,8 +449,8 @@ 0 - 4 - 22 + 3 + 21 1 0 0 @@ -501,8 +461,8 @@ 0 - 4 - 23 + 3 + 22 1 0 0 @@ -513,8 +473,8 @@ 0 - 4 - 24 + 3 + 23 1 0 0 @@ -533,8 +493,8 @@ 0 0 - 5 - 25 + 4 + 24 1 0 0 @@ -545,8 +505,8 @@ 0 - 5 - 26 + 4 + 25 1 0 0 @@ -557,8 +517,8 @@ 0 - 5 - 27 + 4 + 26 2 0 0 @@ -569,8 +529,8 @@ 0 - 5 - 28 + 4 + 27 1 0 0 @@ -581,8 +541,8 @@ 0 - 5 - 29 + 4 + 28 1 0 0 @@ -593,8 +553,8 @@ 0 - 5 - 30 + 4 + 29 1 0 0 @@ -613,8 +573,8 @@ 0 0 - 6 - 31 + 5 + 30 1 0 0 @@ -625,8 +585,8 @@ 0 - 6 - 32 + 5 + 31 1 0 0 @@ -637,8 +597,8 @@ 0 - 6 - 33 + 5 + 32 1 0 0 @@ -649,8 +609,8 @@ 0 - 6 - 34 + 5 + 33 1 0 0 @@ -669,8 +629,8 @@ 0 0 - 7 - 35 + 6 + 34 1 0 0 @@ -681,8 +641,8 @@ 0 - 7 - 36 + 6 + 35 1 0 0 @@ -693,8 +653,8 @@ 0 - 7 - 37 + 6 + 36 1 0 0 @@ -705,8 +665,8 @@ 0 - 7 - 38 + 6 + 37 1 0 0 @@ -717,8 +677,8 @@ 0 - 7 - 39 + 6 + 38 1 0 0 @@ -729,8 +689,8 @@ 0 - 7 - 40 + 6 + 39 1 0 0 @@ -741,8 +701,8 @@ 0 - 7 - 41 + 6 + 40 1 0 0 @@ -753,8 +713,8 @@ 0 - 7 - 42 + 6 + 41 1 0 0 @@ -765,8 +725,8 @@ 0 - 7 - 43 + 6 + 42 1 0 0 @@ -777,8 +737,8 @@ 0 - 7 - 44 + 6 + 43 1 0 0 @@ -789,8 +749,8 @@ 0 - 7 - 45 + 6 + 44 1 0 0 @@ -801,8 +761,8 @@ 0 - 7 - 46 + 6 + 45 1 0 0 @@ -813,8 +773,8 @@ 0 - 7 - 47 + 6 + 46 1 0 0 @@ -833,8 +793,8 @@ 0 0 - 8 - 48 + 7 + 47 1 0 0 @@ -845,8 +805,8 @@ 0 - 8 - 49 + 7 + 48 1 0 0 @@ -857,8 +817,8 @@ 0 - 8 - 50 + 7 + 49 1 0 0 @@ -869,8 +829,8 @@ 0 - 8 - 51 + 7 + 50 1 0 0 @@ -881,8 +841,8 @@ 0 - 8 - 52 + 7 + 51 1 0 0 @@ -893,8 +853,8 @@ 0 - 8 - 53 + 7 + 52 1 0 0 @@ -905,8 +865,8 @@ 0 - 8 - 54 + 7 + 53 1 0 0 @@ -917,8 +877,8 @@ 0 - 8 - 55 + 7 + 54 1 0 0 @@ -929,8 +889,8 @@ 0 - 8 - 56 + 7 + 55 1 0 0 @@ -941,8 +901,8 @@ 0 - 8 - 57 + 7 + 56 1 0 0 @@ -953,8 +913,8 @@ 0 - 8 - 58 + 7 + 57 1 0 0 @@ -965,8 +925,8 @@ 0 - 8 - 59 + 7 + 58 1 0 0 @@ -977,8 +937,8 @@ 0 - 8 - 60 + 7 + 59 1 0 0 @@ -989,8 +949,8 @@ 0 - 8 - 61 + 7 + 60 1 0 0 @@ -1001,8 +961,8 @@ 0 - 8 - 62 + 7 + 61 1 0 0 @@ -1013,8 +973,8 @@ 0 - 8 - 63 + 7 + 62 1 0 0 @@ -1025,8 +985,8 @@ 0 - 8 - 64 + 7 + 63 1 0 0 @@ -1037,8 +997,8 @@ 0 - 8 - 65 + 7 + 64 1 0 0 @@ -1049,8 +1009,8 @@ 0 - 8 - 66 + 7 + 65 1 0 0 diff --git a/project.uvprojx b/project.uvprojx index 8df8d15..f83bc58 100644 --- a/project.uvprojx +++ b/project.uvprojx @@ -10,7 +10,7 @@ rt-thread 0x4 ARM-ADS - 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060750::V5.06 update 6 (build 750)::ARMCC 0 @@ -48,10 +48,10 @@ 0 1 - .\build\keil\Obj\ - rt-thread - 1 - 0 + .\build\ + F413_RTT + 0 + 1 0 1 0 @@ -82,7 +82,7 @@ 1 0 - fromelf --bin !L --output rtthread.bin + E:\xyfc\413\work\stm32f413\move_lib.bat 0 0 @@ -339,7 +339,7 @@ __STDC_LIMIT_MACROS, STM32F413xx, USE_HAL_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, RT_USING_ARM_LIBC - rt-thread\components\drivers\include;rt-thread\components\libc\compilers\common\include;libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;libraries\HAL_Drivers\CMSIS\Include;libraries\HAL_Drivers\config;rt-thread\components\drivers\include;rt-thread\include;rt-thread\components\finsh;rt-thread\components\libc\compilers\common\extension\fcntl\octal;board;rt-thread\components\drivers\include;libraries\HAL_Drivers;rt-thread\components\drivers\include;libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;.;applications;rt-thread\libcpu\arm\common;rt-thread\components\libc\compilers\common\extension;rt-thread\components\libc\posix\io\stdio;rt-thread\components\libc\posix\io\poll;rt-thread\libcpu\arm\cortex-m4;rt-thread\components\libc\posix\ipc;board\CubeMX_Config\Inc + rt-thread\components\drivers\include;rt-thread\components\libc\posix\io\poll;libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;.;board\CubeMX_Config\Inc;rt-thread\components\libc\posix\ipc;libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;rt-thread\components\libc\compilers\common\include;libraries\HAL_Drivers;rt-thread\components\drivers\include;rt-thread\components\libc\compilers\common\extension\fcntl\octal;board;rt-thread\components\libc\posix\io\stdio;rt-thread\libcpu\arm\common;rt-thread\components\drivers\include;rt-thread\include;rt-thread\components\libc\compilers\common\extension;libraries\HAL_Drivers\config;rt-thread\components\finsh;rt-thread\libcpu\arm\cortex-m4;rt-thread\components\drivers\include;libraries\HAL_Drivers\CMSIS\Include @@ -380,16 +380,6 @@ - - Applications - - - main.c - 1 - applications\main.c - - - Compiler diff --git a/rt-thread/libcpu/arm/AT91SAM7S/AT91SAM7S.h b/rt-thread/libcpu/arm/AT91SAM7S/AT91SAM7S.h deleted file mode 100644 index 91b5705..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7S/AT91SAM7S.h +++ /dev/null @@ -1,293 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-08-23 Bernard first version - */ - -#ifndef __AT91SAM7S_H__ -#define __AT91SAM7S_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#define AT91_REG *(volatile unsigned int *) /* Hardware register definition */ - -/* ========== Register definition for TC0 peripheral ========== */ -#define AT91C_TC0_SR (AT91_REG(0xFFFA0020)) /* TC0 Status Register */ -#define AT91C_TC0_RC (AT91_REG(0xFFFA001C)) /* TC0 Register C */ -#define AT91C_TC0_RB (AT91_REG(0xFFFA0018)) /* TC0 Register B */ -#define AT91C_TC0_CCR (AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */ -#define AT91C_TC0_CMR (AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC0_IER (AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */ -#define AT91C_TC0_RA (AT91_REG(0xFFFA0014)) /* TC0 Register A */ -#define AT91C_TC0_IDR (AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */ -#define AT91C_TC0_CV (AT91_REG(0xFFFA0010)) /* TC0 Counter Value */ -#define AT91C_TC0_IMR (AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */ - -/* ========== Register definition for TC1 peripheral ========== */ -#define AT91C_TC1_RB (AT91_REG(0xFFFA0058)) /* TC1 Register B */ -#define AT91C_TC1_CCR (AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */ -#define AT91C_TC1_IER (AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */ -#define AT91C_TC1_IDR (AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */ -#define AT91C_TC1_SR (AT91_REG(0xFFFA0060)) /* TC1 Status Register */ -#define AT91C_TC1_CMR (AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC1_RA (AT91_REG(0xFFFA0054)) /* TC1 Register A */ -#define AT91C_TC1_RC (AT91_REG(0xFFFA005C)) /* TC1 Register C */ -#define AT91C_TC1_IMR (AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */ -#define AT91C_TC1_CV (AT91_REG(0xFFFA0050)) /* TC1 Counter Value */ - -/* ========== Register definition for TC2 peripheral ========== */ -#define AT91C_TC2_CMR (AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC2_CCR (AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */ -#define AT91C_TC2_CV (AT91_REG(0xFFFA0090)) /* TC2 Counter Value */ -#define AT91C_TC2_RA (AT91_REG(0xFFFA0094)) /* TC2 Register A */ -#define AT91C_TC2_RB (AT91_REG(0xFFFA0098)) /* TC2 Register B */ -#define AT91C_TC2_IDR (AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */ -#define AT91C_TC2_IMR (AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */ -#define AT91C_TC2_RC (AT91_REG(0xFFFA009C)) /* TC2 Register C */ -#define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ -#define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ - -/* ========== Register definition for PITC peripheral ========== */ -#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ -#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ -#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ -#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ - -/* ========== Register definition for UDP peripheral ========== */ -#define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ -#define AT91C_UDP_STAT (AT91_REG(0xFFFB0004)) /* UDP Global State Register */ -#define AT91C_UDP_FADDR (AT91_REG(0xFFFB0008)) /* UDP Function Address Register */ -#define AT91C_UDP_IER (AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */ -#define AT91C_UDP_IDR (AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */ -#define AT91C_UDP_IMR (AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */ -#define AT91C_UDP_ISR (AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */ -#define AT91C_UDP_ICR (AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */ -#define AT91C_UDP_RSTEP (AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */ -#define AT91C_UDP_CSR0 (AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */ -#define AT91C_UDP_CSR(n) (*(&AT91C_UDP_CSR0 + n)) -#define AT91C_UDP_FDR0 (AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */ -#define AT91C_UDP_FDR(n) (*(&AT91C_UDP_FDR0 + n)) -#define AT91C_UDP_TXVC (AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */ - -/* ========== Register definition for US0 peripheral ========== */ -#define AT91C_US0_CR (AT91_REG(0xFFFC0000)) /* US0 Control Register */ -#define AT91C_US0_MR (AT91_REG(0xFFFC0004)) /* US0 Mode Register */ -#define AT91C_US0_IER (AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */ -#define AT91C_US0_IDR (AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */ -#define AT91C_US0_IMR (AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */ -#define AT91C_US0_CSR (AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */ -#define AT91C_US0_RHR (AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */ -#define AT91C_US0_THR (AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */ -#define AT91C_US0_BRGR (AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */ -#define AT91C_US0_RTOR (AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */ -#define AT91C_US0_TTGR (AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */ -#define AT91C_US0_NER (AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */ -#define AT91C_US0_FIDI (AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */ -#define AT91C_US0_IF (AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */ - -/* ========== Register definition for AIC peripheral ========== */ -#define AT91C_AIC_SMR0 (AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */ -#define AT91C_AIC_SMR(n) (*(&AT91C_AIC_SMR0 + n)) -#define AT91C_AIC_SVR0 (AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */ -#define AT91C_AIC_SVR(n) (*(&AT91C_AIC_SVR0 + n)) -#define AT91C_AIC_IVR (AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */ -#define AT91C_AIC_FVR (AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */ -#define AT91C_AIC_ISR (AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */ -#define AT91C_AIC_IPR (AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */ -#define AT91C_AIC_IMR (AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */ -#define AT91C_AIC_CISR (AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */ -#define AT91C_AIC_IECR (AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */ -#define AT91C_AIC_IDCR (AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */ -#define AT91C_AIC_ICCR (AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */ -#define AT91C_AIC_ISCR (AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */ -#define AT91C_AIC_EOICR (AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */ -#define AT91C_AIC_SPU (AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */ -#define AT91C_AIC_DCR (AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */ -#define AT91C_AIC_FFER (AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */ -#define AT91C_AIC_FFDR (AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */ -#define AT91C_AIC_FFSR (AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */ - - -/* ========== Register definition for DBGU peripheral ========== */ -#define AT91C_DBGU_EXID (AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */ -#define AT91C_DBGU_BRGR (AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */ -#define AT91C_DBGU_IDR (AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */ -#define AT91C_DBGU_CSR (AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */ -#define AT91C_DBGU_CIDR (AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */ -#define AT91C_DBGU_MR (AT91_REG(0xFFFFF204)) /* DBGU Mode Register */ -#define AT91C_DBGU_IMR (AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */ -#define AT91C_DBGU_CR (AT91_REG(0xFFFFF200)) /* DBGU Control Register */ -#define AT91C_DBGU_FNTR (AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */ -#define AT91C_DBGU_THR (AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */ -#define AT91C_DBGU_RHR (AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */ -#define AT91C_DBGU_IER (AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */ - -/* ========== Register definition for PIO peripheral ========== */ -#define AT91C_PIO_ODR (AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */ -#define AT91C_PIO_SODR (AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */ -#define AT91C_PIO_ISR (AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */ -#define AT91C_PIO_ABSR (AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */ -#define AT91C_PIO_IER (AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */ -#define AT91C_PIO_PPUDR (AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */ -#define AT91C_PIO_IMR (AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */ -#define AT91C_PIO_PER (AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */ -#define AT91C_PIO_IFDR (AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */ -#define AT91C_PIO_OWDR (AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */ -#define AT91C_PIO_MDSR (AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */ -#define AT91C_PIO_IDR (AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */ -#define AT91C_PIO_ODSR (AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */ -#define AT91C_PIO_PPUSR (AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */ -#define AT91C_PIO_OWSR (AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */ -#define AT91C_PIO_BSR (AT91_REG(0xFFFFF474)) /* PIOA Select B Register */ -#define AT91C_PIO_OWER (AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */ -#define AT91C_PIO_IFER (AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */ -#define AT91C_PIO_PDSR (AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */ -#define AT91C_PIO_PPUER (AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */ -#define AT91C_PIO_OSR (AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */ -#define AT91C_PIO_ASR (AT91_REG(0xFFFFF470)) /* PIOA Select A Register */ -#define AT91C_PIO_MDDR (AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */ -#define AT91C_PIO_CODR (AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */ -#define AT91C_PIO_MDER (AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */ -#define AT91C_PIO_PDR (AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */ -#define AT91C_PIO_IFSR (AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */ -#define AT91C_PIO_OER (AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */ -#define AT91C_PIO_PSR (AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */ - -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_IMR (AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_IER (AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_OWDR (AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_ISR (AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PPUDR (AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_MDSR (AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_MDER (AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PER (AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register -#define AT91C_PIOA_PSR (AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register -#define AT91C_PIOA_OER (AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register -#define AT91C_PIOA_BSR (AT91_REG(0xFFFFF474)) // (PIOA) Select B Register -#define AT91C_PIOA_PPUER (AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_MDDR (AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_PDR (AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register -#define AT91C_PIOA_ODR (AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_IFDR (AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_ABSR (AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register -#define AT91C_PIOA_ASR (AT91_REG(0xFFFFF470)) // (PIOA) Select A Register -#define AT91C_PIOA_PPUSR (AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_ODSR (AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SODR (AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register -#define AT91C_PIOA_IFSR (AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_IFER (AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_OSR (AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register -#define AT91C_PIOA_IDR (AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_PDSR (AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_CODR (AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_OWSR (AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register -#define AT91C_PIOA_OWER (AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWSR (AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PPUSR (AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_PPUDR (AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_MDSR (AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_MDER (AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_IMR (AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_OSR (AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register -#define AT91C_PIOB_OER (AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register -#define AT91C_PIOB_PSR (AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register -#define AT91C_PIOB_PER (AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register -#define AT91C_PIOB_BSR (AT91_REG(0xFFFFF674)) // (PIOB) Select B Register -#define AT91C_PIOB_PPUER (AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_IFDR (AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_ODR (AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_ABSR (AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register -#define AT91C_PIOB_ASR (AT91_REG(0xFFFFF670)) // (PIOB) Select A Register -#define AT91C_PIOB_IFER (AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_IFSR (AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_SODR (AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ODSR (AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register -#define AT91C_PIOB_CODR (AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_PDSR (AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_OWER (AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_IER (AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_OWDR (AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDDR (AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_ISR (AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_IDR (AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_PDR (AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register - -/* ========== Register definition for PMC peripheral ========== */ -#define AT91C_PMC_SCER (AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */ -#define AT91C_PMC_SCDR (AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */ -#define AT91C_PMC_SCSR (AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */ -#define AT91C_PMC_PCER (AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */ -#define AT91C_PMC_PCDR (AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */ -#define AT91C_PMC_PCSR (AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */ -#define AT91C_PMC_MOR (AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */ -#define AT91C_PMC_MCFR (AT91_REG(0xFFFFFC24)) /* PMC Main Clock Frequency Register */ -#define AT91C_PMC_PLLR (AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */ -#define AT91C_PMC_MCKR (AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */ -#define AT91C_PMC_PCKR (AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */ -#define AT91C_PMC_IER (AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */ -#define AT91C_PMC_IDR (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */ -#define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ -#define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ - -/******************************************************************************/ -/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */ -/******************************************************************************/ -#define AT91C_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91C_ID_SYS 1 /* System Peripheral */ -#define AT91C_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91C_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91C_ID_ADC 4 /* Analog-to-Digital Converter */ -#define AT91C_ID_SPI 5 /* Serial Peripheral Interface */ -#define AT91C_ID_US0 6 /* USART 0 */ -#define AT91C_ID_US1 7 /* USART 1 */ -#define AT91C_ID_SSC 8 /* Serial Synchronous Controller */ -#define AT91C_ID_TWI 9 /* Two-Wire Interface */ -#define AT91C_ID_PWMC 10 /* PWM Controller */ -#define AT91C_ID_UDP 11 /* USB Device Port */ -#define AT91C_ID_TC0 12 /* Timer Counter 0 */ -#define AT91C_ID_TC1 13 /* Timer Counter 1 */ -#define AT91C_ID_TC2 14 /* Timer Counter 2 */ -#define AT91C_ID_15 15 /* Reserved */ -#define AT91C_ID_16 16 /* Reserved */ -#define AT91C_ID_17 17 /* Reserved */ -#define AT91C_ID_18 18 /* Reserved */ -#define AT91C_ID_19 19 /* Reserved */ -#define AT91C_ID_20 20 /* Reserved */ -#define AT91C_ID_21 21 /* Reserved */ -#define AT91C_ID_22 22 /* Reserved */ -#define AT91C_ID_23 23 /* Reserved */ -#define AT91C_ID_24 24 /* Reserved */ -#define AT91C_ID_25 25 /* Reserved */ -#define AT91C_ID_26 26 /* Reserved */ -#define AT91C_ID_27 27 /* Reserved */ -#define AT91C_ID_28 28 /* Reserved */ -#define AT91C_ID_29 29 /* Reserved */ -#define AT91C_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91C_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91C_ALL_INT 0xC0007FF7 /* ALL VALID INTERRUPTS */ - -/*****************************/ -/* CPU Mode */ -/*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/rt-thread/libcpu/arm/AT91SAM7S/SConscript b/rt-thread/libcpu/arm/AT91SAM7S/SConscript deleted file mode 100644 index b259a94..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7S/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/AT91SAM7S/context_gcc.S b/rt-thread/libcpu/arm/AT91SAM7S/context_gcc.S deleted file mode 100644 index b2629a6..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7S/context_gcc.S +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - */ - -#define NOINT 0xc0 - -/* - * rt_base_t rt_hw_interrupt_disable()/* - */ -.globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mrs r0, cpsr - orr r1, r0, #NOINT - msr cpsr_c, r1 - mov pc, lr - -/* - * void rt_hw_interrupt_enable(rt_base_t level)/* - */ -.globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - msr cpsr, r0 - mov pc, lr - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)/* - * r0 --> from - * r1 --> to - */ -.globl rt_hw_context_switch -rt_hw_context_switch: - stmfd sp!, {lr} /* push pc (lr should be pushed in place of PC) */ - stmfd sp!, {r0-r12, lr} /* push lr & register file */ - - mrs r4, cpsr - stmfd sp!, {r4} /* push cpsr */ - mrs r4, spsr - stmfd sp!, {r4} /* push spsr */ - - str sp, [r0] /* store sp in preempted tasks TCB */ - ldr sp, [r1] /* get new task stack pointer */ - - ldmfd sp!, {r4} /* pop new task spsr */ - msr spsr_cxsf, r4 - ldmfd sp!, {r4} /* pop new task cpsr */ - msr cpsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc} /* pop new task r0-r12, lr & pc */ - -/* - * void rt_hw_context_switch_to(rt_uint32 to)/* - * r0 --> to - */ -.globl rt_hw_context_switch_to -rt_hw_context_switch_to: - ldr sp, [r0] /* get new task stack pointer */ - - ldmfd sp!, {r4} /* pop new task spsr */ - msr spsr_cxsf, r4 - ldmfd sp!, {r4} /* pop new task cpsr */ - msr cpsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc} /* pop new task r0-r12, lr & pc */ - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* - */ -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -.globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - ldr r2, =rt_thread_switch_interrupt_flag - ldr r3, [r2] - cmp r3, #1 - beq _reswitch - mov r3, #1 /* set rt_thread_switch_interrupt_flag to 1 */ - str r3, [r2] - ldr r2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - str r0, [r2] -_reswitch: - ldr r2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - str r1, [r2] - mov pc, lr diff --git a/rt-thread/libcpu/arm/AT91SAM7S/context_rvds.S b/rt-thread/libcpu/arm/AT91SAM7S/context_rvds.S deleted file mode 100644 index 3cc70c7..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7S/context_rvds.S +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-01-20 Bernard first version - */ - -NOINT EQU 0xc0 ; disable interrupt in psr - - AREA |.text|, CODE, READONLY, ALIGN=2 - ARM - REQUIRE8 - PRESERVE8 - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ -rt_hw_interrupt_disable PROC - EXPORT rt_hw_interrupt_disable - MRS r0, cpsr - ORR r1, r0, #NOINT - MSR cpsr_c, r1 - BX lr - ENDP - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ -rt_hw_interrupt_enable PROC - EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0 - BX lr - ENDP - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ -rt_hw_context_switch PROC - EXPORT rt_hw_context_switch - STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC) - STMFD sp!, {r0-r12, lr} ; push lr & register file - - MRS r4, cpsr - STMFD sp!, {r4} ; push cpsr - MRS r4, spsr - STMFD sp!, {r4} ; push spsr - - STR sp, [r0] ; store sp in preempted tasks TCB - LDR sp, [r1] ; get new task stack pointer - - LDMFD sp!, {r4} ; pop new task spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task cpsr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; */ -rt_hw_context_switch_to PROC - EXPORT rt_hw_context_switch_to - LDR sp, [r0] ; get new task stack pointer - - LDMFD sp!, {r4} ; pop new task spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task cpsr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP - -;/* -; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); -; */ - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -rt_hw_context_switch_interrupt PROC - EXPORT rt_hw_context_switch_interrupt - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1 - STR r3, [r2] - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - BX lr - ENDP - - END diff --git a/rt-thread/libcpu/arm/AT91SAM7S/cpu.c b/rt-thread/libcpu/arm/AT91SAM7S/cpu.c deleted file mode 100644 index 18d8d62..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7S/cpu.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-08-23 Bernard first version - */ - -#include -#include "AT91SAM7S.h" - -/** - * @addtogroup AT91SAM7 - */ -/*@{*/ - -/** - * this function will reset CPU - * - */ -RT_WEAK void rt_hw_cpu_reset() -{ -} - -/** - * this function will shutdown CPU - * - */ -RT_WEAK void rt_hw_cpu_shutdown() -{ - rt_kprintf("shutdown...\n"); - - while (1); -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/AT91SAM7S/interrupt.c b/rt-thread/libcpu/arm/AT91SAM7S/interrupt.c deleted file mode 100644 index e4aa864..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7S/interrupt.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-08-23 Bernard first version - */ - -#include -#include "AT91SAM7S.h" - -#define MAX_HANDLERS 32 - -extern rt_uint32_t rt_interrupt_nest; - -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -/** - * @addtogroup AT91SAM7 - */ -/*@{*/ - -void rt_hw_interrupt_handler(int vector) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init() -{ - rt_base_t index; - - for (index = 0; index < MAX_HANDLERS; index ++) - { - AT91C_AIC_SVR(index) = (rt_uint32_t)rt_hw_interrupt_handler; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - /* disable interrupt */ - AT91C_AIC_IDCR = 1 << vector; - - /* clear interrupt */ - AT91C_AIC_ICCR = 1 << vector; -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - AT91C_AIC_IECR = 1 << vector; -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param new_handler the interrupt service routine to be installed - * @param old_handler the old interrupt service routine - */ -void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) -{ - if(vector >= 0 && vector < MAX_HANDLERS) - { - if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)AT91C_AIC_SVR(vector); - if (new_handler != RT_NULL) AT91C_AIC_SVR(vector) = (rt_uint32_t)new_handler; - } -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/AT91SAM7S/serial.c b/rt-thread/libcpu/arm/AT91SAM7S/serial.c deleted file mode 100644 index 583443f..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7S/serial.c +++ /dev/null @@ -1,383 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-08-23 Bernard first version - * 2009-05-14 Bernard add RT-THread device interface - */ - -#include -#include - -#include "AT91SAM7S.h" -#include "serial.h" - -/** - * @addtogroup AT91SAM7 - */ -/*@{*/ -typedef volatile rt_uint32_t REG32; -struct rt_at91serial_hw -{ - REG32 US_CR; // Control Register - REG32 US_MR; // Mode Register - REG32 US_IER; // Interrupt Enable Register - REG32 US_IDR; // Interrupt Disable Register - REG32 US_IMR; // Interrupt Mask Register - REG32 US_CSR; // Channel Status Register - REG32 US_RHR; // Receiver Holding Register - REG32 US_THR; // Transmitter Holding Register - REG32 US_BRGR; // Baud Rate Generator Register - REG32 US_RTOR; // Receiver Time-out Register - REG32 US_TTGR; // Transmitter Time-guard Register - REG32 Reserved0[5]; // - REG32 US_FIDI; // FI_DI_Ratio Register - REG32 US_NER; // Nb Errors Register - REG32 Reserved1[1]; // - REG32 US_IF; // IRDA_FILTER Register - REG32 Reserved2[44]; // - REG32 US_RPR; // Receive Pointer Register - REG32 US_RCR; // Receive Counter Register - REG32 US_TPR; // Transmit Pointer Register - REG32 US_TCR; // Transmit Counter Register - REG32 US_RNPR; // Receive Next Pointer Register - REG32 US_RNCR; // Receive Next Counter Register - REG32 US_TNPR; // Transmit Next Pointer Register - REG32 US_TNCR; // Transmit Next Counter Register - REG32 US_PTCR; // PDC Transfer Control Register - REG32 US_PTSR; // PDC Transfer Status Register -}; - -struct rt_at91serial -{ - struct rt_device parent; - - struct rt_at91serial_hw* hw_base; - rt_uint16_t peripheral_id; - rt_uint32_t baudrate; - - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; -}; -#ifdef RT_USING_UART1 -struct rt_at91serial serial1; -#endif -#ifdef RT_USING_UART2 -struct rt_at91serial serial2; -#endif - -static void rt_hw_serial_isr(int irqno) -{ - rt_base_t level; - struct rt_device* device; - struct rt_at91serial* serial = RT_NULL; - - if (irqno == AT91C_ID_US0) - { -#ifdef RT_USING_UART1 - /* serial 1 */ - serial = &serial1; -#endif - } - else if (irqno == AT91C_ID_US1) - { -#ifdef RT_USING_UART2 - /* serial 2 */ - serial = &serial2; -#endif - } - RT_ASSERT(serial != RT_NULL); - - /* get generic device object */ - device = (rt_device_t)serial; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - /* get received character */ - serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR; - - /* move to next position */ - serial->save_index ++; - if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) - serial->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (serial->save_index == serial->read_index) - { - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - /* indicate to upper layer application */ - if (device->rx_indicate != RT_NULL) - device->rx_indicate(device, 1); - - /* ack interrupt */ - AT91C_AIC_EOICR = 1; -} - -static rt_err_t rt_serial_init (rt_device_t dev) -{ - rt_uint32_t bd; - struct rt_at91serial* serial = (struct rt_at91serial*) dev; - - RT_ASSERT(serial != RT_NULL); - /* must be US0 or US1 */ - RT_ASSERT(((serial->peripheral_id == AT91C_ID_US0) || - (serial->peripheral_id == AT91C_ID_US1))); - - /* Enable Clock for USART */ - AT91C_PMC_PCER = 1 << serial->peripheral_id; - - /* Enable RxD0 and TxDO Pin */ - if (serial->peripheral_id == AT91C_ID_US0) - { - /* set pinmux */ - AT91C_PIO_PDR = (1 << 5) | (1 << 6); - } - else if (serial->peripheral_id == AT91C_ID_US1) - { - /* set pinmux */ - AT91C_PIO_PDR = (1 << 21) | (1 << 22); - } - - serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ - AT91C_US_RSTTX | /* Reset Transmitter */ - AT91C_US_RXDIS | /* Receiver Disable */ - AT91C_US_TXDIS; /* Transmitter Disable */ - - serial->hw_base->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ - AT91C_US_CLKS_CLOCK | /* Clock = MCK */ - AT91C_US_CHRL_8_BITS | /* 8-bit Data */ - AT91C_US_PAR_NONE | /* No Parity */ - AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ - - /* set baud rate divisor */ - bd = ((MCK*10)/(serial->baudrate * 16)); - if ((bd % 10) >= 5) bd = (bd / 10) + 1; - else bd /= 10; - - serial->hw_base->US_BRGR = bd; - serial->hw_base->US_CR = AT91C_US_RXEN | /* Receiver Enable */ - AT91C_US_TXEN; /* Transmitter Enable */ - - /* reset rx index */ - serial->save_index = 0; - serial->read_index = 0; - - /* reset rx buffer */ - rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); - - return RT_EOK; -} - -static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) -{ - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* enable UART rx interrupt */ - serial->hw_base->US_IER = 1 << 0; /* RxReady interrupt */ - serial->hw_base->US_IMR |= 1 << 0; /* umask RxReady interrupt */ - - /* install UART handler */ - rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, RT_NULL); - AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5); - rt_hw_interrupt_umask(serial->peripheral_id); - } - - return RT_EOK; -} - -static rt_err_t rt_serial_close(rt_device_t dev) -{ - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable interrupt */ - serial->hw_base->US_IDR = 1 << 0; /* RxReady interrupt */ - serial->hw_base->US_IMR &= ~(1 << 0); /* mask RxReady interrupt */ - } - - return RT_EOK; -} - -static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); - - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (serial->read_index != serial->save_index) - { - *ptr = serial->rx_buffer[serial->read_index]; - - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - else - { - /* no data in rx buffer */ - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - ptr ++; size --; - } - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } - else - { - /* poll mode */ - while (size) - { - /* Wait for Full Rx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY)); - - /* Read Character */ - *ptr = serial->hw_base->US_RHR; - ptr ++; - size --; - } - - return (rt_size_t)ptr - (rt_size_t)buffer; - } - - return 0; -} - -static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); - - ptr = (rt_uint8_t*) buffer; - if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) - { - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* it's a stream mode device */ - while (size) - { - /* stream mode */ - if (*ptr == '\n') - { - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - serial->hw_base->US_THR = '\r'; - } - - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - - /* Transmit Character */ - serial->hw_base->US_THR = *ptr; - ptr ++; size --; - } - } - else - { - while (size) - { - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - - /* Transmit Character */ - serial->hw_base->US_THR = *ptr; - ptr ++; size --; - } - } - } - - return (rt_size_t)ptr - (rt_size_t)buffer; -} - -static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) -{ - return RT_EOK; -} - -rt_err_t rt_hw_serial_init() -{ - rt_device_t device; - -#ifdef RT_USING_UART1 - device = (rt_device_t) &serial1; - - /* init serial device private data */ - serial1.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US0; - serial1.peripheral_id = AT91C_ID_US0; - serial1.baudrate = 115200; - - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - - /* register uart1 on device subsystem */ - rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); -#endif - -#ifdef RT_USING_UART2 - device = (rt_device_t) &serial2; - - serial2.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US1; - serial2.peripheral_id = AT91C_ID_US1; - serial2.baudrate = 115200; - - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - - /* register uart2 on device subsystem */ - rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); -#endif - - return RT_EOK; -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/AT91SAM7S/serial.h b/rt-thread/libcpu/arm/AT91SAM7S/serial.h deleted file mode 100644 index 7766053..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7S/serial.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ -#ifndef __RT_SERIAL_H__ -#define __RT_SERIAL_H__ - -#ifndef AT91C_BASE_US0 -#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address -#endif - -#ifndef AT91C_BASE_US1 -#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address -#endif - -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* US RXRDY Interrupt */ -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* US TXRDY Interrupt */ -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* US Reset Receiver */ -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* US Reset Transmitter */ -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* US Receiver Enable */ -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* US Receiver Disable */ -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* US Transmitter Enable */ -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* US Transmitter Disable */ -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) /* US Reset Status Bits */ - -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) /* USAR) Normal */ -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) /* USAR) RS485 */ -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) /* USAR) Hardware Handshaking */ -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) /* USAR) Modem */ -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) /* USAR) ISO7816 protocol: T = 0 */ -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) /* USAR) ISO7816 protocol: T = 1 */ -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) /* USAR) IrDA */ -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) /* USAR) Software Handshaking */ - -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* USAR) Clock */ -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) /* USAR) fdiv1 */ -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) /* USAR) slow_clock (ARM) */ -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) /* USAR) External (SCK) */ - -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) /* USAR) Character Length: 5 bits */ -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) /* USAR) Character Length: 6 bits */ -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) /* USAR) Character Length: 7 bits */ -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* USAR) Character Length: 8 bits */ - -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) /* DBGU Even Parity */ -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) /* DBGU Odd Parity */ -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) /* DBGU Parity forced to 0 (Space) */ -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) /* DBGU Parity forced to 1 (Mark) */ -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* DBGU No Parity */ -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) /* DBGU Multi-drop mode */ - -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* USART 1 stop bit */ -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) /* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) /* USART 2 stop bits */ - -#define MCK 48054857 -#define BR 115200 /* Baud Rate */ -#define BRD (MCK/16/BR) /* Baud Rate Divisor */ - -#endif diff --git a/rt-thread/libcpu/arm/AT91SAM7S/stack.c b/rt-thread/libcpu/arm/AT91SAM7S/stack.c deleted file mode 100644 index 23fce8e..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7S/stack.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-08-23 Bernard the first version - */ -#include -#include "AT91SAM7S.h" - -/** - * @addtogroup AT91SAM7 - */ -/*@{*/ - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - - stack_addr += sizeof(rt_uint32_t); - stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); - stk = (rt_uint32_t *)stack_addr; - - *(--stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0xdeadbeef; /* r12 */ - *(--stk) = 0xdeadbeef; /* r11 */ - *(--stk) = 0xdeadbeef; /* r10 */ - *(--stk) = 0xdeadbeef; /* r9 */ - *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = 0xdeadbeef; /* r4 */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = 0xdeadbeef; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - *(--stk) = SVCMODE; /* cpsr */ - *(--stk) = SVCMODE; /* spsr */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/AT91SAM7S/start_gcc.S b/rt-thread/libcpu/arm/AT91SAM7S/start_gcc.S deleted file mode 100644 index d71234c..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7S/start_gcc.S +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-08-31 Bernard first version - */ - - /* Internal Memory Base Addresses */ - .equ FLASH_BASE, 0x00100000 - .equ RAM_BASE, 0x00200000 - - /* Stack Configuration */ - .equ TOP_STACK, 0x00204000 - .equ UND_STACK_SIZE, 0x00000100 - .equ SVC_STACK_SIZE, 0x00000400 - .equ ABT_STACK_SIZE, 0x00000100 - .equ FIQ_STACK_SIZE, 0x00000100 - .equ IRQ_STACK_SIZE, 0x00000100 - .equ USR_STACK_SIZE, 0x00000004 - - /* ARM architecture definitions */ - .equ MODE_USR, 0x10 - .equ MODE_FIQ, 0x11 - .equ MODE_IRQ, 0x12 - .equ MODE_SVC, 0x13 - .equ MODE_ABT, 0x17 - .equ MODE_UND, 0x1B - .equ MODE_SYS, 0x1F - - .equ I_BIT, 0x80 /* when this bit is set, IRQ is disabled */ - .equ F_BIT, 0x40 /* when this bit is set, FIQ is disabled */ - -.section .init, "ax" -.code 32 -.align 0 -.globl _start -_start: - b reset - ldr pc, _vector_undef - ldr pc, _vector_swi - ldr pc, _vector_pabt - ldr pc, _vector_dabt - nop /* reserved vector */ - ldr pc, _vector_irq - ldr pc, _vector_fiq - -_vector_undef: .word vector_undef -_vector_swi: .word vector_swi -_vector_pabt: .word vector_pabt -_vector_dabt: .word vector_dabt -_vector_resv: .word vector_resv -_vector_irq: .word vector_irq -_vector_fiq: .word vector_fiq - -/* - * rtthread bss start and end - * which are defined in linker script - */ -.globl _bss_start -_bss_start: .word __bss_start -.globl _bss_end -_bss_end: .word __bss_end - -/* the system entry */ -reset: - /* disable watchdog */ - ldr r0, =0xFFFFFD40 - ldr r1, =0x00008000 - str r1, [r0, #0x04] - - /* enable the main oscillator */ - ldr r0, =0xFFFFFC00 - ldr r1, =0x00000601 - str r1, [r0, #0x20] - - /* wait for main oscillator to stabilize */ -moscs_loop: - ldr r2, [r0, #0x68] - ands r2, r2, #1 - beq moscs_loop - - /* set up the PLL */ - ldr r1, =0x00191C05 - str r1, [r0, #0x2C] - - /* wait for PLL to lock */ -pll_loop: - ldr r2, [r0, #0x68] - ands r2, r2, #0x04 - beq pll_loop - - /* select clock */ - ldr r1, =0x00000007 - str r1, [r0, #0x30] - - /* setup stack for each mode */ - ldr r0, =TOP_STACK - - /* set stack */ - /* undefined instruction mode */ - msr cpsr_c, #MODE_UND|I_BIT|F_BIT - mov sp, r0 - sub r0, r0, #UND_STACK_SIZE - - /* abort mode */ - msr cpsr_c, #MODE_ABT|I_BIT|F_BIT - mov sp, r0 - sub r0, r0, #ABT_STACK_SIZE - - /* FIQ mode */ - msr cpsr_c, #MODE_FIQ|I_BIT|F_BIT - mov sp, r0 - sub r0, r0, #FIQ_STACK_SIZE - - /* IRQ mode */ - msr cpsr_c, #MODE_IRQ|I_BIT|F_BIT - mov sp, r0 - sub r0, r0, #IRQ_STACK_SIZE - - /* supervisor mode */ - msr cpsr_c, #MODE_SVC - mov sp, r0 - -#ifdef __FLASH_BUILD__ - /* Relocate .data section (Copy from ROM to RAM) */ - ldr r1, =_etext - ldr r2, =_data - ldr r3, =_edata -data_loop: - cmp r2, r3 - ldrlo r0, [r1], #4 - strlo r0, [r2], #4 - blo data_loop -#else - /* remap SRAM to 0x0000 */ - ldr r0, =0xFFFFFF00 - mov r1, #0x01 - str r1, [r0] -#endif - - /* mask all IRQs */ - ldr r1, =0xFFFFF124 - ldr r0, =0XFFFFFFFF - str r0, [r1] - - /* start RT-Thread Kernel */ - ldr pc, _rtthread_startup - -_rtthread_startup: .word rtthread_startup - -/* exception handlers */ -vector_undef: b vector_undef -vector_swi : b vector_swi -vector_pabt : b vector_pabt -vector_dabt : b vector_dabt -vector_resv : b vector_resv - -.globl rt_interrupt_enter -.globl rt_interrupt_leave -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -vector_irq: - stmfd sp!, {r0-r12,lr} - bl rt_interrupt_enter - bl rt_hw_trap_irq - bl rt_interrupt_leave - - /* - * if rt_thread_switch_interrupt_flag set, jump to - * rt_hw_context_switch_interrupt_do and don't return - */ - ldr r0, =rt_thread_switch_interrupt_flag - ldr r1, [r0] - cmp r1, #1 - beq rt_hw_context_switch_interrupt_do - - ldmfd sp!, {r0-r12,lr} - subs pc, lr, #4 - -vector_fiq: - stmfd sp!,{r0-r7,lr} - bl rt_hw_trap_fiq - ldmfd sp!,{r0-r7,lr} - subs pc,lr,#4 - -/* - * void rt_hw_context_switch_interrupt_do(rt_base_t flag) - */ -rt_hw_context_switch_interrupt_do: - mov r1, #0 /* clear flag */ - str r1, [r0] - - ldmfd sp!, {r0-r12,lr} /* reload saved registers */ - stmfd sp!, {r0-r3} /* save r0-r3 */ - mov r1, sp - add sp, sp, #16 /* restore sp */ - sub r2, lr, #4 /* save old task's pc to r2 */ - - mrs r3, spsr /* disable interrupt */ - orr r0, r3, #I_BIT|F_BIT - msr spsr_c, r0 - - ldr r0, =.+8 /* switch to interrupted task's stack */ - movs pc, r0 - - stmfd sp!, {r2} /* push old task's pc */ - stmfd sp!, {r4-r12,lr} /* push old task's lr,r12-r4 */ - mov r4, r1 /* Special optimised code below */ - mov r5, r3 - ldmfd r4!, {r0-r3} - stmfd sp!, {r0-r3} /* push old task's r3-r0 */ - stmfd sp!, {r5} /* push old task's psr */ - mrs r4, spsr - stmfd sp!, {r4} /* push old task's spsr */ - - ldr r4, =rt_interrupt_from_thread - ldr r5, [r4] - str sp, [r5] /* store sp in preempted tasks's TCB */ - - ldr r6, =rt_interrupt_to_thread - ldr r6, [r6] - ldr sp, [r6] /* get new task's stack pointer */ - - ldmfd sp!, {r4} /* pop new task's spsr */ - msr SPSR_cxsf, r4 - ldmfd sp!, {r4} /* pop new task's psr */ - msr CPSR_cxsf, r4 - - ldmfd sp!, {r0-r12,lr,pc} /* pop new task's r0-r12,lr & pc */ diff --git a/rt-thread/libcpu/arm/AT91SAM7S/start_rvds.S b/rt-thread/libcpu/arm/AT91SAM7S/start_rvds.S deleted file mode 100644 index 84274bb..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7S/start_rvds.S +++ /dev/null @@ -1,499 +0,0 @@ -;/*****************************************************************************/ -;/* SAM7.S: Startup file for Atmel AT91SAM7 device series */ -;/*****************************************************************************/ -;/* <<< Use Configuration Wizard in Context Menu >>> */ -;/*****************************************************************************/ -;/* This file is part of the uVision/ARM development tools. */ -;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ -;/* This software may only be used under the terms of a valid, current, */ -;/* end user licence from KEIL for a compatible version of KEIL software */ -;/* development tools. Nothing else gives you the right to use this software. */ -;/*****************************************************************************/ - - -;/* -; * The SAM7.S code is executed after CPU Reset. This file may be -; * translated with the following SET symbols. In uVision these SET -; * symbols are entered under Options - ASM - Define. -; * -; * REMAP: when set the startup code remaps exception vectors from -; * on-chip RAM to address 0. -; * -; * RAM_INTVEC: when set the startup code copies exception vectors -; * from on-chip Flash to on-chip RAM. -; */ - - -; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled - - -; Internal Memory Base Addresses -FLASH_BASE EQU 0x00100000 -RAM_BASE EQU 0x00200000 - - -;// Stack Configuration (Stack Sizes in Bytes) -;// Undefined Mode <0x0-0xFFFFFFFF:8> -;// Supervisor Mode <0x0-0xFFFFFFFF:8> -;// Abort Mode <0x0-0xFFFFFFFF:8> -;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> -;// Interrupt Mode <0x0-0xFFFFFFFF:8> -;// User/System Mode <0x0-0xFFFFFFFF:8> -;// - -UND_Stack_Size EQU 0x00000000 -SVC_Stack_Size EQU 0x00000100 -ABT_Stack_Size EQU 0x00000000 -FIQ_Stack_Size EQU 0x00000000 -IRQ_Stack_Size EQU 0x00000100 -USR_Stack_Size EQU 0x00000100 - -ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - -Stack_Mem SPACE USR_Stack_Size -__initial_sp SPACE ISR_Stack_Size -Stack_Top - - -;// Heap Configuration -;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> -;// - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - -; Reset Controller (RSTC) definitions -RSTC_BASE EQU 0xFFFFFD00 ; RSTC Base Address -RSTC_MR EQU 0x08 ; RSTC_MR Offset - -;/* -;// Reset Controller (RSTC) -;// URSTEN: User Reset Enable -;// Enables NRST Pin to generate Reset -;// ERSTL: External Reset Length <0-15> -;// External Reset Time in 2^(ERSTL+1) Slow Clock Cycles -;// -;*/ -RSTC_SETUP EQU 1 -RSTC_MR_Val EQU 0xA5000401 - - -; Embedded Flash Controller (EFC) definitions -EFC_BASE EQU 0xFFFFFF00 ; EFC Base Address -EFC0_FMR EQU 0x60 ; EFC0_FMR Offset -EFC1_FMR EQU 0x70 ; EFC1_FMR Offset - -;// Embedded Flash Controller 0 (EFC0) -;// FMCN: Flash Microsecond Cycle Number <0-255> -;// Number of Master Clock Cycles in 1us -;// FWS: Flash Wait State -;// <0=> Read: 1 cycle / Write: 2 cycles -;// <1=> Read: 2 cycle / Write: 3 cycles -;// <2=> Read: 3 cycle / Write: 4 cycles -;// <3=> Read: 4 cycle / Write: 4 cycles -;// -EFC0_SETUP EQU 1 -EFC0_FMR_Val EQU 0x00320100 - -;// Embedded Flash Controller 1 (EFC1) -;// FMCN: Flash Microsecond Cycle Number <0-255> -;// Number of Master Clock Cycles in 1us -;// FWS: Flash Wait State -;// <0=> Read: 1 cycle / Write: 2 cycles -;// <1=> Read: 2 cycle / Write: 3 cycles -;// <2=> Read: 3 cycle / Write: 4 cycles -;// <3=> Read: 4 cycle / Write: 4 cycles -;// -EFC1_SETUP EQU 0 -EFC1_FMR_Val EQU 0x00320100 - - -; Watchdog Timer (WDT) definitions -WDT_BASE EQU 0xFFFFFD40 ; WDT Base Address -WDT_MR EQU 0x04 ; WDT_MR Offset - -;// Watchdog Timer (WDT) -;// WDV: Watchdog Counter Value <0-4095> -;// WDD: Watchdog Delta Value <0-4095> -;// WDFIEN: Watchdog Fault Interrupt Enable -;// WDRSTEN: Watchdog Reset Enable -;// WDRPROC: Watchdog Reset Processor -;// WDDBGHLT: Watchdog Debug Halt -;// WDIDLEHLT: Watchdog Idle Halt -;// WDDIS: Watchdog Disable -;// -WDT_SETUP EQU 1 -WDT_MR_Val EQU 0x00008000 - - -; Power Mangement Controller (PMC) definitions -PMC_BASE EQU 0xFFFFFC00 ; PMC Base Address -PMC_MOR EQU 0x20 ; PMC_MOR Offset -PMC_MCFR EQU 0x24 ; PMC_MCFR Offset -PMC_PLLR EQU 0x2C ; PMC_PLLR Offset -PMC_MCKR EQU 0x30 ; PMC_MCKR Offset -PMC_SR EQU 0x68 ; PMC_SR Offset -PMC_MOSCEN EQU (1<<0) ; Main Oscillator Enable -PMC_OSCBYPASS EQU (1<<1) ; Main Oscillator Bypass -PMC_OSCOUNT EQU (0xFF<<8) ; Main OScillator Start-up Time -PMC_DIV EQU (0xFF<<0) ; PLL Divider -PMC_PLLCOUNT EQU (0x3F<<8) ; PLL Lock Counter -PMC_OUT EQU (0x03<<14) ; PLL Clock Frequency Range -PMC_MUL EQU (0x7FF<<16) ; PLL Multiplier -PMC_USBDIV EQU (0x03<<28) ; USB Clock Divider -PMC_CSS EQU (3<<0) ; Clock Source Selection -PMC_PRES EQU (7<<2) ; Prescaler Selection -PMC_MOSCS EQU (1<<0) ; Main Oscillator Stable -PMC_LOCK EQU (1<<2) ; PLL Lock Status -PMC_MCKRDY EQU (1<<3) ; Master Clock Status - -;// Power Mangement Controller (PMC) -;// Main Oscillator -;// MOSCEN: Main Oscillator Enable -;// OSCBYPASS: Oscillator Bypass -;// OSCCOUNT: Main Oscillator Startup Time <0-255> -;// -;// Phase Locked Loop (PLL) -;// DIV: PLL Divider <0-255> -;// MUL: PLL Multiplier <0-2047> -;// PLL Output is multiplied by MUL+1 -;// OUT: PLL Clock Frequency Range -;// <0=> 80..160MHz <1=> Reserved -;// <2=> 150..220MHz <3=> Reserved -;// PLLCOUNT: PLL Lock Counter <0-63> -;// USBDIV: USB Clock Divider -;// <0=> None <1=> 2 <2=> 4 <3=> Reserved -;// -;// CSS: Clock Source Selection -;// <0=> Slow Clock -;// <1=> Main Clock -;// <2=> Reserved -;// <3=> PLL Clock -;// PRES: Prescaler -;// <0=> None -;// <1=> Clock / 2 <2=> Clock / 4 -;// <3=> Clock / 8 <4=> Clock / 16 -;// <5=> Clock / 32 <6=> Clock / 64 -;// <7=> Reserved -;// -PMC_SETUP EQU 1 -PMC_MOR_Val EQU 0x00000601 -PMC_PLLR_Val EQU 0x00191C05 -PMC_MCKR_Val EQU 0x00000007 - - - PRESERVE8 - - -; Area Definition and Entry Point -; Startup Code must be linked first at Address at which it expects to run. - - AREA RESET, CODE, READONLY - ARM - - -; Exception Vectors -; Mapped to Address 0. -; Absolute addressing mode must be used. -; Dummy Handlers are implemented as infinite loops which can be modified. - -Vectors LDR PC,Reset_Addr - LDR PC,Undef_Addr - LDR PC,SWI_Addr - LDR PC,PAbt_Addr - LDR PC,DAbt_Addr - NOP ; Reserved Vector - LDR PC,IRQ_Addr - LDR PC,FIQ_Addr - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SWI_Addr DCD SWI_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler - DCD 0 ; Reserved Address -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - -Undef_Handler B Undef_Handler -SWI_Handler B SWI_Handler -PAbt_Handler B PAbt_Handler -DAbt_Handler B DAbt_Handler -FIQ_Handler B FIQ_Handler - - -; Reset Handler - - EXPORT Reset_Handler -Reset_Handler - - -; Setup RSTC - IF RSTC_SETUP != 0 - LDR R0, =RSTC_BASE - LDR R1, =RSTC_MR_Val - STR R1, [R0, #RSTC_MR] - ENDIF - - -; Setup EFC0 - IF EFC0_SETUP != 0 - LDR R0, =EFC_BASE - LDR R1, =EFC0_FMR_Val - STR R1, [R0, #EFC0_FMR] - ENDIF - -; Setup EFC1 - IF EFC1_SETUP != 0 - LDR R0, =EFC_BASE - LDR R1, =EFC1_FMR_Val - STR R1, [R0, #EFC1_FMR] - ENDIF - -; Setup WDT - IF WDT_SETUP != 0 - LDR R0, =WDT_BASE - LDR R1, =WDT_MR_Val - STR R1, [R0, #WDT_MR] - ENDIF - - -; Setup PMC - IF PMC_SETUP != 0 - LDR R0, =PMC_BASE - -; Setup Main Oscillator - LDR R1, =PMC_MOR_Val - STR R1, [R0, #PMC_MOR] - -; Wait until Main Oscillator is stablilized - IF (PMC_MOR_Val:AND:PMC_MOSCEN) != 0 -MOSCS_Loop LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MOSCS - BEQ MOSCS_Loop - ENDIF - -; Setup the PLL - IF (PMC_PLLR_Val:AND:PMC_MUL) != 0 - LDR R1, =PMC_PLLR_Val - STR R1, [R0, #PMC_PLLR] - -; Wait until PLL is stabilized -PLL_Loop LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_LOCK - BEQ PLL_Loop - ENDIF - -; Select Clock - IF (PMC_MCKR_Val:AND:PMC_CSS) == 1 ; Main Clock Selected - LDR R1, =PMC_MCKR_Val - AND R1, #PMC_CSS - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy1 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy1 - LDR R1, =PMC_MCKR_Val - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy2 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy2 - ELIF (PMC_MCKR_Val:AND:PMC_CSS) == 3 ; PLL Clock Selected - LDR R1, =PMC_MCKR_Val - AND R1, #PMC_PRES - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy1 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy1 - LDR R1, =PMC_MCKR_Val - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy2 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy2 - ENDIF ; Select Clock - ENDIF ; PMC_SETUP - - -; Copy Exception Vectors to Internal RAM - - IF :DEF:RAM_INTVEC - ADR R8, Vectors ; Source - LDR R9, =RAM_BASE ; Destination - LDMIA R8!, {R0-R7} ; Load Vectors - STMIA R9!, {R0-R7} ; Store Vectors - LDMIA R8!, {R0-R7} ; Load Handler Addresses - STMIA R9!, {R0-R7} ; Store Handler Addresses - ENDIF - - -; Remap on-chip RAM to address 0 - -MC_BASE EQU 0xFFFFFF00 ; MC Base Address -MC_RCR EQU 0x00 ; MC_RCR Offset - - IF :DEF:REMAP - LDR R0, =MC_BASE - MOV R1, #1 - STR R1, [R0, #MC_RCR] ; Remap - ENDIF - - -; Setup Stack for each mode - - LDR R0, =Stack_Top - -; Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #UND_Stack_Size - -; Enter Abort Mode and set its Stack Pointer - MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #ABT_Stack_Size - -; Enter FIQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #FIQ_Stack_Size - -; Enter IRQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #IRQ_Stack_Size - -; Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #SVC_Stack_Size - -; Enter User Mode and set its Stack Pointer - ; MSR CPSR_c, #Mode_USR - IF :DEF:__MICROLIB - - EXPORT __initial_sp - - ELSE - - ; No usr mode stack here. - ;MOV SP, R0 - ;SUB SL, SP, #USR_Stack_Size - - ENDIF - - -; Enter the C code - - IMPORT __main - LDR R0, =__main - BX R0 - - IMPORT rt_interrupt_enter - IMPORT rt_interrupt_leave - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - IMPORT rt_hw_trap_irq - -IRQ_Handler PROC - EXPORT IRQ_Handler - STMFD sp!, {r0-r12,lr} - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; if rt_thread_switch_interrupt_flag set, jump to - ; rt_hw_context_switch_interrupt_do and don't return - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD sp!, {r0-r12,lr} - SUBS pc, lr, #4 - ENDP - -; /* -; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) -; */ -rt_hw_context_switch_interrupt_do PROC - EXPORT rt_hw_context_switch_interrupt_do - MOV r1, #0 ; clear flag - STR r1, [r0] - - LDMFD sp!, {r0-r12,lr}; reload saved registers - STMFD sp!, {r0-r3} ; save r0-r3 - MOV r1, sp - ADD sp, sp, #16 ; restore sp - SUB r2, lr, #4 ; save old task's pc to r2 - - MRS r3, spsr ; get cpsr of interrupt thread - - ; switch to SVC mode and no interrupt - MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC - - STMFD sp!, {r2} ; push old task's pc - STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 - MOV r4, r1 ; Special optimised code below - MOV r5, r3 - LDMFD r4!, {r0-r3} - STMFD sp!, {r0-r3} ; push old task's r3-r0 - STMFD sp!, {r5} ; push old task's cpsr - MRS r4, spsr - STMFD sp!, {r4} ; push old task's spsr - - LDR r4, =rt_interrupt_from_thread - LDR r5, [r4] - STR sp, [r5] ; store sp in preempted tasks's TCB - - LDR r6, =rt_interrupt_to_thread - LDR r6, [r6] - LDR sp, [r6] ; get new task's stack pointer - - LDMFD sp!, {r4} ; pop new task's spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task's psr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc - ENDP - - IF :DEF:__MICROLIB - - EXPORT __heap_base - EXPORT __heap_limit - - ELSE -; User Initial Stack & Heap - AREA |.text|, CODE, READONLY - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, = (Stack_Mem + IRQ_Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDIF - - END diff --git a/rt-thread/libcpu/arm/AT91SAM7S/trap.c b/rt-thread/libcpu/arm/AT91SAM7S/trap.c deleted file mode 100644 index aa9df7c..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7S/trap.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-08-25 Bernard first version - */ - -#include -#include - -#include "AT91SAM7S.h" - -/** - * @addtogroup AT91SAM7 - */ -/*@{*/ - -void rt_hw_trap_irq() -{ - rt_isr_handler_t hander = (rt_isr_handler_t)AT91C_AIC_IVR; - - hander(AT91C_AIC_ISR); - - /* end of interrupt */ - AT91C_AIC_EOICR = 0; -} - -void rt_hw_trap_fiq() -{ - rt_kprintf("fast interrupt request\n"); -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/AT91SAM7X/SConscript b/rt-thread/libcpu/arm/AT91SAM7X/SConscript deleted file mode 100644 index b259a94..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7X/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/AT91SAM7X/context_gcc.S b/rt-thread/libcpu/arm/AT91SAM7X/context_gcc.S deleted file mode 100644 index d4d6363..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7X/context_gcc.S +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - */ - -/*! - * \addtogroup xgs3c4510 - */ -/*@{*/ - -#define NOINT 0xc0 - -/* - * rt_base_t rt_hw_interrupt_disable(); - */ -.globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mrs r0, cpsr - orr r1, r0, #NOINT - msr cpsr_c, r1 - mov pc, lr - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ -.globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - msr cpsr, r0 - mov pc, lr - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to - */ -.globl rt_hw_context_switch -rt_hw_context_switch: - stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) - stmfd sp!, {r0-r12, lr} @ push lr & register file - - mrs r4, cpsr - stmfd sp!, {r4} @ push cpsr - mrs r4, spsr - stmfd sp!, {r4} @ push spsr - - str sp, [r0] @ store sp in preempted tasks TCB - ldr sp, [r1] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - ldmfd sp!, {r4} @ pop new task cpsr - msr cpsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc} @ pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to - */ -.globl rt_hw_context_switch_to -rt_hw_context_switch_to: - ldr sp, [r0] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - ldmfd sp!, {r4} @ pop new task cpsr - msr cpsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc} @ pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - */ -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -.globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - ldr r2, =rt_thread_switch_interrupt_flag - ldr r3, [r2] - cmp r3, #1 - beq _reswitch - mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 - str r3, [r2] - ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread - str r0, [r2] -_reswitch: - ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread - str r1, [r2] - mov pc, lr diff --git a/rt-thread/libcpu/arm/AT91SAM7X/context_rvds.S b/rt-thread/libcpu/arm/AT91SAM7X/context_rvds.S deleted file mode 100644 index 3cc70c7..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7X/context_rvds.S +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-01-20 Bernard first version - */ - -NOINT EQU 0xc0 ; disable interrupt in psr - - AREA |.text|, CODE, READONLY, ALIGN=2 - ARM - REQUIRE8 - PRESERVE8 - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ -rt_hw_interrupt_disable PROC - EXPORT rt_hw_interrupt_disable - MRS r0, cpsr - ORR r1, r0, #NOINT - MSR cpsr_c, r1 - BX lr - ENDP - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ -rt_hw_interrupt_enable PROC - EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0 - BX lr - ENDP - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ -rt_hw_context_switch PROC - EXPORT rt_hw_context_switch - STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC) - STMFD sp!, {r0-r12, lr} ; push lr & register file - - MRS r4, cpsr - STMFD sp!, {r4} ; push cpsr - MRS r4, spsr - STMFD sp!, {r4} ; push spsr - - STR sp, [r0] ; store sp in preempted tasks TCB - LDR sp, [r1] ; get new task stack pointer - - LDMFD sp!, {r4} ; pop new task spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task cpsr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; */ -rt_hw_context_switch_to PROC - EXPORT rt_hw_context_switch_to - LDR sp, [r0] ; get new task stack pointer - - LDMFD sp!, {r4} ; pop new task spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task cpsr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP - -;/* -; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); -; */ - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -rt_hw_context_switch_interrupt PROC - EXPORT rt_hw_context_switch_interrupt - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1 - STR r3, [r2] - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - BX lr - ENDP - - END diff --git a/rt-thread/libcpu/arm/AT91SAM7X/cpu.c b/rt-thread/libcpu/arm/AT91SAM7X/cpu.c deleted file mode 100644 index ffa4092..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7X/cpu.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-08-23 Bernard first version - */ - -#include - - -/** - * @addtogroup AT91SAM7X - */ -/*@{*/ - -/** - * this function will reset CPU - * - */ -RT_WEAK void rt_hw_cpu_reset() -{ -} - -/** - * this function will shutdown CPU - * - */ -RT_WEAK void rt_hw_cpu_shutdown() -{ - rt_kprintf("shutdown...\n"); - - while (1); -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/AT91SAM7X/interrupt.c b/rt-thread/libcpu/arm/AT91SAM7X/interrupt.c deleted file mode 100644 index 3a28f50..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7X/interrupt.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-08-23 Bernard first version - * 2013-03-29 aozima Modify the interrupt interface implementations. - */ - -#include -#include -#include "AT91SAM7X256.h" - -#define MAX_HANDLERS 32 - -/* exception and interrupt handler table */ -struct rt_irq_desc irq_desc[MAX_HANDLERS]; - -extern rt_uint32_t rt_interrupt_nest; - -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -/** - * @addtogroup AT91SAM7 - */ -/*@{*/ - -static void rt_hw_interrupt_handler(int vector, void *param) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - rt_base_t index; - - /* init exceptions table */ - for(index=0; index < MAX_HANDLERS; index++) - { - irq_desc[index].handler = (rt_isr_handler_t)rt_hw_interrupt_handler; - irq_desc[index].param = RT_NULL; - } - - for (index = 0; index < MAX_HANDLERS; index ++) - { - AT91C_BASE_AIC->AIC_SVR[index] = (rt_uint32_t)rt_hw_interrupt_handler; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - /* disable interrupt */ - AT91C_BASE_AIC->AIC_IDCR = 1 << vector; - - /* clear interrupt */ - AT91C_BASE_AIC->AIC_ICCR = 1 << vector; -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - AT91C_BASE_AIC->AIC_IECR = 1 << vector; -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param handler the interrupt service routine to be installed - * @param param the parameter for interrupt service routine - * @name unused. - * - * @return the old handler - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - if(vector >= 0 && vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = (rt_isr_handler_t)handler; - irq_desc[vector].param = param; - } - } - - return old_handler; -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/AT91SAM7X/stack.c b/rt-thread/libcpu/arm/AT91SAM7X/stack.c deleted file mode 100644 index caa4826..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7X/stack.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-08-23 Bernard the first version - */ -#include - -#define SVCMODE 0x13 - -/** - * @addtogroup AT91SAM7 - */ -/*@{*/ - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - - stack_addr += sizeof(rt_uint32_t); - stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); - stk = (rt_uint32_t *)stack_addr; - *(--stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0xdeadbeef; /* r12 */ - *(--stk) = 0xdeadbeef; /* r11 */ - *(--stk) = 0xdeadbeef; /* r10 */ - *(--stk) = 0xdeadbeef; /* r9 */ - *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = 0xdeadbeef; /* r4 */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = 0xdeadbeef; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - *(--stk) = SVCMODE; /* cpsr */ - *(--stk) = SVCMODE; /* spsr */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/AT91SAM7X/start_gcc.S b/rt-thread/libcpu/arm/AT91SAM7X/start_gcc.S deleted file mode 100644 index 6e09356..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7X/start_gcc.S +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-08-31 Bernard first version - */ - - /* Internal Memory Base Addresses */ - .equ FLASH_BASE, 0x00100000 - .equ RAM_BASE, 0x00200000 - - /* Stack Configuration */ - .equ TOP_STACK, 0x00204000 - .equ UND_STACK_SIZE, 0x00000100 - .equ SVC_STACK_SIZE, 0x00000400 - .equ ABT_STACK_SIZE, 0x00000100 - .equ FIQ_STACK_SIZE, 0x00000100 - .equ IRQ_STACK_SIZE, 0x00000100 - .equ USR_STACK_SIZE, 0x00000004 - - /* ARM architecture definitions */ - .equ MODE_USR, 0x10 - .equ MODE_FIQ, 0x11 - .equ MODE_IRQ, 0x12 - .equ MODE_SVC, 0x13 - .equ MODE_ABT, 0x17 - .equ MODE_UND, 0x1B - .equ MODE_SYS, 0x1F - - .equ I_BIT, 0x80 /* when this bit is set, IRQ is disabled */ - .equ F_BIT, 0x40 /* when this bit is set, FIQ is disabled */ - -.section .init, "ax" -.code 32 -.align 0 -.globl _start -_start: - b reset - ldr pc, _vector_undef - ldr pc, _vector_swi - ldr pc, _vector_pabt - ldr pc, _vector_dabt - nop /* reserved vector */ - ldr pc, _vector_irq - ldr pc, _vector_fiq - -_vector_undef: .word vector_undef -_vector_swi: .word vector_swi -_vector_pabt: .word vector_pabt -_vector_dabt: .word vector_dabt -_vector_resv: .word vector_resv -_vector_irq: .word vector_irq -_vector_fiq: .word vector_fiq - -/* - * rtthread bss start and end - * which are defined in linker script - */ -.globl _bss_start -_bss_start: .word __bss_start -.globl _bss_end -_bss_end: .word __bss_end - -/* the system entry */ -reset: - /* disable watchdog */ - ldr r0, =0xFFFFFD40 - ldr r1, =0x00008000 - str r1, [r0, #0x04] - - /* enable the main oscillator */ - ldr r0, =0xFFFFFC00 - ldr r1, =0x00000601 - str r1, [r0, #0x20] - - /* wait for main oscillator to stabilize */ -moscs_loop: - ldr r2, [r0, #0x68] - ands r2, r2, #1 - beq moscs_loop - - /* set up the PLL */ - ldr r1, =0x00191C05 - str r1, [r0, #0x2C] - - /* wait for PLL to lock */ -pll_loop: - ldr r2, [r0, #0x68] - ands r2, r2, #0x04 - beq pll_loop - - /* select clock */ - ldr r1, =0x00000007 - str r1, [r0, #0x30] - -#ifdef __FLASH_BUILD__ - /* copy exception vectors into internal sram */ - /* - mov r8, #RAM_BASE - ldr r9, =_start - ldmia r9!, {r0-r7} - stmia r8!, {r0-r7} - ldmia r9!, {r0-r6} - stmia r8!, {r0-r6} - */ -#endif - - /* setup stack for each mode */ - ldr r0, =TOP_STACK - - /* set stack */ - /* undefined instruction mode */ - msr cpsr_c, #MODE_UND|I_BIT|F_BIT - mov sp, r0 - sub r0, r0, #UND_STACK_SIZE - - /* abort mode */ - msr cpsr_c, #MODE_ABT|I_BIT|F_BIT - mov sp, r0 - sub r0, r0, #ABT_STACK_SIZE - - /* FIQ mode */ - msr cpsr_c, #MODE_FIQ|I_BIT|F_BIT - mov sp, r0 - sub r0, r0, #FIQ_STACK_SIZE - - /* IRQ mode */ - msr cpsr_c, #MODE_IRQ|I_BIT|F_BIT - mov sp, r0 - sub r0, r0, #IRQ_STACK_SIZE - - /* supervisor mode */ - msr cpsr_c, #MODE_SVC|I_BIT|F_BIT - mov sp, r0 - - /* remap SRAM to 0x0000 */ - /* - ldr r0, =0xFFFFFF00 - mov r1, #0x01 - str r1, [r0] - */ - - /* mask all IRQs */ - ldr r1, =0xFFFFF124 - ldr r0, =0XFFFFFFFF - str r0, [r1] - - /* copy .data to SRAM */ - ldr r1, =_sidata /* .data start in image */ - ldr r2, =_edata /* .data end in image */ - ldr r3, =_sdata /* sram data start */ -data_loop: - ldr r0, [r1, #0] - str r0, [r3] - - add r1, r1, #4 - add r3, r3, #4 - - cmp r3, r2 /* check if data to clear */ - blo data_loop /* loop until done */ - - /* clear .bss */ - mov r0,#0 /* get a zero */ - ldr r1,=__bss_start /* bss start */ - ldr r2,=__bss_end /* bss end */ - -bss_loop: - cmp r1,r2 /* check if data to clear */ - strlo r0,[r1],#4 /* clear 4 bytes */ - blo bss_loop /* loop until done */ - - /* call C++ constructors of global objects */ - ldr r0, =__ctors_start__ - ldr r1, =__ctors_end__ - -ctor_loop: - cmp r0, r1 - beq ctor_end - ldr r2, [r0], #4 - stmfd sp!, {r0-r1} - mov lr, pc - bx r2 - ldmfd sp!, {r0-r1} - b ctor_loop -ctor_end: - - - /* start RT-Thread Kernel */ - ldr pc, _rtthread_startup - -_rtthread_startup: .word rtthread_startup - -/* exception handlers */ -vector_undef: b vector_undef -vector_swi : b vector_swi -vector_pabt : b vector_pabt -vector_dabt : b vector_dabt -vector_resv : b vector_resv - -.globl rt_interrupt_enter -.globl rt_interrupt_leave -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -vector_irq: - stmfd sp!, {r0-r12,lr} - bl rt_interrupt_enter - bl rt_hw_trap_irq - bl rt_interrupt_leave - - /* - * if rt_thread_switch_interrupt_flag set, jump to - * rt_hw_context_switch_interrupt_do and don't return - */ - ldr r0, =rt_thread_switch_interrupt_flag - ldr r1, [r0] - cmp r1, #1 - beq rt_hw_context_switch_interrupt_do - - ldmfd sp!, {r0-r12,lr} - subs pc, lr, #4 - -vector_fiq: - stmfd sp!,{r0-r7,lr} - bl rt_hw_trap_fiq - ldmfd sp!,{r0-r7,lr} - subs pc,lr,#4 - -/* - * void rt_hw_context_switch_interrupt_do(rt_base_t flag) - */ -rt_hw_context_switch_interrupt_do: - mov r1, #0 @ clear flag - str r1, [r0] - - ldmfd sp!, {r0-r12,lr}@ reload saved registers - stmfd sp!, {r0-r3} @ save r0-r3 - mov r1, sp - add sp, sp, #16 @ restore sp - sub r2, lr, #4 @ save old task's pc to r2 - - mrs r3, spsr @ disable interrupt - orr r0, r3, #I_BIT|F_BIT - msr spsr_c, r0 - - ldr r0, =.+8 @ switch to interrupted task's stack - movs pc, r0 - - stmfd sp!, {r2} @ push old task's pc - stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4 - mov r4, r1 @ Special optimised code below - mov r5, r3 - ldmfd r4!, {r0-r3} - stmfd sp!, {r0-r3} @ push old task's r3-r0 - stmfd sp!, {r5} @ push old task's psr - mrs r4, spsr - stmfd sp!, {r4} @ push old task's spsr - - ldr r4, =rt_interrupt_from_thread - ldr r5, [r4] - str sp, [r5] @ store sp in preempted tasks's TCB - - ldr r6, =rt_interrupt_to_thread - ldr r6, [r6] - ldr sp, [r6] @ get new task's stack pointer - - ldmfd sp!, {r4} @ pop new task's spsr - msr SPSR_cxsf, r4 - ldmfd sp!, {r4} @ pop new task's psr - msr CPSR_cxsf, r4 - - ldmfd sp!, {r0-r12,lr,pc} @ pop new task's r0-r12,lr & pc diff --git a/rt-thread/libcpu/arm/AT91SAM7X/start_rvds.S b/rt-thread/libcpu/arm/AT91SAM7X/start_rvds.S deleted file mode 100644 index 9760965..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7X/start_rvds.S +++ /dev/null @@ -1,517 +0,0 @@ -;/*****************************************************************************/ -;/* SAM7.S: Startup file for Atmel AT91SAM7 device series */ -;/*****************************************************************************/ -;/* <<< Use Configuration Wizard in Context Menu >>> */ -;/*****************************************************************************/ -;/* This file is part of the uVision/ARM development tools. */ -;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ -;/* This software may only be used under the terms of a valid, current, */ -;/* end user licence from KEIL for a compatible version of KEIL software */ -;/* development tools. Nothing else gives you the right to use this software. */ -;/*****************************************************************************/ - - -;/* -; * The SAM7.S code is executed after CPU Reset. This file may be -; * translated with the following SET symbols. In uVision these SET -; * symbols are entered under Options - ASM - Define. -; * -; * REMAP: when set the startup code remaps exception vectors from -; * on-chip RAM to address 0. -; * -; * RAM_INTVEC: when set the startup code copies exception vectors -; * from on-chip Flash to on-chip RAM. -; */ - - -; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs - -; 2009-12-28 MingBai Bug fix (USR mode stack removed). -; 2009-12-29 MingBai Merge svc and irq stack, add abort handler. - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled - - -; Internal Memory Base Addresses -FLASH_BASE EQU 0x00100000 -RAM_BASE EQU 0x00200000 - - -;// Stack Configuration (Stack Sizes in Bytes) -;// Undefined Mode <0x0-0xFFFFFFFF:8> -;// Supervisor Mode <0x0-0xFFFFFFFF:8> -;// Abort Mode <0x0-0xFFFFFFFF:8> -;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> -;// Interrupt Mode <0x0-0xFFFFFFFF:8> -;// User/System Mode <0x0-0xFFFFFFFF:8> -;// - -UND_Stack_Size EQU 0x00000000 -SVC_Stack_Size EQU 0x00000000 -ABT_Stack_Size EQU 0x00000000 -FIQ_Stack_Size EQU 0x00000000 -IRQ_Stack_Size EQU 0x00000100 -USR_Stack_Size EQU 0x00000000 - -ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - -Stack_Mem SPACE USR_Stack_Size -__initial_sp SPACE ISR_Stack_Size -Stack_Top - - -;// Heap Configuration -;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> -;// - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - -; Reset Controller (RSTC) definitions -RSTC_BASE EQU 0xFFFFFD00 ; RSTC Base Address -RSTC_MR EQU 0x08 ; RSTC_MR Offset - -;/* -;// Reset Controller (RSTC) -;// URSTEN: User Reset Enable -;// Enables NRST Pin to generate Reset -;// ERSTL: External Reset Length <0-15> -;// External Reset Time in 2^(ERSTL+1) Slow Clock Cycles -;// -;*/ -RSTC_SETUP EQU 1 -RSTC_MR_Val EQU 0xA5000401 - - -; Embedded Flash Controller (EFC) definitions -EFC_BASE EQU 0xFFFFFF00 ; EFC Base Address -EFC0_FMR EQU 0x60 ; EFC0_FMR Offset -EFC1_FMR EQU 0x70 ; EFC1_FMR Offset - -;// Embedded Flash Controller 0 (EFC0) -;// FMCN: Flash Microsecond Cycle Number <0-255> -;// Number of Master Clock Cycles in 1us -;// FWS: Flash Wait State -;// <0=> Read: 1 cycle / Write: 2 cycles -;// <1=> Read: 2 cycle / Write: 3 cycles -;// <2=> Read: 3 cycle / Write: 4 cycles -;// <3=> Read: 4 cycle / Write: 4 cycles -;// -EFC0_SETUP EQU 1 -EFC0_FMR_Val EQU 0x00320100 - -;// Embedded Flash Controller 1 (EFC1) -;// FMCN: Flash Microsecond Cycle Number <0-255> -;// Number of Master Clock Cycles in 1us -;// FWS: Flash Wait State -;// <0=> Read: 1 cycle / Write: 2 cycles -;// <1=> Read: 2 cycle / Write: 3 cycles -;// <2=> Read: 3 cycle / Write: 4 cycles -;// <3=> Read: 4 cycle / Write: 4 cycles -;// -EFC1_SETUP EQU 0 -EFC1_FMR_Val EQU 0x00320100 - - -; Watchdog Timer (WDT) definitions -WDT_BASE EQU 0xFFFFFD40 ; WDT Base Address -WDT_MR EQU 0x04 ; WDT_MR Offset - -;// Watchdog Timer (WDT) -;// WDV: Watchdog Counter Value <0-4095> -;// WDD: Watchdog Delta Value <0-4095> -;// WDFIEN: Watchdog Fault Interrupt Enable -;// WDRSTEN: Watchdog Reset Enable -;// WDRPROC: Watchdog Reset Processor -;// WDDBGHLT: Watchdog Debug Halt -;// WDIDLEHLT: Watchdog Idle Halt -;// WDDIS: Watchdog Disable -;// -WDT_SETUP EQU 1 -WDT_MR_Val EQU 0x00008000 - - -; Power Mangement Controller (PMC) definitions -PMC_BASE EQU 0xFFFFFC00 ; PMC Base Address -PMC_MOR EQU 0x20 ; PMC_MOR Offset -PMC_MCFR EQU 0x24 ; PMC_MCFR Offset -PMC_PLLR EQU 0x2C ; PMC_PLLR Offset -PMC_MCKR EQU 0x30 ; PMC_MCKR Offset -PMC_SR EQU 0x68 ; PMC_SR Offset -PMC_MOSCEN EQU (1<<0) ; Main Oscillator Enable -PMC_OSCBYPASS EQU (1<<1) ; Main Oscillator Bypass -PMC_OSCOUNT EQU (0xFF<<8) ; Main OScillator Start-up Time -PMC_DIV EQU (0xFF<<0) ; PLL Divider -PMC_PLLCOUNT EQU (0x3F<<8) ; PLL Lock Counter -PMC_OUT EQU (0x03<<14) ; PLL Clock Frequency Range -PMC_MUL EQU (0x7FF<<16) ; PLL Multiplier -PMC_USBDIV EQU (0x03<<28) ; USB Clock Divider -PMC_CSS EQU (3<<0) ; Clock Source Selection -PMC_PRES EQU (7<<2) ; Prescaler Selection -PMC_MOSCS EQU (1<<0) ; Main Oscillator Stable -PMC_LOCK EQU (1<<2) ; PLL Lock Status -PMC_MCKRDY EQU (1<<3) ; Master Clock Status - -;// Power Mangement Controller (PMC) -;// Main Oscillator -;// MOSCEN: Main Oscillator Enable -;// OSCBYPASS: Oscillator Bypass -;// OSCCOUNT: Main Oscillator Startup Time <0-255> -;// -;// Phase Locked Loop (PLL) -;// DIV: PLL Divider <0-255> -;// MUL: PLL Multiplier <0-2047> -;// PLL Output is multiplied by MUL+1 -;// OUT: PLL Clock Frequency Range -;// <0=> 80..160MHz <1=> Reserved -;// <2=> 150..220MHz <3=> Reserved -;// PLLCOUNT: PLL Lock Counter <0-63> -;// USBDIV: USB Clock Divider -;// <0=> None <1=> 2 <2=> 4 <3=> Reserved -;// -;// CSS: Clock Source Selection -;// <0=> Slow Clock -;// <1=> Main Clock -;// <2=> Reserved -;// <3=> PLL Clock -;// PRES: Prescaler -;// <0=> None -;// <1=> Clock / 2 <2=> Clock / 4 -;// <3=> Clock / 8 <4=> Clock / 16 -;// <5=> Clock / 32 <6=> Clock / 64 -;// <7=> Reserved -;// -PMC_SETUP EQU 1 -PMC_MOR_Val EQU 0x00000601 -PMC_PLLR_Val EQU 0x00191C05 -PMC_MCKR_Val EQU 0x00000007 - - - PRESERVE8 - - -; Area Definition and Entry Point -; Startup Code must be linked first at Address at which it expects to run. - - AREA RESET, CODE, READONLY - ARM - - -; Exception Vectors -; Mapped to Address 0. -; Absolute addressing mode must be used. -; Dummy Handlers are implemented as infinite loops which can be modified. - -Vectors LDR PC,Reset_Addr - LDR PC,Undef_Addr - LDR PC,SWI_Addr - LDR PC,PAbt_Addr - LDR PC,DAbt_Addr - NOP ; Reserved Vector - LDR PC,IRQ_Addr - LDR PC,FIQ_Addr - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SWI_Addr DCD SWI_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler - DCD 0 ; Reserved Address -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - -Undef_Handler B Undef_Handler -SWI_Handler B SWI_Handler -PAbt_Handler B Abort_Handler -DAbt_Handler B Abort_Handler -FIQ_Handler B FIQ_Handler - - -; Reset Handler - - EXPORT Reset_Handler -Reset_Handler - - -; Setup RSTC - IF RSTC_SETUP != 0 - LDR R0, =RSTC_BASE - LDR R1, =RSTC_MR_Val - STR R1, [R0, #RSTC_MR] - ENDIF - - -; Setup EFC0 - IF EFC0_SETUP != 0 - LDR R0, =EFC_BASE - LDR R1, =EFC0_FMR_Val - STR R1, [R0, #EFC0_FMR] - ENDIF - -; Setup EFC1 - IF EFC1_SETUP != 0 - LDR R0, =EFC_BASE - LDR R1, =EFC1_FMR_Val - STR R1, [R0, #EFC1_FMR] - ENDIF - -; Setup WDT - IF WDT_SETUP != 0 - LDR R0, =WDT_BASE - LDR R1, =WDT_MR_Val - STR R1, [R0, #WDT_MR] - ENDIF - - -; Setup PMC - IF PMC_SETUP != 0 - LDR R0, =PMC_BASE - -; Setup Main Oscillator - LDR R1, =PMC_MOR_Val - STR R1, [R0, #PMC_MOR] - -; Wait until Main Oscillator is stablilized - IF (PMC_MOR_Val:AND:PMC_MOSCEN) != 0 -MOSCS_Loop LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MOSCS - BEQ MOSCS_Loop - ENDIF - -; Setup the PLL - IF (PMC_PLLR_Val:AND:PMC_MUL) != 0 - LDR R1, =PMC_PLLR_Val - STR R1, [R0, #PMC_PLLR] - -; Wait until PLL is stabilized -PLL_Loop LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_LOCK - BEQ PLL_Loop - ENDIF - -; Select Clock - IF (PMC_MCKR_Val:AND:PMC_CSS) == 1 ; Main Clock Selected - LDR R1, =PMC_MCKR_Val - AND R1, #PMC_CSS - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy1 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy1 - LDR R1, =PMC_MCKR_Val - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy2 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy2 - ELIF (PMC_MCKR_Val:AND:PMC_CSS) == 3 ; PLL Clock Selected - LDR R1, =PMC_MCKR_Val - AND R1, #PMC_PRES - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy1 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy1 - LDR R1, =PMC_MCKR_Val - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy2 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy2 - ENDIF ; Select Clock - ENDIF ; PMC_SETUP - - -; Copy Exception Vectors to Internal RAM - - IF :DEF:RAM_INTVEC - ADR R8, Vectors ; Source - LDR R9, =RAM_BASE ; Destination - LDMIA R8!, {R0-R7} ; Load Vectors - STMIA R9!, {R0-R7} ; Store Vectors - LDMIA R8!, {R0-R7} ; Load Handler Addresses - STMIA R9!, {R0-R7} ; Store Handler Addresses - ENDIF - - -; Remap on-chip RAM to address 0 - -MC_BASE EQU 0xFFFFFF00 ; MC Base Address -MC_RCR EQU 0x00 ; MC_RCR Offset - - IF :DEF:REMAP - LDR R0, =MC_BASE - MOV R1, #1 - STR R1, [R0, #MC_RCR] ; Remap - ENDIF - - -; Setup Stack for each mode - - LDR R0, =Stack_Top - -; Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit - MOV SP, R0 - ;SUB R0, R0, #UND_Stack_Size - -; Enter Abort Mode and set its Stack Pointer - MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit - MOV SP, R0 - ;SUB R0, R0, #ABT_Stack_Size - -; Enter FIQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - ;SUB R0, R0, #FIQ_Stack_Size - -; Enter IRQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - ;SUB R0, R0, #IRQ_Stack_Size - -; Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit - MOV SP, R0 - ; SUB R0, R0, #SVC_Stack_Size - -; Enter User Mode and set its Stack Pointer - ; MSR CPSR_c, #Mode_USR - IF :DEF:__MICROLIB - - EXPORT __initial_sp - - ELSE - - ; No usr mode stack here. - ;MOV SP, R0 - ;SUB SL, SP, #USR_Stack_Size - - ENDIF - - -; Enter the C code - - IMPORT __main - LDR R0, =__main - BX R0 - - IMPORT rt_interrupt_enter - IMPORT rt_interrupt_leave - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - IMPORT rt_hw_trap_irq - IMPORT rt_hw_trap_abort - IMPORT rt_interrupt_nest - -Abort_Handler PROC - EXPORT Abort_Handler - stmfd sp!, {r0-r12,lr} - LDR r0, =rt_interrupt_nest - LDR r1, [r0] - CMP r1, #0 -DeadLoop BHI DeadLoop ; Abort happened in irq mode, halt system. - bl rt_interrupt_enter - bl rt_hw_trap_abort - bl rt_interrupt_leave - b SWITCH - ENDP - -IRQ_Handler PROC - EXPORT IRQ_Handler - STMFD sp!, {r0-r12,lr} - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; if rt_thread_switch_interrupt_flag set, jump to - ; rt_hw_context_switch_interrupt_do and don't return -SWITCH LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD sp!, {r0-r12,lr} - SUBS pc, lr, #4 - ENDP - -; /* -; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) -; */ -rt_hw_context_switch_interrupt_do PROC - EXPORT rt_hw_context_switch_interrupt_do - MOV r1, #0 ; clear flag - STR r1, [r0] - - LDMFD sp!, {r0-r12,lr}; reload saved registers - STMFD sp!, {r0-r3} ; save r0-r3 - MOV r1, sp - ADD sp, sp, #16 ; restore sp - SUB r2, lr, #4 ; save old task's pc to r2 - - MRS r3, spsr ; get cpsr of interrupt thread - - ; switch to SVC mode and no interrupt - MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC - - STMFD sp!, {r2} ; push old task's pc - STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 - MOV r4, r1 ; Special optimised code below - MOV r5, r3 - LDMFD r4!, {r0-r3} - STMFD sp!, {r0-r3} ; push old task's r3-r0 - STMFD sp!, {r5} ; push old task's cpsr - MRS r4, spsr - STMFD sp!, {r4} ; push old task's spsr - - LDR r4, =rt_interrupt_from_thread - LDR r5, [r4] - STR sp, [r5] ; store sp in preempted tasks's TCB - - LDR r6, =rt_interrupt_to_thread - LDR r6, [r6] - LDR sp, [r6] ; get new task's stack pointer - - LDMFD sp!, {r4} ; pop new task's spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task's psr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc - ENDP - - IF :DEF:__MICROLIB - - EXPORT __heap_base - EXPORT __heap_limit - - ELSE -; User Initial Stack & Heap - AREA |.text|, CODE, READONLY - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, = (Stack_Mem + IRQ_Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDIF - - END diff --git a/rt-thread/libcpu/arm/AT91SAM7X/trap.c b/rt-thread/libcpu/arm/AT91SAM7X/trap.c deleted file mode 100644 index 3c012dd..0000000 --- a/rt-thread/libcpu/arm/AT91SAM7X/trap.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-08-25 Bernard first version - */ - -#include -#include - -#include "AT91SAM7X256.h" - -/** - * @addtogroup AT91SAM7 - */ -/*@{*/ - -void rt_hw_trap_irq(void) -{ - int irqno; - extern struct rt_irq_desc irq_desc[]; - - /* get interrupt number */ - irqno = AT91C_BASE_AIC->AIC_ISR; - - /* invoke isr with parameters */ - irq_desc[irqno].handler(irqno, irq_desc[irqno].param); - - /* end of interrupt */ - AT91C_BASE_AIC->AIC_EOICR = 0; -} - -void rt_hw_trap_fiq(void) -{ - rt_kprintf("fast interrupt request\n"); -} - -extern struct rt_thread* rt_current_thread; -void rt_hw_trap_abort(void) -{ - rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name); - rt_thread_suspend(rt_current_thread); - rt_schedule(); - -} -/*@}*/ diff --git a/rt-thread/libcpu/arm/am335x/SConscript b/rt-thread/libcpu/arm/am335x/SConscript deleted file mode 100644 index b259a94..0000000 --- a/rt-thread/libcpu/arm/am335x/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/am335x/am33xx.h b/rt-thread/libcpu/arm/am335x/am33xx.h deleted file mode 100644 index c74a0c1..0000000 --- a/rt-thread/libcpu/arm/am335x/am33xx.h +++ /dev/null @@ -1,354 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ -#ifndef __AM33XX_H__ -#define __AM33XX_H__ - -#define REG32(x) (*((volatile unsigned int *)(x))) -#define REG16(x) (*((volatile unsigned short *)(x))) - -/** Cache Line size in ARM Cortex-A8. */ -#define AM33XX_CACHELINE_SIZE (64) - -/** @brief Base address of AINTC memory mapped registers */ -#define AM33XX_AINTC_REGS (0x48200000) - - -/** @brief Base addresses of control module registers */ -#define AM33XX_CTLM_REGS (0x44e10000) - -/** @brief Base addresses of USB memory mapped registers */ -#define AM33XX_USB_0_BASE (0x47401400) -#define AM33XX_USB_1_BASE (0x47401C00) -/** @brief Base addresses of SPI memory mapped registers */ -#define AM33XX_SPI_0_REGS (0x48030000) -#define AM33XX_SPI_1_REGS (0x481A0000) - -/** @brief Base addresses of GPIO memory mapped registers */ -#define AM33XX_GPIO_0_REGS (0x44E07000) -#define AM33XX_GPIO_1_REGS (0x4804C000) -#define AM33XX_GPIO_2_REGS (0x481AC000) -#define AM33XX_GPIO_3_REGS (0x481AE000) - -/** @brief Base addresses of DMTIMER memory mapped registers */ -#define AM33XX_DMTIMER_0_REGS (0x44E05000) -#define AM33XX_DMTIMER_1_REGS (0x44E31000) -#define AM33XX_DMTIMER_2_REGS (0x48040000) -#define AM33XX_DMTIMER_3_REGS (0x48042000) -#define AM33XX_DMTIMER_4_REGS (0x48044000) -#define AM33XX_DMTIMER_5_REGS (0x48046000) -#define AM33XX_DMTIMER_6_REGS (0x48048000) -#define AM33XX_DMTIMER_7_REGS (0x4804A000) - -/** @brief Base address of MMC memory mapped registers */ -#define AM33XX_MMCHS_0_REGS (0x48060000) -#define AM33XX_MMCHS_1_REGS (0x481D8000) -#define AM33XX_MMCHS_2_REGS (0x47810000) - -/** @brief Base address of GPMC memory mapped registers */ -#define AM33XX_GPMC_0_REGS (0x50000000) - -/** @brief Base address of GPMC memory mapped registers */ -#define AM33XX_ELM_0_REGS (0x48080000) - -/** @brief Base address of I2C memory mapped registers */ -#define AM33XX_I2C_0_REGS (0x44E0B000) -#define AM33XX_I2C_1_REGS (0x4802A000) -#define AM33XX_I2C_2_REGS (0x4819C000) - -/** @brief Base address of WDT memory mapped registers */ -#define AM33XX_WDT_0_REGS (0x44E33000) -#define AM33XX_WDT_1_REGS (0x44E35000) - -/** @brief Base address of WDT memory mapped registers */ -#define AM33XX_CPSW_SS_REGS (0x4A100000) -#define AM33XX_CPSW_MDIO_REGS (0x4A101000) -#define AM33XX_CPSW_WR_REGS (0x4A101200) -#define AM33XX_CPSW_CPDMA_REGS (0x4A100800) -#define AM33XX_CPSW_ALE_REGS (0x4A100D00) -#define AM33XX_CPSW_STAT_REGS (0x4A100900) -#define AM33XX_CPSW_PORT_0_REGS (0x4A100100) -#define AM33XX_CPSW_PORT_1_REGS (0x4A100200) -#define AM33XX_CPSW_SLIVER_1_REGS (0x4A100D80) -#define AM33XX_CPSW_PORT_2_REGS (0x4A100300) -#define AM33XX_CPSW_SLIVER_2_REGS (0x4A100DC0) -#define AM33XX_CPSW_CPPI_RAM_REGS (0x4A102000) - -/** @brief Base address of McASP memory mapped registers */ -#define AM33XX_MCASP_1_CTRL_REGS (0x4803C000) -#define AM33XX_MCASP_1_FIFO_REGS (AM33XX_MCASP_1_CTRL_REGS + 0x1000) -#define AM33XX_MCASP_1_DATA_REGS (0x46400000) - -/** @brief Base address of EMIF memory mapped registers */ -#define AM33XX_EMIF_0_REGS (0x4C000000) - -/** @brief Base addresses of RTC memory mapped registers */ -#define AM33XX_RTC_0_REGS (0x44E3E000) - -#define CM_PER(base) ((base) + 0) -#define CM_PER_L4LS_CLKSTCTRL(base) (CM_PER(base) + 0) -#define CM_PER_UART1_CLKCTRL(base) (CM_PER(base) + 0x6C) -#define CM_PER_UART2_CLKCTRL(base) (CM_PER(base) + 0x70) -#define CM_PER_UART3_CLKCTRL(base) (CM_PER(base) + 0x74) -#define CM_PER_UART4_CLKCTRL(base) (CM_PER(base) + 0x78) -#define CM_PER_UART5_CLKCTRL(base) (CM_PER(base) + 0x38) -#define CM_WKUP(base) ((base) + 0x400) -#define CM_WKUP_CLKSTCTRL(base) (CM_WKUP(base) + 0) -#define CM_WKUP_UART0_CLKCTRL(base) (CM_WKUP(base) + 0xB4) -#define CM_DPLL(base) ((base) + 0x500) -#define CM_MPU(base) ((base) + 0x600) -#define CM_DEVICE(base) ((base) + 0x700) -#define CM_RTC(base) ((base) + 0x800) -#define CM_GFX(base) ((base) + 0x900) -#define CM_CEFUSE(base) ((base) + 0xA00) -#define OCP_AM33XXKET_RAM(base) ((base) + 0xB00) -#define PRM_PER(base) ((base) + 0xC00) -#define PRM_PER_PWRSTST(base) (PRM_PER(base) + 0x008) -#define PRM_PER_PWRSTCTRL(base) (PRM_PER(base) + 0x00C) -#define PRM_WKUP(base) ((base) + 0xD00) -#define PRM_MPU(base) ((base) + 0xE00) -#define PRM_DEVICE(base) ((base) + 0xF00) -#define PRM_RTC(base) ((base) + 0x1000) -#define PRM_GFX(base) ((base) + 0x1100) -#define PRM_CEFUSE(base) ((base) + 0x1200) - -/** @brief Base addresses of PRCM memory mapped registers */ -#define AM33XX_PRCM_REGS (0x44E00000) -#define AM33XX_CM_PER_REGS CM_PER(AM33XX_PRCM_REGS) -#define AM33XX_CM_WKUP_REGS CM_WKUP(AM33XX_PRCM_REGS) -#define AM33XX_CM_DPLL_REGS CM_DPLL(AM33XX_PRCM_REGS) -#define AM33XX_CM_MPU_REGS CM_MPU(AM33XX_PRCM_REGS) -#define AM33XX_CM_DEVICE_REGS CM_DEVICE(AM33XX_PRCM_REGS) -#define AM33XX_CM_RTC_REGS CM_RTC(AM33XX_PRCM_REGS) -#define AM33XX_CM_GFX_REGS CM_GFX(AM33XX_PRCM_REGS) -#define AM33XX_CM_CEFUSE_REGS CM_CEFUSE(AM33XX_PRCM_REGS) -#define AM33XX_OCP_AM33XXKET_RAM_REGS OCP_AM33XXKET_RAM(AM33XX_PRCM_REGS) -#define AM33XX_PRM_PER_REGS PRM_PER(AM33XX_PRCM_REGS) -#define AM33XX_PRM_WKUP_REGS PRM_WKUP(AM33XX_PRCM_REGS) -#define AM33XX_PRM_MPU_REGS PRM_MPU(AM33XX_PRCM_REGS) -#define AM33XX_PRM_DEVICE_REGS PRM_DEVICE(AM33XX_PRCM_REGS) -#define AM33XX_PRM_RTC_REGS PRM_RTC(AM33XX_PRCM_REGS) -#define AM33XX_PRM_GFX_REGS PRM_GFX(AM33XX_PRCM_REGS) -#define AM33XX_PRM_CEFUSE_REGS PRM_CEFUSE(AM33XX_PRCM_REGS) - -/** @brief Base address of control module memory mapped registers */ -#define AM33XX_CONTROL_REGS (0x44E10000) - - -/** @brief Base address of Channel controller memory mapped registers */ -#define AM33XX_EDMA30CC_0_REGS (0x49000000) - -/** @brief Base address of DCAN module memory mapped registers */ -#define AM33XX_DCAN_0_REGS (0x481CC000) -#define AM33XX_DCAN_1_REGS (0x481D0000) - -/******************************************************************************\ -* Parameterizable Configuration:- These are fed directly from the RTL -* parameters for the given AM33XX -\******************************************************************************/ -#define TPCC_MUX(n) 0xF90 + ((n) * 4) - - -#define AM33XX_LCDC_0_REGS 0x4830E000 - -#define AM33XX_ADC_TSC_0_REGS 0x44E0D000 - -/** @brief Base addresses of PWMSS memory mapped registers. */ - -#define AM33XX_PWMSS0_REGS (0x48300000) -#define AM33XX_PWMSS1_REGS (0x48302000) -#define AM33XX_PWMSS2_REGS (0x48304000) - -#define AM33XX_ECAP_REGS (0x00000100) -#define AM33XX_EQEP_REGS (0x00000180) -#define AM33XX_EPWM_REGS (0x00000200) - -#define AM33XX_ECAP_0_REGS (AM33XX_PWMSS0_REGS + AM33XX_ECAP_REGS) -#define AM33XX_ECAP_1_REGS (AM33XX_PWMSS1_REGS + AM33XX_ECAP_REGS) -#define AM33XX_ECAP_2_REGS (AM33XX_PWMSS2_REGS + AM33XX_ECAP_REGS) - -#define AM33XX_EQEP_0_REGS (AM33XX_PWMSS0_REGS + AM33XX_EQEP_REGS) -#define AM33XX_EQEP_1_REGS (AM33XX_PWMSS1_REGS + AM33XX_EQEP_REGS) -#define AM33XX_EQEP_2_REGS (AM33XX_PWMSS2_REGS + AM33XX_EQEP_REGS) - -#define AM33XX_EPWM_0_REGS (AM33XX_PWMSS0_REGS + AM33XX_EPWM_REGS) -#define AM33XX_EPWM_1_REGS (AM33XX_PWMSS1_REGS + AM33XX_EPWM_REGS) -#define AM33XX_EPWM_2_REGS (AM33XX_PWMSS2_REGS + AM33XX_EPWM_REGS) - -#define AM33XX_EPWM_MODULE_FREQ 100 - -/* PRCM registers */ -#define CM_PER_L4LS_CLKSTCTRL_REG(base) REG32((base) + 0x0) -#define CM_PER_UART1_CLKCTRL_REG(base) REG32(CM_PER_UART1_CLKCTRL(base)) -#define CM_PER_UART2_CLKCTRL_REG(base) REG32(CM_PER_UART2_CLKCTRL(base)) -#define CM_PER_UART3_CLKCTRL_REG(base) REG32(CM_PER_UART3_CLKCTRL(base)) -#define CM_PER_UART4_CLKCTRL_REG(base) REG32(CM_PER_UART4_CLKCTRL(base)) -#define CM_PER_UART5_CLKCTRL_REG(base) REG32(CM_PER_UART5_CLKCTRL(base)) - -#define CM_PER_TIMER7_CLKCTRL(base) REG32((base) + 0x7C) -#define CM_PER_TIMER2_CLKCTRL(base) REG32((base) + 0x80) - -#define PRM_PER_PWRSTST_REG(base) REG32(PRM_PER_PWRSTST(base)) -#define PRM_PER_PWRSTCTRL_REG(base) REG32(PRM_PER_PWRSTCTRL(base)) - -#define CM_WKUP_CLKSTCTRL_REG(base) REG32(CM_WKUP_CLKSTCTRL(base)) -#define CM_WKUP_UART0_CLKCTRL_REG(base) REG32(CM_WKUP_UART0_CLKCTRL(base)) - -#define CM_DPLL_CLKSEL_TIMER7_CLK(base) REG32(CM_DPLL(base) + 0x4) -#define CM_DPLL_CLKSEL_TIMER2_CLK(base) REG32(CM_DPLL(base) + 0x8) - -/* timer registers */ -#define DMTIMER_TIDR(base) REG32(base + 0x0) -#define DMTIMER_TIOCP_CFG(base) REG32(base + 0x10) -#define DMTIMER_IRQ_EOI(base) REG32(base + 0x20) -#define DMTIMER_IRQSTATUS_RAW(base) REG32(base + 0x24) -#define DMTIMER_IRQSTATUS(base) REG32(base + 0x28) -#define DMTIMER_IRQENABLE_SET(base) REG32(base + 0x2C) -#define DMTIMER_IRQENABLE_CLR(base) REG32(base + 0x30) -#define DMTIMER_IRQWAKEEN(base) REG32(base + 0x34) -#define DMTIMER_TCLR(base) REG32(base + 0x38) -#define DMTIMER_TCRR(base) REG32(base + 0x3C) -#define DMTIMER_TLDR(base) REG32(base + 0x40) -#define DMTIMER_TTGR(base) REG32(base + 0x44) -#define DMTIMER_TWPS(base) REG32(base + 0x48) -#define DMTIMER_TMAR(base) REG32(base + 0x4C) -#define DMTIMER_TCAR(base, n) REG32(base + 0x50 + (((n) - 1) * 8)) -#define DMTIMER_TSICR(base) REG32(base + 0x54) - -#define EMU_INT 0 -#define COMMTX_INT 1 -#define COMMRX_INT 2 -#define BENCH_INT 3 -#define ELM_IRQ_INT 4 -#define NMI_INT 7 -#define L3DEBUG_INT 9 -#define L3APP_INT 10 -#define PRCM_INT 11 -#define EDMACOMP_INT 12 -#define EDMAMPERR_INT 13 -#define EDMAERR_INT 14 -#define ADC_TSC_GEN_INT 16 -#define USBSS_INT 17 -#define USB_INT0 18 -#define USB_INT1 19 -#define PRU_ICSS_EVTOUT0_INT 20 -#define PRU_ICSS_EVTOUT1_INT 21 -#define PRU_ICSS_EVTOUT2_INT 22 -#define PRU_ICSS_EVTOUT3_INT 23 -#define PRU_ICSS_EVTOUT4_INT 24 -#define PRU_ICSS_EVTOUT5_INT 25 -#define PRU_ICSS_EVTOUT6_INT 26 -#define PRU_ICSS_EVTOUT7_INT 27 -#define MMCSD1_INT 28 -#define MMCSD2_INT 29 -#define I2C2_INT 30 -#define ECAP0_INT 31 -#define GPIO_INT2A 32 -#define GPIO_INT2B 33 -#define USBWAKEUP_INT 34 -#define LCDC_INT 36 -#define GFX_INT 37 -#define EPWM2_INT 39 -#define CPSW_RXTHR0_INT 40 -#define CPSW_RX_INT0 41 -#define CPSW_TX_INT0 42 -#define CPSW_MISC0_INT 43 -#define UART3_INT 44 -#define UART4_INT 45 -#define UART5_INT 46 -#define ECAP1_INT 47 -#define DCAN0_INT0 52 -#define DCAN0_INT1 53 -#define DCAN0_PARITY 54 -#define DCAN1_INT0 55 -#define DCAN1_INT1 56 -#define DCAN1_PARITY 57 -#define EPWM0_TZINT 58 -#define EPWM1_TZINT 59 -#define EPWM2_TZINT 60 -#define ECAP2_INT 61 -#define GPIO_INT3A 62 -#define GPIO_INT3B 63 -#define MMCSD0_INT 64 -#define MCSPI0_INT 65 -#define TINT0 66 -#define TINT1_1MS 67 -#define TINT2 68 -#define TINT3 69 -#define I2C0_INT 70 -#define I2C1_INT 71 -#define UART0_INT 72 -#define UART1_INT 73 -#define UART2_INT 74 -#define RTC_INT 75 -#define RTC_ALARM_INT 76 -#define MB_INT0 77 -#define M3_TXEV 78 -#define EQEP0_INT 79 -#define MACTX_INT0 80 -#define MCARX_INT0 81 -#define MCATX_INT1 82 -#define MCARX_INT1 83 -#define EPWM0_INT 86 -#define EPWM1_INT 87 -#define EQEP1_INT 88 -#define EQEP2_INT 89 -#define DMA_INTR_PIN2 90 -#define WDT1_INT 91 -#define TINT4 92 -#define TINT5 93 -#define TINT6 94 -#define TINT7 95 -#define GPIO_INT0A 96 -#define GPIO_INT0B 97 -#define GPIO_INT1A 98 -#define GPIO_INT1B 99 -#define GPMC_INT 100 -#define DDRERR0 101 -#define TCERR_INT0 112 -#define TCERR_INT1 113 -#define TCERR_INT2 114 -#define ADC_TSC_PEN_INT 115 -#define SMRFLX_MPU 120 -#define SMRFLX_CORE 121 -#define DMA_INTR_PIN0 123 -#define DMA_INTR_PIN1 124 -#define MCSPI1_INT 125 - -struct rt_hw_register -{ - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; - unsigned long ORIG_r0; -}; - -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -#endif diff --git a/rt-thread/libcpu/arm/am335x/context_gcc.S b/rt-thread/libcpu/arm/am335x/context_gcc.S deleted file mode 100644 index 20ac26d..0000000 --- a/rt-thread/libcpu/arm/am335x/context_gcc.S +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - */ - -/* - * rt_base_t rt_hw_interrupt_disable(); - */ -.globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mrs r0, cpsr - cpsid if - bx lr - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ -.globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - msr cpsr_c, r0 - bx lr - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to - */ -.globl rt_hw_context_switch -rt_hw_context_switch: - stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) - stmfd sp!, {r0-r12, lr} @ push lr & register file - - mrs r4, cpsr - tst lr, #0x01 - orrne r4, r4, #0x20 @ it's thumb code - - stmfd sp!, {r4} @ push cpsr - - str sp, [r0] @ store sp in preempted tasks TCB - ldr sp, [r1] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task cpsr to spsr - msr spsr_cxsf, r4 - -_do_switch: - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to - */ -.globl rt_hw_context_switch_to -rt_hw_context_switch_to: - ldr sp, [r0] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - - bic r4, r4, #0x20 @ must be ARM mode - msr cpsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - */ -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -.globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - ldr r2, =rt_thread_switch_interrupt_flag - ldr r3, [r2] - cmp r3, #1 - beq _reswitch - mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 - str r3, [r2] - ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread - str r0, [r2] -_reswitch: - ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread - str r1, [r2] - bx lr diff --git a/rt-thread/libcpu/arm/am335x/context_iar.S b/rt-thread/libcpu/arm/am335x/context_iar.S deleted file mode 100644 index a800367..0000000 --- a/rt-thread/libcpu/arm/am335x/context_iar.S +++ /dev/null @@ -1,86 +0,0 @@ -;/* -; * Copyright (c) 2006-2021, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2011-08-14 weety copy from mini2440 -; * 2015-04-15 ArdaFu convert from context_gcc.s -; */ - -#define NOINT 0xc0 - - SECTION .text:CODE(6) -/* - * rt_base_t rt_hw_interrupt_disable(); - */ - PUBLIC rt_hw_interrupt_disable -rt_hw_interrupt_disable: - MRS R0, CPSR - ORR R1, R0, #NOINT - MSR CPSR_C, R1 - MOV PC, LR - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ - PUBLIC rt_hw_interrupt_enable -rt_hw_interrupt_enable: - MSR CPSR_CXSF, R0 - MOV PC, LR - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to - */ - PUBLIC rt_hw_context_switch -rt_hw_context_switch: - STMFD SP!, {LR} ; push pc (lr should be pushed in place of PC) - STMFD SP!, {R0-R12, LR} ; push lr & register file - MRS R4, CPSR - TST LR, #0x01 - ORRNE R4, R4, #0x20 ; it's thumb code - STMFD SP!, {R4} ; push cpsr - STR SP, [R0] ; store sp in preempted tasks TCB - LDR SP, [R1] ; get new task stack pointer - LDMFD SP!, {R4} ; pop new task spsr - MSR SPSR_cxsf, R4 - LDMFD SP!, {R0-R12, LR, PC}^ ; pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to - */ - PUBLIC rt_hw_context_switch_to -rt_hw_context_switch_to: - LDR SP, [R0] ; get new task stack pointer - LDMFD SP!, {R4} ; pop new task spsr - MSR SPSR_cxsf, R4 - BIC R4, R4, #0x20 ; must be ARM mode - MSR CPSR_CXSF, R4 - LDMFD SP!, {R0-R12, LR, PC}^ ; pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - */ - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - PUBLIC rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - LDR R2, =rt_thread_switch_interrupt_flag - LDR R3, [R2] - CMP R3, #1 - BEQ _reswitch - MOV R3, #1 ; set flag to 1 - STR R3, [R2] - LDR R2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR R0, [R2] -_reswitch: - LDR R2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR R1, [R2] - MOV PC, LR - END - diff --git a/rt-thread/libcpu/arm/am335x/cp15_gcc.S b/rt-thread/libcpu/arm/am335x/cp15_gcc.S deleted file mode 100644 index 6568f7d..0000000 --- a/rt-thread/libcpu/arm/am335x/cp15_gcc.S +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - */ - -.globl rt_cpu_vector_set_base -rt_cpu_vector_set_base: - mcr p15, #0, r0, c12, c0, #0 - dsb - bx lr - -.globl rt_cpu_vector_get_base -rt_cpu_vector_get_base: - mrc p15, #0, r0, c12, c0, #0 - bx lr - -.globl rt_cpu_get_sctlr -rt_cpu_get_sctlr: - mrc p15, #0, r0, c1, c0, #0 - bx lr - -.globl rt_cpu_dcache_enable -rt_cpu_dcache_enable: - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x00000004 - mcr p15, #0, r0, c1, c0, #0 - bx lr - -.globl rt_cpu_icache_enable -rt_cpu_icache_enable: - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x00001000 - mcr p15, #0, r0, c1, c0, #0 - bx lr - -_FLD_MAX_WAY: - .word 0x3ff -_FLD_MAX_IDX: - .word 0x7ff - -.globl rt_cpu_dcache_clean_flush -rt_cpu_dcache_clean_flush: - push {r4-r11} - dmb - mrc p15, #1, r0, c0, c0, #1 @ read clid register - ands r3, r0, #0x7000000 @ get level of coherency - mov r3, r3, lsr #23 - beq finished - mov r10, #0 -loop1: - add r2, r10, r10, lsr #1 - mov r1, r0, lsr r2 - and r1, r1, #7 - cmp r1, #2 - blt skip - mcr p15, #2, r10, c0, c0, #0 - isb - mrc p15, #1, r1, c0, c0, #0 - and r2, r1, #7 - add r2, r2, #4 - ldr r4, _FLD_MAX_WAY - ands r4, r4, r1, lsr #3 - clz r5, r4 - ldr r7, _FLD_MAX_IDX - ands r7, r7, r1, lsr #13 -loop2: - mov r9, r4 -loop3: - orr r11, r10, r9, lsl r5 - orr r11, r11, r7, lsl r2 - mcr p15, #0, r11, c7, c14, #2 - subs r9, r9, #1 - bge loop3 - subs r7, r7, #1 - bge loop2 -skip: - add r10, r10, #2 - cmp r3, r10 - bgt loop1 - -finished: - dsb - isb - pop {r4-r11} - bx lr - -.globl rt_cpu_dcache_disable -rt_cpu_dcache_disable: - push {r4-r11, lr} - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #0x00000004 - mcr p15, #0, r0, c1, c0, #0 - bl rt_cpu_dcache_clean_flush - pop {r4-r11, lr} - bx lr - -.globl rt_cpu_icache_disable -rt_cpu_icache_disable: - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #0x00001000 - mcr p15, #0, r0, c1, c0, #0 - bx lr - -.globl rt_cpu_mmu_disable -rt_cpu_mmu_disable: - mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #1 - mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit - dsb - bx lr - -.globl rt_cpu_mmu_enable -rt_cpu_mmu_enable: - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x001 - mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit - dsb - bx lr - -.globl rt_cpu_tlb_set -rt_cpu_tlb_set: - mcr p15, #0, r0, c2, c0, #0 - dmb - bx lr diff --git a/rt-thread/libcpu/arm/am335x/cp15_iar.s b/rt-thread/libcpu/arm/am335x/cp15_iar.s deleted file mode 100644 index 9e155fa..0000000 --- a/rt-thread/libcpu/arm/am335x/cp15_iar.s +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2015-04-06 zchong change to iar compiler from convert from cp15_gcc.S - */ - - SECTION .text:CODE:NOROOT(2) - - ARM - - EXPORT rt_cpu_vector_set_base -rt_cpu_vector_set_base: - MCR p15, #0, r0, c12, c0, #0 - DSB - BX lr - - EXPORT rt_cpu_vector_get_base -rt_cpu_vector_get_base: - MRC p15, #0, r0, c12, c0, #0 - BX lr - - EXPORT rt_cpu_get_sctlr -rt_cpu_get_sctlr: - MRC p15, #0, r0, c1, c0, #0 - BX lr - - EXPORT rt_cpu_dcache_enable -rt_cpu_dcache_enable: - MRC p15, #0, r0, c1, c0, #0 - ORR r0, r0, #0x00000004 - MCR p15, #0, r0, c1, c0, #0 - BX lr - - EXPORT rt_cpu_icache_enable -rt_cpu_icache_enable: - MRC p15, #0, r0, c1, c0, #0 - ORR r0, r0, #0x00001000 - MCR p15, #0, r0, c1, c0, #0 - BX lr - -;_FLD_MAX_WAY DEFINE 0x3ff -;_FLD_MAX_IDX DEFINE 0x7ff - - - EXPORT rt_cpu_dcache_clean_flush -rt_cpu_dcache_clean_flush: - PUSH {r4-r11} - DMB - MRC p15, #1, r0, c0, c0, #1 ; read clid register - ANDS r3, r0, #0x7000000 ; get level of coherency - MOV r3, r3, lsr #23 - BEQ finished - MOV r10, #0 -loop1: - ADD r2, r10, r10, lsr #1 - MOV r1, r0, lsr r2 - AND r1, r1, #7 - CMP r1, #2 - BLT skip - MCR p15, #2, r10, c0, c0, #0 - ISB - MRC p15, #1, r1, c0, c0, #0 - AND r2, r1, #7 - ADD r2, r2, #4 - ;LDR r4, _FLD_MAX_WAY - LDR r4, =0x3FF - ANDS r4, r4, r1, lsr #3 - CLZ r5, r4 - ;LDR r7, _FLD_MAX_IDX - LDR r7, =0x7FF - ANDS r7, r7, r1, lsr #13 -loop2: - MOV r9, r4 -loop3: - ORR r11, r10, r9, lsl r5 - ORR r11, r11, r7, lsl r2 - MCR p15, #0, r11, c7, c14, #2 - SUBS r9, r9, #1 - BGE loop3 - SUBS r7, r7, #1 - BGE loop2 -skip: - ADD r10, r10, #2 - CMP r3, r10 - BGT loop1 - -finished: - DSB - ISB - POP {r4-r11} - BX lr - - - EXPORT rt_cpu_dcache_disable -rt_cpu_dcache_disable: - PUSH {r4-r11, lr} - MRC p15, #0, r0, c1, c0, #0 - BIC r0, r0, #0x00000004 - MCR p15, #0, r0, c1, c0, #0 - BL rt_cpu_dcache_clean_flush - POP {r4-r11, lr} - BX lr - - - EXPORT rt_cpu_icache_disable -rt_cpu_icache_disable: - MRC p15, #0, r0, c1, c0, #0 - BIC r0, r0, #0x00001000 - MCR p15, #0, r0, c1, c0, #0 - BX lr - - EXPORT rt_cpu_mmu_disable -rt_cpu_mmu_disable: - MCR p15, #0, r0, c8, c7, #0 ; invalidate tlb - MRC p15, #0, r0, c1, c0, #0 - BIC r0, r0, #1 - MCR p15, #0, r0, c1, c0, #0 ; clear mmu bit - DSB - BX lr - - EXPORT rt_cpu_mmu_enable -rt_cpu_mmu_enable: - MRC p15, #0, r0, c1, c0, #0 - ORR r0, r0, #0x001 - MCR p15, #0, r0, c1, c0, #0 ; set mmu enable bit - DSB - BX lr - - EXPORT rt_cpu_tlb_set -rt_cpu_tlb_set: - MCR p15, #0, r0, c2, c0, #0 - DMB - BX lr - - END diff --git a/rt-thread/libcpu/arm/am335x/cpu.c b/rt-thread/libcpu/arm/am335x/cpu.c deleted file mode 100644 index 3688d31..0000000 --- a/rt-thread/libcpu/arm/am335x/cpu.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-09-15 Bernard first version - * 2022-09-20 YangZhongQing - * add IAR assembler - */ - -#include -#include -#include "am33xx.h" - -/** - * @addtogroup AM33xx - */ -/*@{*/ - -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) - -#if defined(__CC_ARM) -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - __asm - { - mrc p15, 0, i, c1, c0, 0 - } - - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } -} -#elif defined(__GNUC__) -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); -} -#elif defined(__ICCARM__) -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - __asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - rt_uint32_t tmp; - - __asm volatile( \ - "mrc p15,0,%0,c1,c0,0\n\t" \ - "orr %0,%0,%1\n\t" \ - "mcr p15,0,%0,c1,c0,0" \ - :"+r"(tmp) \ - :"r"(bit) \ - :"memory"); -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - rt_uint32_t tmp; - - __asm volatile( \ - "mrc p15,0,%0,c1,c0,0\n\t" \ - "bic %0,%0,%1\n\t" \ - "mcr p15,0,%0,c1,c0,0" \ - :"+r"(tmp) \ - :"r"(bit) \ - :"memory"); -} -#endif - -/** - * enable I-Cache - * - */ -void rt_hw_cpu_icache_enable() -{ - cache_enable(ICACHE_MASK); -} - -/** - * disable I-Cache - * - */ -void rt_hw_cpu_icache_disable() -{ - cache_disable(ICACHE_MASK); -} - -/** - * return the status of I-Cache - * - */ -rt_base_t rt_hw_cpu_icache_status() -{ - return (cp15_rd() & ICACHE_MASK); -} - -/** - * enable D-Cache - * - */ -void rt_hw_cpu_dcache_enable() -{ - cache_enable(DCACHE_MASK); -} - -/** - * disable D-Cache - * - */ -void rt_hw_cpu_dcache_disable() -{ - cache_disable(DCACHE_MASK); -} - -/** - * return the status of D-Cache - * - */ -rt_base_t rt_hw_cpu_dcache_status() -{ - return (cp15_rd() & DCACHE_MASK); -} - -/** - * shutdown CPU - * - */ -RT_WEAK void rt_hw_cpu_shutdown() -{ - rt_base_t level; - rt_kprintf("shutdown...\n"); - - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/am335x/interrupt.c b/rt-thread/libcpu/arm/am335x/interrupt.c deleted file mode 100644 index 1810a92..0000000 --- a/rt-thread/libcpu/arm/am335x/interrupt.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-06 Bernard first version - * 2015-11-06 zchong support iar compiler - */ - -#include -#include - -#include "am33xx.h" -#include "interrupt.h" - -#define AINTC_BASE AM33XX_AINTC_REGS - -#define MAX_HANDLERS 128 - -extern volatile rt_uint8_t rt_interrupt_nest; - -/* exception and interrupt handler table */ -struct rt_irq_desc isr_table[MAX_HANDLERS]; -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -/** - * @addtogroup AM33xx - */ -/*@{*/ - -void rt_dump_aintc(void) -{ - int k; - rt_kprintf("active irq %d", INTC_SIR_IRQ(AINTC_BASE)); - rt_kprintf("\n--- hw mask ---\n"); - for (k = 0; k < 4; k++) - { - rt_kprintf("0x%08x, ", INTC_MIR(AINTC_BASE, k)); - } - rt_kprintf("\n--- hw itr ---\n"); - for (k = 0; k < 4; k++) - { - rt_kprintf("0x%08x, ", INTC_ITR(AINTC_BASE, k)); - } - rt_kprintf("\n"); -} - -const unsigned int AM335X_VECTOR_BASE = 0x4030FC00; -extern void rt_cpu_vector_set_base(unsigned int addr); -#ifdef __ICCARM__ -extern int __vector; -#else -extern int system_vectors; -#endif - -static void rt_hw_vector_init(void) -{ - unsigned int *dest = (unsigned int *)AM335X_VECTOR_BASE; - -#ifdef __ICCARM__ - unsigned int *src = (unsigned int *)&__vector; -#else - unsigned int *src = (unsigned int *)&system_vectors; -#endif - - rt_memcpy(dest, src, 16 * 4); - rt_cpu_vector_set_base(AM335X_VECTOR_BASE); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - /* Reset the ARM interrupt controller */ - INTC_SYSCONFIG(AINTC_BASE) = INTC_SYSCONFIG_SOFTRESET; - - /* Wait for the reset to complete */ - while((INTC_SYSSTATUS(AINTC_BASE) - & INTC_SYSSTATUS_RESETDONE) != INTC_SYSSTATUS_RESETDONE); - - /* Enable any interrupt generation by setting priority threshold */ - INTC_THRESHOLD(AINTC_BASE) = INTC_THRESHOLD_PRIORITYTHRESHOLD; - - /* initialize vector table */ - rt_hw_vector_init(); - - /* init exceptions table */ - rt_memset(isr_table, 0x00, sizeof(isr_table)); - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - INTC_MIR_SET(AINTC_BASE, vector >> 0x05) = 0x1 << (vector & 0x1f); -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - INTC_MIR_CLEAR(AINTC_BASE, vector >> 0x05) = 0x1 << (vector & 0x1f); -} - -/** - * This function will control the interrupt attribute. - * @param vector the interrupt number - */ -void rt_hw_interrupt_control(int vector, int priority, int route) -{ - int fiq; - - if (route == 0) - fiq = 0; - else - fiq = 1; - - INTC_ILR(AINTC_BASE, vector) = ((priority << 0x02) & 0x1FC) | fiq ; -} - -int rt_hw_interrupt_get_active(int fiq_irq) -{ - int ir; - if (fiq_irq == INT_FIQ) - { - ir = INTC_SIR_FIQ(AINTC_BASE) & 0x7f; - } - else - { - ir = INTC_SIR_IRQ(AINTC_BASE) & 0x7f; - } - - return ir; -} - -void rt_hw_interrupt_ack(int fiq_irq) -{ - if (fiq_irq == INT_FIQ) - { - /* new FIQ generation */ - INTC_CONTROL(AINTC_BASE) |= 0x02; - } - else - { - /* new IRQ generation */ - INTC_CONTROL(AINTC_BASE) |= 0x01; - } -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param new_handler the interrupt service routine to be installed - * @param old_handler the old interrupt service routine - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if(vector < MAX_HANDLERS) - { - old_handler = isr_table[vector].handler; - - if (handler != RT_NULL) - { -#ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); -#endif /* RT_USING_INTERRUPT_INFO */ - isr_table[vector].handler = handler; - isr_table[vector].param = param; - } - } - - return old_handler; -} - -/** - * This function will trigger an interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_trigger(int vector) -{ - INTC_ISR_SET(AINTC_BASE, vector>>5) = 1 << (vector & 0x1f); -} - -void rt_hw_interrupt_clear(int vector) -{ - INTC_ISR_CLEAR(AINTC_BASE, vector>>5) = 1 << (vector & 0x1f); -} - -void rt_dump_isr_table(void) -{ - int idx; - for(idx = 0; idx < MAX_HANDLERS; idx++) - { -#ifdef RT_USING_INTERRUPT_INFO - rt_kprintf("nr:%4d, name: %*.s, handler: 0x%p, param: 0x%08x\r\n", - idx, RT_NAME_MAX, isr_table[idx].name, - isr_table[idx].handler, isr_table[idx].param); -#else - rt_kprintf("nr:%4d, handler: 0x%p, param: 0x%08x\r\n", - idx, isr_table[idx].handler, isr_table[idx].param); -#endif - } -} -/*@}*/ - - diff --git a/rt-thread/libcpu/arm/am335x/interrupt.h b/rt-thread/libcpu/arm/am335x/interrupt.h deleted file mode 100644 index 35239b1..0000000 --- a/rt-thread/libcpu/arm/am335x/interrupt.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-06 Bernard first version - */ - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#define INT_IRQ 0x00 -#define INT_FIQ 0x01 - -/*************************************************************************\ - * Registers Definition -\*************************************************************************/ -#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) -#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) -#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) -#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) -#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) -#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) -#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) -#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) -#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) -#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) -#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) -#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) -#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) -#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) -#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) -#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) -#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) -#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) -#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) -#define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20)) -#define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20)) -#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) - -/**************************************************************************\ -* Field Definition Macros -\**************************************************************************/ - -/* REVISION */ -#define INTC_REVISION_REV (0x000000FFu) -#define INTC_REVISION_REV_SHIFT (0x00000000u) - -/* SYSCONFIG */ -#define INTC_SYSCONFIG_SOFTRESET (0x00000002u) -#define INTC_SYSCONFIG_SOFTRESET_SHIFT (0x00000001u) - -#define INTC_SYSCONFIG_AUTOIDLE (0x00000001u) -#define INTC_SYSCONFIG_AUTOIDLE_SHIFT (0x00000000u) - -/* SYSSTATUS */ -#define INTC_SYSSTATUS_RESETDONE (0x00000001u) -#define INTC_SYSSTATUS_RESETDONE_SHIFT (0x00000000u) - -/* SIR_IRQ */ -#define INTC_SIR_IRQ_SPURIOUSIRQ (0xFFFFFF80u) -#define INTC_SIR_IRQ_SPURIOUSIRQ_SHIFT (0x00000007u) - -#define INTC_SIR_IRQ_ACTIVEIRQ (0x0000007F) -#define INTC_SIR_IRQ_ACTIVEIRQ_SHIFT (0x00000000) - -/* SIR_FIQ */ -#define INTC_SIR_FIQ_SPURIOUSFIQ (0xFFFFFF80) -#define INTC_SIR_FIQ_SPURIOUSFIQ_SHIFT (0x00000007) - -#define INTC_SIR_FIQ_ACTIVEFIQ (0x0000007F) -#define INTC_SIR_FIQ_ACTIVEFIQ_SHIFT (0x00000000) - -/* CONTROL */ -#define INTC_CONTROL_NEWFIQAGR (0x00000002) -#define INTC_CONTROL_NEWFIQAGR_SHIFT (0x00000001) - -#define INTC_CONTROL_NEWIRQAGR (0x00000001) -#define INTC_CONTROL_NEWIRQAGR_SHIFT (0x00000000) - -/* PROTECTION */ -#define INTC_PROTECTION_PROTECTION (0x00000001u) -#define INTC_PROTECTION_PROTECTION_SHIFT (0x00000000u) - -/* IDLE */ -#define INTC_IDLE_TURBO (0x00000002u) -#define INTC_IDLE_TURBO_SHIFT (0x00000001u) - -#define INTC_IDLE_FUNCIDLE (0x00000001u) -#define INTC_IDLE_FUNCIDLE_SHIFT (0x00000000u) - -/* IRQ_PRIORITY */ -#define INTC_IRQ_PRIORITY_SPURIOUSIRQFLAG (0xFFFFFFC0u) -#define INTC_IRQ_PRIORITY_SPURIOUSIRQFLAG_SHIFT (0x00000006u) - -#define INTC_IRQ_PRIORITY_IRQPRIORITY (0x0000003Fu) -#define INTC_IRQ_PRIORITY_IRQPRIORITY_SHIFT (0x00000000u) - -/* FIQ_PRIORITY */ -#define INTC_FIQ_PRIORITY_SPURIOUSFIQFLAG (0xFFFFFFC0u) -#define INTC_FIQ_PRIORITY_SPURIOUSFIQFLAG_SHIFT (0x00000006u) - -#define INTC_FIQ_PRIORITY_FIQPRIORITY (0x0000003Fu) -#define INTC_FIQ_PRIORITY_FIQPRIORITY_SHIFT (0x00000000u) - -/* THRESHOLD */ -#define INTC_THRESHOLD_PRIORITYTHRESHOLD (0x000000FFu) -#define INTC_THRESHOLD_PRIORITYTHRESHOLD_SHIFT (0x00000000u) - -/* SICR */ -#define INTC_SICR_GLOBALMASK (0x00000040u) -#define INTC_SICR_GLOBALMASK_SHIFT (0x00000006u) - -#define INTC_SICR_SOFTRESETINH (0x00000020u) -#define INTC_SICR_SOFTRESETINH_SHIFT (0x00000005u) - -#define INTC_SICR_PUBLICMASKFEEDBACK (0x00000010u) -#define INTC_SICR_PUBLICMASKFEEDBACK_SHIFT (0x00000004u) - -#define INTC_SICR_PUBLICINHIBIT (0x00000008u) -#define INTC_SICR_PUBLICINHIBIT_SHIFT (0x00000003u) - -#define INTC_SICR_AUTOINHIBIT (0x00000004u) -#define INTC_SICR_AUTOINHIBIT_SHIFT (0x00000002u) - -#define INTC_SICR_SSMFIQENABLE (0x00000002u) -#define INTC_SICR_SSMFIQENABLE_SHIFT (0x00000001u) - -#define INTC_SICR_SSMFIQSTATUS (0x00000001u) -#define INTC_SICR_SSMFIQSTATUS_SHIFT (0x00000000u) - -/* SCR0 */ -#define INTC_SCR0_SECUREENABLE (0xFFFFFFFFu) -#define INTC_SCR0_SECUREENABLE_SHIFT (0x00000000u) - -/* SCR1 */ -#define INTC_SCR1_SECUREENABLE (0xFFFFFFFFu) -#define INTC_SCR1_SECUREENABLE_SHIFT (0x00000000u) - -/* SCR2 */ -#define INTC_SCR2_SECUREENABLE (0xFFFFFFFFu) -#define INTC_SCR2_SECUREENABLE_SHIFT (0x00000000u) - -/* ITR0 */ -#define INTC_ITR0_ITR (0xFFFFFFFFu) -#define INTC_ITR0_ITR_SHIFT (0x00000000u) - -/* MIR0 */ -#define INTC_MIR0_MIR (0xFFFFFFFFu) -#define INTC_MIR0_MIR_SHIFT (0x00000000u) - -/* MIR_CLEAR0 */ -#define INTC_MIR_CLEAR0_MIRCLEAR (0xFFFFFFFFu) -#define INTC_MIR_CLEAR0_MIRCLEAR_SHIFT (0x00000000u) - -/* MIR_SET0 */ -#define INTC_MIR_SET0_MIRSET (0xFFFFFFFFu) -#define INTC_MIR_SET0_MIRSET_SHIFT (0x00000000u) - -/* ISR_SET0 */ -#define INTC_ISR_SET0_ISRSET (0xFFFFFFFFu) -#define INTC_ISR_SET0_ISRSET_SHIFT (0x00000000u) - -/* ISR_CLEAR0 */ -#define INTC_ISR_CLEAR0_ISRCLEAR (0xFFFFFFFFu) -#define INTC_ISR_CLEAR0_ISRCLEAR_SHIFT (0x00000000u) - -/* PENDING_IRQ0 */ -#define INTC_PENDING_IRQ0_PENDING_IRQ (0xFFFFFFFFu) -#define INTC_PENDING_IRQ0_PENDING_IRQ_SHIFT (0x00000000u) - -/* PENDING_FIQ0 */ -#define INTC_PENDING_FIQ0_PENDING_FIQ (0xFFFFFFFFu) -#define INTC_PENDING_FIQ0_PENDING_FIQ_SHIFT (0x00000000u) - -/* ITR1 */ -#define INTC_ITR1_ITR (0xFFFFFFFFu) -#define INTC_ITR1_ITR_SHIFT (0x00000000u) - -/* MIR1 */ -#define INTC_MIR1_MIR (0xFFFFFFFFu) -#define INTC_MIR1_MIR_SHIFT (0x00000000u) - -/* MIR_CLEAR1 */ -#define INTC_MIR_CLEAR1_MIRCLEAR (0xFFFFFFFFu) -#define INTC_MIR_CLEAR1_MIRCLEAR_SHIFT (0x00000000u) - -/* MIR_SET1 */ -#define INTC_MIR_SET1_MIRSET (0xFFFFFFFFu) -#define INTC_MIR_SET1_MIRSET_SHIFT (0x00000000u) - -/* ISR_SET1 */ -#define INTC_ISR_SET1_ISRSET (0xFFFFFFFFu) -#define INTC_ISR_SET1_ISRSET_SHIFT (0x00000000u) - -/* ISR_CLEAR1 */ -#define INTC_ISR_CLEAR1_ISRCLEAR (0xFFFFFFFFu) -#define INTC_ISR_CLEAR1_ISRCLEAR_SHIFT (0x00000000u) - -/* PENDING_IRQ1 */ -#define INTC_PENDING_IRQ1_PENDING_IRQ (0xFFFFFFFFu) -#define INTC_PENDING_IRQ1_PENDING_IRQ_SHIFT (0x00000000u) - -/* PENDING_FIQ1 */ -#define INTC_PENDING_FIQ1_PENDING_FIQ (0xFFFFFFFFu) -#define INTC_PENDING_FIQ1_PENDING_FIQ_SHIFT (0x00000000u) - -/* ITR2 */ -#define INTC_ITR2_ITR (0xFFFFFFFFu) -#define INTC_ITR2_ITR_SHIFT (0x00000000u) - -/* MIR2 */ -#define INTC_MIR2_MIR (0xFFFFFFFFu) -#define INTC_MIR2_MIR_SHIFT (0x00000000u) - -/* MIR_CLEAR2 */ -#define INTC_MIR_CLEAR2_MIRCLEAR (0xFFFFFFFFu) -#define INTC_MIR_CLEAR2_MIRCLEAR_SHIFT (0x00000000u) - -/* MIR_SET2 */ -#define INTC_MIR_SET2_MIRSET (0xFFFFFFFFu) -#define INTC_MIR_SET2_MIRSET_SHIFT (0x00000000u) - -/* ISR_SET2 */ -#define INTC_ISR_SET2_ISRSET (0xFFFFFFFFu) -#define INTC_ISR_SET2_ISRSET_SHIFT (0x00000000u) - -/* ISR_CLEAR2 */ -#define INTC_ISR_CLEAR2_ISRCLEAR (0xFFFFFFFFu) -#define INTC_ISR_CLEAR2_ISRCLEAR_SHIFT (0x00000000u) - -/* PENDING_IRQ2 */ -#define INTC_PENDING_IRQ2_PENDING_IRQ (0xFFFFFFFFu) -#define INTC_PENDING_IRQ2_PENDING_IRQ_SHIFT (0x00000000u) - -/* PENDING_FIQ2 */ -#define INTC_PENDING_FIQ2_PENDING_FIQ (0xFFFFFFFFu) -#define INTC_PENDING_FIQ2_PENDING_FIQ_SHIFT (0x00000000u) - -/* ILR */ -#define INTC_ILR_PRIORITY (0x000001FCu) -#define INTC_ILR_PRIORITY_SHIFT (0x00000002u) - -#define INTC_ILR_FIQNIRQ (0x00000001u) -#define INTC_ILR_FIQNIRQ_SHIFT (0x00000000u) - -void rt_hw_interrupt_control(int vector, int priority, int route); -int rt_hw_interrupt_get_active(int fiq_irq); -void rt_hw_interrupt_ack(int fiq_irq); -void rt_hw_interrupt_trigger(int vector); -void rt_hw_interrupt_clear(int vector); - -#endif diff --git a/rt-thread/libcpu/arm/am335x/mmu.c b/rt-thread/libcpu/arm/am335x/mmu.c deleted file mode 100644 index 19cc9fc..0000000 --- a/rt-thread/libcpu/arm/am335x/mmu.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2012-01-10 bernard porting to AM1808 - */ - -#include -#include "am33xx.h" -#include - -extern void rt_cpu_dcache_disable(void); -extern void rt_hw_cpu_dcache_enable(void); -extern void rt_cpu_icache_disable(void); -extern void rt_hw_cpu_icache_enable(void); -extern void rt_cpu_mmu_disable(void); -extern void rt_cpu_mmu_enable(void); -extern void rt_cpu_tlb_set(register rt_uint32_t i); - -void mmu_disable_dcache() -{ - rt_cpu_dcache_disable(); -} - -void mmu_enable_dcache() -{ - rt_hw_cpu_dcache_enable(); -} - -void mmu_disable_icache() -{ - rt_cpu_icache_disable(); -} - -void mmu_enable_icache() -{ - rt_hw_cpu_icache_enable(); -} - -void mmu_disable() -{ - rt_cpu_mmu_disable(); -} - -void mmu_enable() -{ - rt_cpu_mmu_enable(); -} - -void mmu_setttbase(register rt_uint32_t i) -{ - register rt_uint32_t value; - - /* Invalidates all TLBs.Domain access is selected as - * client by configuring domain access register, - * in that case access controlled by permission value - * set by page table entry - */ - value = 0; - asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); - - value = 0x55555555; - asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); - - rt_cpu_tlb_set(i); -} - -void mmu_set_domain(register rt_uint32_t i) -{ - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); -} - -void mmu_enable_alignfault() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= (1 << 1); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable_alignfault() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~(1 << 1); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_clean_invalidated_cache_index(int index) -{ - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); -} - -void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~0x1f; - - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); - ptr += 32; - } -} - -void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~0x1f; - - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); - ptr += 32; - } -} - -void mmu_invalidate_tlb() -{ - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); -} - -void mmu_invalidate_icache() -{ - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); -} - -/* level1 page table */ -static volatile unsigned int _page_table[4*1024] __attribute__((aligned(16*1024))); -void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrStart, rt_uint32_t attr) -{ - volatile rt_uint32_t *pTT; - int i,nSec; - pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20); - nSec=(vaddrEnd>>20)-(vaddrStart>>20); - for(i=0;i<=nSec;i++) - { - *pTT = attr |(((paddrStart>>20)+i)<<20); - pTT++; - } -} - -/* set page table */ -RT_WEAK void mmu_setmtts(void) -{ - mmu_setmtt(0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB); /* None cached for 4G memory */ - mmu_setmtt(0x80200000, 0x80800000 - 1, 0x80200000, RW_CB); /* 126M cached DDR memory */ - mmu_setmtt(0x80000000, 0x80200000 - 1, 0x80000000, RW_NCNB); /* 2M none-cached DDR memory */ - mmu_setmtt(0x402F0000, 0x40300000 - 1, 0x402F0000, RW_CB); /* 63K OnChip memory */ -} - -void rt_hw_mmu_init(void) -{ - /* disable I/D cache */ - mmu_disable_dcache(); - mmu_disable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); - - mmu_setmtts(); - - /* set MMU table address */ - mmu_setttbase((rt_uint32_t)_page_table); - - /* enables MMU */ - mmu_enable(); - - /* enable Instruction Cache */ - mmu_enable_icache(); - - /* enable Data Cache */ - mmu_enable_dcache(); -} - diff --git a/rt-thread/libcpu/arm/am335x/mmu.h b/rt-thread/libcpu/arm/am335x/mmu.h deleted file mode 100644 index 706d669..0000000 --- a/rt-thread/libcpu/arm/am335x/mmu.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2012-01-10 bernard porting to AM1808 - */ - -#ifndef __MMU_H__ -#define __MMU_H__ - -#include - -#define DESC_SEC (0x2) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO - -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) - -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) - -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ - -void rt_hw_mmu_init(void); - -#endif diff --git a/rt-thread/libcpu/arm/am335x/stack.c b/rt-thread/libcpu/arm/am335x/stack.c deleted file mode 100644 index db3cb37..0000000 --- a/rt-thread/libcpu/arm/am335x/stack.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-09-23 Bernard the first version - * 2011-10-05 Bernard add thumb mode - */ -#include -#include "am33xx.h" - -/** - * @addtogroup AM33xx - */ -/*@{*/ - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - - stack_addr += sizeof(rt_uint32_t); - stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); - stk = (rt_uint32_t *)stack_addr; - - *(--stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0xdeadbeef; /* r12 */ - *(--stk) = 0xdeadbeef; /* r11 */ - *(--stk) = 0xdeadbeef; /* r10 */ - *(--stk) = 0xdeadbeef; /* r9 */ - *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = 0xdeadbeef; /* r4 */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = 0xdeadbeef; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/am335x/start_gcc.S b/rt-thread/libcpu/arm/am335x/start_gcc.S deleted file mode 100644 index 07f505c..0000000 --- a/rt-thread/libcpu/arm/am335x/start_gcc.S +++ /dev/null @@ -1,252 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - */ - -.equ Mode_USR, 0x10 -.equ Mode_FIQ, 0x11 -.equ Mode_IRQ, 0x12 -.equ Mode_SVC, 0x13 -.equ Mode_ABT, 0x17 -.equ Mode_UND, 0x1B -.equ Mode_SYS, 0x1F - -.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled -.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled - -.equ UND_Stack_Size, 0x00000200 -.equ SVC_Stack_Size, 0x00000100 -.equ ABT_Stack_Size, 0x00000000 -.equ FIQ_Stack_Size, 0x00000000 -.equ IRQ_Stack_Size, 0x00000100 -.equ USR_Stack_Size, 0x00000100 - -#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - -/* stack */ -.globl stack_start -.globl stack_top - -.align 3 -stack_start: -.rept ISR_Stack_Size -.long 0 -.endr -stack_top: - -/* reset entry */ -.globl _reset -_reset: - /* set the cpu to SVC32 mode and disable interrupt */ - mrs r0, cpsr - bic r0, r0, #0x1f - orr r0, r0, #0x13 - msr cpsr_c, r0 - - /* setup stack */ - bl stack_setup - - /* clear .bss */ - mov r0,#0 /* get a zero */ - ldr r1,=__bss_start /* bss start */ - ldr r2,=__bss_end /* bss end */ - -bss_loop: - cmp r1,r2 /* check if data to clear */ - strlo r0,[r1],#4 /* clear 4 bytes */ - blo bss_loop /* loop until done */ - - /* call C++ constructors of global objects */ - ldr r0, =__ctors_start__ - ldr r1, =__ctors_end__ - -ctor_loop: - cmp r0, r1 - beq ctor_end - ldr r2, [r0], #4 - stmfd sp!, {r0-r1} - mov lr, pc - bx r2 - ldmfd sp!, {r0-r1} - b ctor_loop -ctor_end: - - /* start RT-Thread Kernel */ - ldr pc, _rtthread_startup -_rtthread_startup: - .word rtthread_startup - -stack_setup: - ldr r0, =stack_top - - @ Enter Undefined Instruction Mode and set its Stack Pointer - msr cpsr_c, #Mode_UND|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #UND_Stack_Size - - @ Enter Abort Mode and set its Stack Pointer - msr cpsr_c, #Mode_ABT|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #ABT_Stack_Size - - @ Enter FIQ Mode and set its Stack Pointer - msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #FIQ_Stack_Size - - @ Enter IRQ Mode and set its Stack Pointer - msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #IRQ_Stack_Size - - @ Enter Supervisor Mode and set its Stack Pointer - msr cpsr_c, #Mode_SVC|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #SVC_Stack_Size - - @ Enter User Mode and set its Stack Pointer - mov sp, r0 - sub sl, sp, #USR_Stack_Size - bx lr - -/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */ - .align 5 -.globl vector_undef -vector_undef: - sub sp, sp, #72 - stmia sp, {r0 - r12} @/* Calling r0-r12 */ - add r8, sp, #60 - - mrs r1, cpsr - mrs r2, spsr - orr r2,r2, #I_Bit|F_Bit - msr cpsr_c, r2 - mov r0, r0 - stmdb r8, {sp, lr} @/* Calling SP, LR */ - msr cpsr_c, r1 @/* return to Undefined Instruction mode */ - - str lr, [r8, #0] @/* Save calling PC */ - mrs r6, spsr - str r6, [r8, #4] @/* Save CPSR */ - str r0, [r8, #8] @/* Save OLD_R0 */ - mov r0, sp - - bl rt_hw_trap_udef - - ldmia sp, {r0 - r12} @/* Calling r0 - r2 */ - mov r0, r0 - ldr lr, [sp, #60] @/* Get PC */ - add sp, sp, #72 - movs pc, lr @/* return & move spsr_svc into cpsr */ - - .align 5 -.globl vector_swi -vector_swi: - bl rt_hw_trap_swi - - .align 5 -.globl vector_pabt -vector_pabt: - bl rt_hw_trap_pabt - - .align 5 -.globl vector_dabt -vector_dabt: - sub sp, sp, #72 - stmia sp, {r0 - r12} @/* Calling r0-r12 */ - add r8, sp, #60 - stmdb r8, {sp, lr} @/* Calling SP, LR */ - str lr, [r8, #0] @/* Save calling PC */ - mrs r6, spsr - str r6, [r8, #4] @/* Save CPSR */ - str r0, [r8, #8] @/* Save OLD_R0 */ - mov r0, sp - - bl rt_hw_trap_dabt - - ldmia sp, {r0 - r12} @/* Calling r0 - r2 */ - mov r0, r0 - ldr lr, [sp, #60] @/* Get PC */ - add sp, sp, #72 - movs pc, lr @/* return & move spsr_svc into cpsr */ - - .align 5 -.globl vector_resv -vector_resv: - b . - - .align 5 -.globl vector_fiq -vector_fiq: - stmfd sp!,{r0-r7,lr} - bl rt_hw_trap_fiq - ldmfd sp!,{r0-r7,lr} - subs pc,lr,#4 - -.globl rt_interrupt_enter -.globl rt_interrupt_leave -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread - -.globl rt_current_thread -.globl vmm_thread -.globl vmm_virq_check - -.globl vector_irq -vector_irq: - stmfd sp!, {r0-r12,lr} - - bl rt_interrupt_enter - bl rt_hw_trap_irq - bl rt_interrupt_leave - - @ if rt_thread_switch_interrupt_flag set, jump to - @ rt_hw_context_switch_interrupt_do and don't return - ldr r0, =rt_thread_switch_interrupt_flag - ldr r1, [r0] - cmp r1, #1 - beq rt_hw_context_switch_interrupt_do - - ldmfd sp!, {r0-r12,lr} - subs pc, lr, #4 - -rt_hw_context_switch_interrupt_do: - mov r1, #0 @ clear flag - str r1, [r0] - - ldmfd sp!, {r0-r12,lr}@ reload saved registers - stmfd sp, {r0-r2} @ save r0-r2 - - mrs r0, spsr @ get cpsr of interrupt thread - - sub r1, sp, #4*3 - sub r2, lr, #4 @ save old task's pc to r2 - - @ switch to SVC mode with no interrupt - msr cpsr_c, #I_Bit|F_Bit|Mode_SVC - - stmfd sp!, {r2} @ push old task's pc - stmfd sp!, {r3-r12,lr}@ push old task's lr,r12-r4 - ldmfd r1, {r1-r3} @ restore r0-r2 of the interrupt thread - stmfd sp!, {r1-r3} @ push old task's r0-r2 - stmfd sp!, {r0} @ push old task's cpsr - - ldr r4, =rt_interrupt_from_thread - ldr r5, [r4] - str sp, [r5] @ store sp in preempted tasks's TCB - - ldr r6, =rt_interrupt_to_thread - ldr r6, [r6] - ldr sp, [r6] @ get new task's stack pointer - - ldmfd sp!, {r4} @ pop new task's cpsr to spsr - msr spsr_cxsf, r4 - - ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr diff --git a/rt-thread/libcpu/arm/am335x/start_iar.s b/rt-thread/libcpu/arm/am335x/start_iar.s deleted file mode 100644 index beb3113..0000000 --- a/rt-thread/libcpu/arm/am335x/start_iar.s +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2015-04-06 zchong the first version - */ - - MODULE ?cstartup - - ; -------------------- -; Mode, correspords to bits 0-5 in CPSR - -MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR -I_Bit DEFINE 0x80 ; when I bit is set, IRQ is disabled -F_Bit DEFINE 0x40 ; when F bit is set, FIQ is disabled - -USR_MODE DEFINE 0x10 ; User mode -FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode -IRQ_MODE DEFINE 0x12 ; Interrupt Request mode -SVC_MODE DEFINE 0x13 ; Supervisor mode -ABT_MODE DEFINE 0x17 ; Abort mode -UND_MODE DEFINE 0x1B ; Undefined Instruction mode -SYS_MODE DEFINE 0x1F ; System mode - - - ;; Forward declaration of sections. - SECTION IRQ_STACK:DATA:NOROOT(3) - SECTION FIQ_STACK:DATA:NOROOT(3) - SECTION SVC_STACK:DATA:NOROOT(3) - SECTION ABT_STACK:DATA:NOROOT(3) - SECTION UND_STACK:DATA:NOROOT(3) - SECTION CSTACK:DATA:NOROOT(3) - SECTION .text:CODE - - - SECTION .intvec:CODE:NOROOT(5) - - PUBLIC __vector - PUBLIC __iar_program_start - - -__iar_init$$done: ; The vector table is not needed - ; until after copy initialization is done - -__vector: ; Make this a DATA label, so that stack usage - ; analysis doesn't consider it an uncalled fun - ARM - - ; All default exception handlers (except reset) are - ; defined as weak symbol definitions. - ; If a handler is defined by the application it will take precedence. - LDR PC,Reset_Addr ; Reset - LDR PC,Undefined_Addr ; Undefined instructions - LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) - LDR PC,Prefetch_Addr ; Prefetch abort - LDR PC,Abort_Addr ; Data abort - DCD 0 ; RESERVED - LDR PC,IRQ_Addr ; IRQ - LDR PC,FIQ_Addr ; FIQ - - DATA - -Reset_Addr: DCD __iar_program_start -Undefined_Addr: DCD Undefined_Handler -SWI_Addr: DCD SWI_Handler -Prefetch_Addr: DCD Prefetch_Handler -Abort_Addr: DCD Abort_Handler -IRQ_Addr: DCD IRQ_Handler -FIQ_Addr: DCD FIQ_Handler - - -; -------------------------------------------------- -; ?cstartup -- low-level system initialization code. -; -; After a reset execution starts here, the mode is ARM, supervisor -; with interrupts disabled. -; - - SECTION .text:CODE:NOROOT(2) - - EXTERN rt_hw_trap_udef - EXTERN rt_hw_trap_swi - EXTERN rt_hw_trap_pabt - EXTERN rt_hw_trap_dabt - EXTERN rt_hw_trap_fiq - EXTERN rt_hw_trap_irq - EXTERN rt_interrupt_enter - EXTERN rt_interrupt_leave - EXTERN rt_thread_switch_interrupt_flag - EXTERN rt_interrupt_from_thread - EXTERN rt_interrupt_to_thread - EXTERN rt_current_thread - EXTERN vmm_thread - EXTERN vmm_virq_check - - EXTERN __cmain - REQUIRE __vector - EXTWEAK __iar_init_core - EXTWEAK __iar_init_vfp - - - ARM - -__iar_program_start: -?cstartup: - -; -; Add initialization needed before setup of stackpointers here. -; - -; -; Initialize the stack pointers. -; The pattern below can be used for any of the exception stacks: -; FIQ, IRQ, SVC, ABT, UND, SYS. -; The USR mode uses the same stack as SYS. -; The stack segments must be defined in the linker command file, -; and be declared above. -; - - MRS r0, cpsr ; Original PSR value - - ;; Set up the interrupt stack pointer. - BIC r0, r0, #MODE_MSK ; Clear the mode bits - ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - ;; Set up the fast interrupt stack pointer. - BIC r0, r0, #MODE_MSK ; Clear the mode bits - ORR r0, r0, #FIQ_MODE ; Set FIR mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - BIC r0,r0,#MODE_MSK ; Clear the mode bits - ORR r0,r0,#ABT_MODE ; Set Abort mode bits - MSR cpsr_c,r0 ; Change the mode - LDR sp,=SFE(ABT_STACK) ; End of ABT_STACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - BIC r0,r0,#MODE_MSK ; Clear the mode bits - ORR r0,r0,#UND_MODE ; Set Undefined mode bits - MSR cpsr_c,r0 ; Change the mode - LDR sp,=SFE(UND_STACK) ; End of UND_STACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - ;; Set up the normal stack pointer. - BIC r0 ,r0, #MODE_MSK ; Clear the mode bits - ORR r0 ,r0, #SVC_MODE ; Set System mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - ;; Turn on core features assumed to be enabled. - BL __iar_init_core - - ;; Initialize VFP (if needed). - BL __iar_init_vfp - - - ;; Continue to __cmain for C-level initialization. - B __cmain - - -Undefined_Handler: - SUB sp, sp, #72 - STMIA sp, {r0 - r12} ;/* Calling r0-r12 */ - ADD r8, sp, #60 - - MRS r1, cpsr - MRS r2, spsr - ORR r2,r2, #I_Bit | F_Bit - MSR cpsr_c, r2 - MOV r0, r0 - STMDB r8, {sp, lr} ;/* Calling SP, LR */ - MSR cpsr_c, r1 ;/* return to Undefined Instruction mode */ - - STR lr, [r8, #0] ;/* Save calling PC */ - MRS r6, spsr - STR r6, [r8, #4] ;/* Save CPSR */ - STR r0, [r8, #8] ;/* Save OLD_R0 */ - MOV r0, sp - - BL rt_hw_trap_udef - - LDMIA sp, {r0 - r12} ;/* Calling r0 - r2 */ - MOV r0, r0 - LDR lr, [sp, #60] ;/* Get PC */ - ADD sp, sp, #72 - MOVS pc, lr ;/* return & move spsr_svc into cpsr */ - -SWI_Handler: - BL rt_hw_trap_swi - -Prefetch_Handler: - BL rt_hw_trap_pabt - -Abort_Handler: - SUB sp, sp, #72 - STMIA sp, {r0 - r12} ;/* Calling r0-r12 */ - ADD r8, sp, #60 - STMDB r8, {sp, lr} ;/* Calling SP, LR */ - STR lr, [r8, #0] ;/* Save calling PC */ - MRS r6, spsr - STR r6, [r8, #4] ;/* Save CPSR */ - STR r0, [r8, #8] ;/* Save OLD_R0 */ - MOV r0, sp - - BL rt_hw_trap_dabt - - LDMIA sp, {r0 - r12} ;/* Calling r0 - r2 */ - MOV r0, r0 - LDR lr, [sp, #60] ;/* Get PC */ - ADD sp, sp, #72 - MOVS pc, lr ;/* return & move spsr_svc into cpsr */ - -FIQ_Handler: - STMFD sp!,{r0-r7,lr} - BL rt_hw_trap_fiq - LDMFD sp!,{r0-r7,lr} - SUBS pc,lr,#4 - -IRQ_Handler: - STMFD sp!, {r0-r12,lr} - - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; if rt_thread_switch_interrupt_flag set, jump to - ; rt_hw_context_switch_interrupt_do and don't return - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD sp!, {r0-r12,lr} - SUBS pc, lr, #4 - -rt_hw_context_switch_interrupt_do: - MOV r1, #0 ; clear flag - STR r1, [r0] - - LDMFD sp!, {r0-r12,lr}; reload saved registers - STMFD sp, {r0-r2} ; save r0-r2 - - MRS r0, spsr ; get cpsr of interrupt thread - - SUB r1, sp, #4*3 - SUB r2, lr, #4 ; save old task's pc to r2 - - ; switch to SVC mode with no interrupt - MSR cpsr_c, #I_Bit | F_Bit | SVC_MODE - - STMFD sp!, {r2} ; push old task's pc - STMFD sp!, {r3-r12,lr}; push old task's lr,r12-r4 - LDMFD r1, {r1-r3} ; restore r0-r2 of the interrupt thread - STMFD sp!, {r1-r3} ; push old task's r0-r2 - STMFD sp!, {r0} ; push old task's cpsr - - LDR r4, =rt_interrupt_from_thread - LDR r5, [r4] - STR sp, [r5] ; store sp in preempted tasks's TCB - - LDR r6, =rt_interrupt_to_thread - LDR r6, [r6] - LDR sp, [r6] ; get new task's stack pointer - - LDMFD sp!, {r4} ; pop new task's cpsr to spsr - MSR spsr_cxsf, r4 - - LDMFD sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr - - END diff --git a/rt-thread/libcpu/arm/am335x/trap.c b/rt-thread/libcpu/arm/am335x/trap.c deleted file mode 100644 index 19cb31a..0000000 --- a/rt-thread/libcpu/arm/am335x/trap.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-09-23 Bernard first version - */ - -#include -#include - -#include "am33xx.h" -#include "interrupt.h" - -#ifdef RT_USING_GDB -#include "gdb_stub.h" -#endif - -/** - * @addtogroup AM33XX - */ -/*@{*/ - -extern struct rt_thread *rt_current_thread; -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) -extern long list_thread(void); -#endif - -/** - * this function will show registers of CPU - * - * @param regs the registers point - */ - -void rt_hw_show_register (struct rt_hw_register *regs) -{ - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); -} - -/** - * When ARM7TDMI comes across an instruction which it cannot handle, - * it takes the undefined instruction trap. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_udef(struct rt_hw_register *regs) -{ - -#ifdef RT_USING_GDB - regs->pc -= 4; //lr in undef is pc + 4 - if (gdb_undef_hook(regs)) - return; -#endif - - rt_hw_show_register(regs); - - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); - -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * The software interrupt instruction (SWI) is used for entering - * Supervisor mode, usually to request a particular supervisor - * function. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_swi(struct rt_hw_register *regs) -{ - rt_hw_show_register(regs); - - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during an instruction prefetch. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_pabt(struct rt_hw_register *regs) -{ - rt_hw_show_register(regs); - - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); - -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during a data access. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_dabt(struct rt_hw_register *regs) -{ - -#ifdef RT_USING_GDB - if (gdb_mem_fault_handler) { - regs->pc = (unsigned long)gdb_mem_fault_handler; - return; - } -#endif - rt_hw_show_register(regs); - - rt_kprintf("data abort\n"); - rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); - -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -void rt_hw_trap_irq() -{ - void *param; - unsigned long ir; - rt_isr_handler_t isr_func; - extern struct rt_irq_desc isr_table[]; - - ir = rt_hw_interrupt_get_active(INT_IRQ); - if (ir == 127) - { - /* new IRQ generation */ - rt_hw_interrupt_ack(INT_IRQ); - ir = rt_hw_interrupt_get_active(INT_IRQ); - if (ir == 127) - { - /* still spurious interrupt, get out */ - /*rt_kprintf("still spurious interrupt\n");*/ - return; - } - /*rt_kprintf("new IRQ: %d\n", ir);*/ - } - - /* get interrupt service routine */ - isr_func = isr_table[ir].handler; - param = isr_table[ir].param; - - /* turn to interrupt service routine */ - if (isr_func != RT_NULL) - isr_func(ir, param); - - /* new IRQ generation */ - rt_hw_interrupt_ack(INT_IRQ); -} - -void rt_hw_trap_fiq() -{ - void *param; - unsigned long ir; - rt_isr_handler_t isr_func; - extern struct rt_irq_desc isr_table[]; - - ir = rt_hw_interrupt_get_active(INT_FIQ); - - /* get interrupt service routine */ - isr_func = isr_table[ir].handler; - param = isr_table[ir].param; - - /* turn to interrupt service routine */ - isr_func(ir, param); - - /* new FIQ generation */ - rt_hw_interrupt_ack(INT_FIQ); -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/am335x/vector_gcc.S b/rt-thread/libcpu/arm/am335x/vector_gcc.S deleted file mode 100644 index 9c30f62..0000000 --- a/rt-thread/libcpu/arm/am335x/vector_gcc.S +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - */ - -.section .vectors, "ax" -.code 32 - -.globl system_vectors -system_vectors: - ldr pc, _vector_reset - ldr pc, _vector_undef - ldr pc, _vector_swi - ldr pc, _vector_pabt - ldr pc, _vector_dabt - ldr pc, _vector_resv - ldr pc, _vector_irq - ldr pc, _vector_fiq - -.globl _reset -.globl vector_undef -.globl vector_swi -.globl vector_pabt -.globl vector_dabt -.globl vector_resv -.globl vector_irq -.globl vector_fiq - -_vector_reset: - .word _reset -_vector_undef: - .word vector_undef -_vector_swi: - .word vector_swi -_vector_pabt: - .word vector_pabt -_vector_dabt: - .word vector_dabt -_vector_resv: - .word vector_resv -_vector_irq: - .word vector_irq -_vector_fiq: - .word vector_fiq - -.balignl 16,0xdeadbeef diff --git a/rt-thread/libcpu/arm/arm926/SConscript b/rt-thread/libcpu/arm/arm926/SConscript deleted file mode 100644 index 3760ab5..0000000 --- a/rt-thread/libcpu/arm/arm926/SConscript +++ /dev/null @@ -1,25 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] -ASFLAGS = '' - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - ASFLAGS = ' --cpreproc' - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) - -Return('group') diff --git a/rt-thread/libcpu/arm/arm926/context_gcc.S b/rt-thread/libcpu/arm/arm926/context_gcc.S deleted file mode 100644 index f69aa9f..0000000 --- a/rt-thread/libcpu/arm/arm926/context_gcc.S +++ /dev/null @@ -1,79 +0,0 @@ -;/* -; * Copyright (c) 2006-2018, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2011-08-14 weety copy from mini2440 -; */ - -#define NOINT 0xC0 - -.text -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ - .globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - MRS R0, CPSR - ORR R1, R0, #NOINT - MSR CPSR_c, R1 - BX LR - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ - .globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - MSR CPSR, R0 - BX LR - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to - */ - .globl rt_hw_context_switch -rt_hw_context_switch: - STMFD SP!, {LR} @; push pc (lr should be pushed in place of pc) - STMFD SP!, {R0-R12, LR} @; push lr & register file - MRS R4, CPSR - STMFD SP!, {R4} @; push cpsr - STR SP, [R0] @; store sp in preempted tasks tcb - LDR SP, [R1] @; get new task stack pointer - LDMFD SP!, {R4} @; pop new task spsr - MSR SPSR_cxsf, R4 - LDMFD SP!, {R0-R12, LR, PC}^ @; pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to - */ - .globl rt_hw_context_switch_to -rt_hw_context_switch_to: - LDR SP, [R0] @; get new task stack pointer - LDMFD SP!, {R4} @; pop new task cpsr - MSR SPSR_cxsf, R4 - LDMFD SP!, {R0-R12, LR, PC}^ @; pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - */ - .globl rt_thread_switch_interrupt_flag - .globl rt_interrupt_from_thread - .globl rt_interrupt_to_thread - .globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - LDR R2, =rt_thread_switch_interrupt_flag - LDR R3, [R2] - CMP R3, #1 - BEQ _reswitch - MOV R3, #1 @; set flag to 1 - STR R3, [R2] - LDR R2, =rt_interrupt_from_thread @; set rt_interrupt_from_thread - STR R0, [R2] -_reswitch: - LDR R2, =rt_interrupt_to_thread @; set rt_interrupt_to_thread - STR R1, [R2] - BX LR diff --git a/rt-thread/libcpu/arm/arm926/context_iar.S b/rt-thread/libcpu/arm/arm926/context_iar.S deleted file mode 100644 index f4588ec..0000000 --- a/rt-thread/libcpu/arm/arm926/context_iar.S +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-08-14 weety copy from mini2440 - * 2015-04-15 ArdaFu convert from context_gcc.s - */ - -#define NOINT 0xc0 - - SECTION .text:CODE(6) -/* - * rt_base_t rt_hw_interrupt_disable(); - */ - PUBLIC rt_hw_interrupt_disable -rt_hw_interrupt_disable: - MRS R0, CPSR - ORR R1, R0, #NOINT - MSR CPSR_C, R1 - MOV PC, LR - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ - PUBLIC rt_hw_interrupt_enable -rt_hw_interrupt_enable: - MSR CPSR_CXSF, R0 - MOV PC, LR - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to - */ - PUBLIC rt_hw_context_switch -rt_hw_context_switch: - STMFD SP!, {LR} ; push pc (lr should be pushed in place of PC) - STMFD SP!, {R0-R12, LR} ; push lr & register file - MRS R4, CPSR - STMFD SP!, {R4} ; push cpsr - STR SP, [R0] ; store sp in preempted tasks TCB - LDR SP, [R1] ; get new task stack pointer - LDMFD SP!, {R4} ; pop new task spsr - MSR SPSR_cxsf, R4 - LDMFD SP!, {R0-R12, LR, PC}^ ; pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to - */ - PUBLIC rt_hw_context_switch_to -rt_hw_context_switch_to: - LDR SP, [R0] ; get new task stack pointer - LDMFD SP!, {R4} ; pop new task spsr - MSR SPSR_cxsf, R4 - LDMFD SP!, {R0-R12, LR, PC}^ ; pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - */ - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - PUBLIC rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - LDR R2, =rt_thread_switch_interrupt_flag - LDR R3, [R2] - CMP R3, #1 - BEQ _reswitch - MOV R3, #1 ; set flag to 1 - STR R3, [R2] - LDR R2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR R0, [R2] -_reswitch: - LDR R2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR R1, [R2] - MOV PC, LR - END - diff --git a/rt-thread/libcpu/arm/arm926/context_rvds.S b/rt-thread/libcpu/arm/arm926/context_rvds.S deleted file mode 100644 index 03eff68..0000000 --- a/rt-thread/libcpu/arm/arm926/context_rvds.S +++ /dev/null @@ -1,91 +0,0 @@ -;/* -; * Copyright (c) 2006-2018, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2011-08-14 weety copy from mini2440 -; */ - -NOINT EQU 0XC0 ; disable interrupt in psr - - AREA |.TEXT|, CODE, READONLY, ALIGN=2 - ARM - REQUIRE8 - PRESERVE8 - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ -rt_hw_interrupt_disable PROC - EXPORT rt_hw_interrupt_disable - MRS R0, CPSR - ORR R1, R0, #NOINT - MSR CPSR_C, R1 - BX LR - ENDP - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ -rt_hw_interrupt_enable proc - export rt_hw_interrupt_enable - msr cpsr_c, r0 - bx lr - endp - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ -rt_hw_context_switch proc - export rt_hw_context_switch - stmfd sp!, {lr} ; push pc (lr should be pushed in place of pc) - stmfd sp!, {r0-r12, lr} ; push lr & register file - mrs r4, cpsr - stmfd sp!, {r4} ; push cpsr - str sp, [r0] ; store sp in preempted tasks tcb - ldr sp, [r1] ; get new task stack pointer - ldmfd sp!, {r4} ; pop new task spsr - msr spsr_cxsf, r4 - ldmfd sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc - endp - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; */ -rt_hw_context_switch_to proc - export rt_hw_context_switch_to - ldr sp, [r0] ; get new task stack pointer - ldmfd sp!, {r4} ; pop new task spsr - msr spsr_cxsf, r4 - ldmfd sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc - endp - -;/* -; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); -; */ - import rt_thread_switch_interrupt_flag - import rt_interrupt_from_thread - import rt_interrupt_to_thread - -rt_hw_context_switch_interrupt proc - export rt_hw_context_switch_interrupt - ldr r2, =rt_thread_switch_interrupt_flag - ldr r3, [r2] - cmp r3, #1 - beq _reswitch - mov r3, #1 ; set flag to 1 - str r3, [r2] - ldr r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - str r0, [r2] -_reswitch - ldr r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - str r1, [r2] - bx lr - endp - - end diff --git a/rt-thread/libcpu/arm/arm926/cpuport.c b/rt-thread/libcpu/arm/arm926/cpuport.c deleted file mode 100644 index d27ee10..0000000 --- a/rt-thread/libcpu/arm/arm926/cpuport.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety modified from mini2440 - * 2015-04-15 ArdaFu Add code for IAR - */ - -#include -#include - -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) - -extern void machine_reset(void); -extern void machine_shutdown(void); - -#if defined(__GNUC__) || defined(__ICCARM__) -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - __asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r"(i)); - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - __asm volatile(\ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - : "r"(bit) \ - : "memory"); -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - __asm volatile(\ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - : "r"(bit) \ - : "memory"); -} -#endif - -#if defined(__CC_ARM) -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - __asm volatile - { - mrc p15, 0, i, c1, c0, 0 - } - - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } -} -#endif - -/** - * enable I-Cache - * - */ -void rt_hw_cpu_icache_enable() -{ - cache_enable(ICACHE_MASK); -} - -/** - * disable I-Cache - * - */ -void rt_hw_cpu_icache_disable() -{ - cache_disable(ICACHE_MASK); -} - -/** - * return the status of I-Cache - * - */ -rt_base_t rt_hw_cpu_icache_status() -{ - return (cp15_rd() & ICACHE_MASK); -} - -/** - * enable D-Cache - * - */ -void rt_hw_cpu_dcache_enable() -{ - cache_enable(DCACHE_MASK); -} - -/** - * disable D-Cache - * - */ -void rt_hw_cpu_dcache_disable() -{ - cache_disable(DCACHE_MASK); -} - -/** - * return the status of D-Cache - * - */ -rt_base_t rt_hw_cpu_dcache_status() -{ - return (cp15_rd() & DCACHE_MASK); -} - -/** - * reset cpu by dog's time-out - * - */ -RT_WEAK void rt_hw_cpu_reset() -{ - - rt_kprintf("Restarting system...\n"); - machine_reset(); - - while (1); /* loop forever and wait for reset to happen */ - - /* NEVER REACHED */ -} - -/** - * shutdown CPU - * - */ -RT_WEAK void rt_hw_cpu_shutdown() -{ - rt_base_t level; - rt_kprintf("shutdown...\n"); - - level = rt_hw_interrupt_disable(); - machine_shutdown(); - while (level) - { - RT_ASSERT(0); - } -} - -#ifdef RT_USING_CPU_FFS -/** - * This function finds the first bit set (beginning with the least significant bit) - * in value and return the index of that bit. - * - * Bits are numbered starting at 1 (the least significant bit). A return value of - * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function - * shall return 0. - */ -#if defined(__CC_ARM) -int __rt_ffs(int value) -{ - register rt_uint32_t x; - - if (value == 0) - return value; - - __asm - { - rsb x, value, #0 - and x, x, value - clz x, x - rsb x, x, #32 - } - - return x; -} -#elif defined(__GNUC__) || defined(__ICCARM__) -int __rt_ffs(int value) -{ - return __builtin_ffs(value); -} -#endif - -#endif - - -/*@}*/ diff --git a/rt-thread/libcpu/arm/arm926/machine.c b/rt-thread/libcpu/arm/arm926/machine.c deleted file mode 100644 index 19baa4d..0000000 --- a/rt-thread/libcpu/arm/arm926/machine.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-02-08 RT-Thread the first version - */ - -#include -#include - -RT_WEAK void machine_reset(void) -{ - rt_kprintf("reboot system...\n"); - rt_hw_interrupt_disable(); - while (1); -} - -RT_WEAK void machine_shutdown(void) -{ - rt_kprintf("shutdown...\n"); - rt_hw_interrupt_disable(); - while (1); -} - diff --git a/rt-thread/libcpu/arm/arm926/mmu.c b/rt-thread/libcpu/arm/arm926/mmu.c deleted file mode 100644 index 50ada17..0000000 --- a/rt-thread/libcpu/arm/arm926/mmu.c +++ /dev/null @@ -1,443 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2015-04-15 ArdaFu Add code for IAR - */ - -#include "mmu.h" - -/*----- Keil -----------------------------------------------------------------*/ -#ifdef __CC_ARM -void mmu_setttbase(rt_uint32_t i) -{ - register rt_uint32_t value; - - /* Invalidates all TLBs.Domain access is selected as - * client by configuring domain access register, - * in that case access controlled by permission value - * set by page table entry - */ - value = 0; - __asm volatile{ mcr p15, 0, value, c8, c7, 0 } - value = 0x55555555; - __asm volatile { mcr p15, 0, value, c3, c0, 0 } - __asm volatile { mcr p15, 0, i, c2, c0, 0 } -} - -void mmu_set_domain(rt_uint32_t i) -{ - __asm volatile { mcr p15, 0, i, c3, c0, 0 } -} - -void mmu_enable() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_enable_icache() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_enable_dcache() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable_icache() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable_dcache() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_enable_alignfault() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable_alignfault() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_clean_invalidated_cache_index(int index) -{ - __asm volatile { mcr p15, 0, index, c7, c14, 2 } -} - -void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~(CACHE_LINE_SIZE - 1); - - while (ptr < buffer + size) - { - __asm volatile { MCR p15, 0, ptr, c7, c14, 1 } - ptr += CACHE_LINE_SIZE; - } -} - -void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~(CACHE_LINE_SIZE - 1); - - while (ptr < buffer + size) - { - __asm volatile { MCR p15, 0, ptr, c7, c10, 1 } - ptr += CACHE_LINE_SIZE; - } -} - -void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~(CACHE_LINE_SIZE - 1); - - while (ptr < buffer + size) - { - __asm volatile { MCR p15, 0, ptr, c7, c6, 1 } - ptr += CACHE_LINE_SIZE; - } -} - -void mmu_invalidate_tlb() -{ - register rt_uint32_t value; - - value = 0; - __asm volatile { mcr p15, 0, value, c8, c7, 0 } -} - -void mmu_invalidate_icache() -{ - register rt_uint32_t value; - - value = 0; - - __asm volatile { mcr p15, 0, value, c7, c5, 0 } -} - - -void mmu_invalidate_dcache_all() -{ - register rt_uint32_t value; - - value = 0; - - __asm volatile { mcr p15, 0, value, c7, c6, 0 } -} -/*----- GNU ------------------------------------------------------------------*/ -#elif defined(__GNUC__) || defined(__ICCARM__) -void mmu_setttbase(register rt_uint32_t i) -{ - register rt_uint32_t value; - - /* Invalidates all TLBs.Domain access is selected as - * client by configuring domain access register, - * in that case access controlled by permission value - * set by page table entry - */ - value = 0; - asm volatile("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); - - value = 0x55555555; - asm volatile("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); - - asm volatile("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); - -} - -void mmu_set_domain(register rt_uint32_t i) -{ - asm volatile("mcr p15,0, %0, c3, c0, 0": :"r"(i)); -} - -void mmu_enable() -{ - asm volatile - ( - "mrc p15, 0, r0, c1, c0, 0 \n" - "orr r0, r0, #0x1 \n" - "mcr p15, 0, r0, c1, c0, 0 \n" - :::"r0" - ); -} - -void mmu_disable() -{ - asm volatile - ( - "mrc p15, 0, r0, c1, c0, 0 \n" - "bic r0, r0, #0x1 \n" - "mcr p15, 0, r0, c1, c0, 0 \n" - :::"r0" - ); - -} - -void mmu_enable_icache() -{ - asm volatile - ( - "mrc p15, 0, r0, c1, c0, 0 \n" - "orr r0, r0, #(1<<12) \n" - "mcr p15, 0, r0, c1, c0, 0 \n" - :::"r0" - ); -} - -void mmu_enable_dcache() -{ - asm volatile - ( - "mrc p15, 0, r0, c1, c0, 0 \n" - "orr r0, r0, #(1<<2) \n" - "mcr p15, 0, r0, c1, c0, 0 \n" - :::"r0" - ); - -} - -void mmu_disable_icache() -{ - asm volatile - ( - "mrc p15, 0, r0, c1, c0, 0 \n" - "bic r0, r0, #(1<<12) \n" - "mcr p15, 0, r0, c1, c0, 0 \n" - :::"r0" - ); - -} - -void mmu_disable_dcache() -{ - asm volatile - ( - "mrc p15, 0, r0, c1, c0, 0 \n" - "bic r0, r0, #(1<<2) \n" - "mcr p15, 0, r0, c1, c0, 0 \n" - :::"r0" - ); - -} - -void mmu_enable_alignfault() -{ - asm volatile - ( - "mrc p15, 0, r0, c1, c0, 0 \n" - "orr r0, r0, #1 \n" - "mcr p15, 0, r0, c1, c0, 0 \n" - :::"r0" - ); - -} - -void mmu_disable_alignfault() -{ - asm volatile - ( - "mrc p15, 0, r0, c1, c0, 0 \n" - "bic r0, r0, #1 \n" - "mcr p15, 0, r0, c1, c0, 0 \n" - :::"r0" - ); - -} - -void mmu_clean_invalidated_cache_index(int index) -{ - asm volatile("mcr p15, 0, %0, c7, c14, 2": :"r"(index)); -} - -void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~(CACHE_LINE_SIZE - 1); - - while (ptr < buffer + size) - { - asm volatile("mcr p15, 0, %0, c7, c14, 1": :"r"(ptr)); - - ptr += CACHE_LINE_SIZE; - } -} - - -void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~(CACHE_LINE_SIZE - 1); - - while (ptr < buffer + size) - { - asm volatile("mcr p15, 0, %0, c7, c10, 1": :"r"(ptr)); - - ptr += CACHE_LINE_SIZE; - } -} - -void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~(CACHE_LINE_SIZE - 1); - - while (ptr < buffer + size) - { - asm volatile("mcr p15, 0, %0, c7, c6, 1": :"r"(ptr)); - - ptr += CACHE_LINE_SIZE; - } -} - -void mmu_invalidate_tlb() -{ - asm volatile("mcr p15, 0, %0, c8, c7, 0": :"r"(0)); - -} - -void mmu_invalidate_icache() -{ - asm volatile("mcr p15, 0, %0, c7, c5, 0": :"r"(0)); - -} - -void mmu_invalidate_dcache_all() -{ - asm volatile("mcr p15, 0, %0, c7, c6, 0": :"r"(0)); - -} -#endif - -/* level1 page table */ -#if defined(__ICCARM__) -#pragma data_alignment=(16*1024) -static volatile rt_uint32_t _page_table[4 * 1024]; -#else -static volatile rt_uint32_t _page_table[4 * 1024] \ -__attribute__((aligned(16 * 1024))); -#endif - -void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, - rt_uint32_t paddrStart, rt_uint32_t attr) -{ - volatile rt_uint32_t *pTT; - volatile int nSec; - int i = 0; - pTT = (rt_uint32_t *)_page_table + (vaddrStart >> 20); - nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); - for (i = 0; i <= nSec; i++) - { - *pTT = attr | (((paddrStart >> 20) + i) << 20); - pTT++; - } -} - -void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size) -{ - /* disable I/D cache */ - mmu_disable_dcache(); - mmu_disable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); - - /* set page table */ - for (; size > 0; size--) - { - mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end, - mdesc->paddr_start, mdesc->attr); - mdesc++; - } - - /* set MMU table address */ - mmu_setttbase((rt_uint32_t)_page_table); - - /* enables MMU */ - mmu_enable(); - - /* enable Instruction Cache */ - mmu_enable_icache(); - - /* enable Data Cache */ - mmu_enable_dcache(); - - mmu_invalidate_icache(); - mmu_invalidate_dcache_all(); -} diff --git a/rt-thread/libcpu/arm/arm926/mmu.h b/rt-thread/libcpu/arm/arm926/mmu.h deleted file mode 100644 index ecd39d4..0000000 --- a/rt-thread/libcpu/arm/arm926/mmu.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-02-08 RT-Thread the first version - */ - -#ifndef __MMU_H__ -#define __MMU_H__ - -#include - -#define CACHE_LINE_SIZE 32 - -#define DESC_SEC (0x2|(1<<4)) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO - -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) - -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) - -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ - -struct mem_desc -{ - rt_uint32_t vaddr_start; - rt_uint32_t vaddr_end; - rt_uint32_t paddr_start; - rt_uint32_t attr; -}; - -void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size); -void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size); -void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); -void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); -#endif diff --git a/rt-thread/libcpu/arm/arm926/stack.c b/rt-thread/libcpu/arm/arm926/stack.c deleted file mode 100644 index caf16c4..0000000 --- a/rt-thread/libcpu/arm/arm926/stack.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety copy from mini2440 - */ -#include - -/*****************************/ -/* CPU Mode */ -/*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - - stack_addr += sizeof(rt_uint32_t); - stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); - stk = (rt_uint32_t *)stack_addr; - - *(--stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0xdeadbeef; /* r12 */ - *(--stk) = 0xdeadbeef; /* r11 */ - *(--stk) = 0xdeadbeef; /* r10 */ - *(--stk) = 0xdeadbeef; /* r9 */ - *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = 0xdeadbeef; /* r4 */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = 0xdeadbeef; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} diff --git a/rt-thread/libcpu/arm/arm926/start_gcc.S b/rt-thread/libcpu/arm/arm926/start_gcc.S deleted file mode 100644 index 56f996c..0000000 --- a/rt-thread/libcpu/arm/arm926/start_gcc.S +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version - * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP - * 2015-04-21 ArdaFu Remove remap code. Using mmu to map vector table - * 2015-06-04 aozima Align stack address to 8 byte. - */ - -.equ MODE_USR, 0x10 -.equ MODE_FIQ, 0x11 -.equ MODE_IRQ, 0x12 -.equ MODE_SVC, 0x13 -.equ MODE_ABT, 0x17 -.equ MODE_UND, 0x1B -.equ MODE_SYS, 0x1F -.equ MODEMASK, 0x1F -.equ NOINT, 0xC0 - -.equ I_BIT, 0x80 -.equ F_BIT, 0x40 - -.equ UND_STACK_SIZE, 0x00000100 -.equ SVC_STACK_SIZE, 0x00000100 -.equ ABT_STACK_SIZE, 0x00000100 -.equ FIQ_STACK_SIZE, 0x00000100 -.equ IRQ_STACK_SIZE, 0x00000100 -.equ SYS_STACK_SIZE, 0x00000100 - - /* - *************************************** - * Interrupt vector table - *************************************** - */ -.section .vectors -.code 32 - -.global system_vectors -system_vectors: - ldr pc, _vector_reset - ldr pc, _vector_undef - ldr pc, _vector_swi - ldr pc, _vector_pabt - ldr pc, _vector_dabt - ldr pc, _vector_resv - ldr pc, _vector_irq - ldr pc, _vector_fiq - -_vector_reset: - .word reset -_vector_undef: - .word vector_undef -_vector_swi: - .word vector_swi -_vector_pabt: - .word vector_pabt -_vector_dabt: - .word vector_dabt -_vector_resv: - .word vector_resv -_vector_irq: - .word vector_irq -_vector_fiq: - .word vector_fiq - -.balignl 16,0xdeadbeef - - /* - *************************************** - * Stack and Heap Definitions - *************************************** - */ - .section .data - .space UND_STACK_SIZE - .align 3 - .global und_stack_start -und_stack_start: - - .space ABT_STACK_SIZE - .align 3 - .global abt_stack_start -abt_stack_start: - - .space FIQ_STACK_SIZE - .align 3 - .global fiq_stack_start -fiq_stack_start: - - .space IRQ_STACK_SIZE - .align 3 - .global irq_stack_start -irq_stack_start: - - .skip SYS_STACK_SIZE - .align 3 - .global sys_stack_start -sys_stack_start: - - .space SVC_STACK_SIZE - .align 3 - .global svc_stack_start -svc_stack_start: - -/* - *************************************** - * Startup Code - *************************************** - */ - .section .text - .global reset -reset: - /* Enter svc mode and mask interrupts */ - mrs r0, cpsr - bic r0, r0, #MODEMASK - orr r0, r0, #MODE_SVC|NOINT - msr cpsr_cxsf, r0 - - /* init cpu */ - bl cpu_init_crit - - /* Call low level init function */ - ldr sp, =svc_stack_start - ldr r0, =rt_low_level_init - blx r0 - - /* init stack */ - bl stack_setup - - /* clear bss */ - mov r0, #0 - ldr r1, =__bss_start - ldr r2, =__bss_end - -bss_clear_loop: - cmp r1, r2 - strlo r0, [r1], #4 - blo bss_clear_loop - - /* call c++ constructors of global objects */ - /* - ldr r0, =__ctors_start__ - ldr r1, =__ctors_end__ - -ctor_loop: - cmp r0, r1 - beq ctor_end - ldr r2, [r0], #4 - stmfd sp!, {r0-r1} - mov lr, pc - bx r2 - ldmfd sp!, {r0-r1} - b ctor_loop -ctor_end: - */ - /* start RT-Thread Kernel */ - ldr pc, _rtthread_startup -_rtthread_startup: - .word rtthread_startup - - - -cpu_init_crit: - /* invalidate I/D caches */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 - mcr p15, 0, r0, c8, c7, 0 - - /* disable MMU stuff and caches */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 - bic r0, r0, #0x00000087 - orr r0, r0, #0x00000002 - orr r0, r0, #0x00001000 - mcr p15, 0, r0, c1, c0, 0 - - bx lr - -stack_setup: - /* Setup Stack for each mode */ - mrs r0, cpsr - bic r0, r0, #MODEMASK - - orr r1, r0, #MODE_UND|NOINT - msr cpsr_cxsf, r1 - ldr sp, =und_stack_start - - orr r1, r0, #MODE_ABT|NOINT - msr cpsr_cxsf, r1 - ldr sp, =abt_stack_start - - orr r1, r0, #MODE_IRQ|NOINT - msr cpsr_cxsf, r1 - ldr sp, =irq_stack_start - - orr r1, r0, #MODE_FIQ|NOINT - msr cpsr_cxsf, r1 - ldr sp, =fiq_stack_start - - orr r1, r0, #MODE_SYS|NOINT - msr cpsr_cxsf,r1 - ldr sp, =sys_stack_start - - orr r1, r0, #MODE_SVC|NOINT - msr cpsr_cxsf, r1 - ldr sp, =svc_stack_start - - bx lr - -/* - *************************************** - * exception handlers - *************************************** - */ - /* Interrupt */ -vector_fiq: - stmfd sp!,{r0-r7,lr} - bl rt_hw_trap_fiq - ldmfd sp!,{r0-r7,lr} - subs pc, lr, #4 - -vector_irq: - stmfd sp!, {r0-r12,lr} - - bl rt_interrupt_enter - bl rt_hw_trap_irq - bl rt_interrupt_leave - - ldr r0, =rt_thread_switch_interrupt_flag - ldr r1, [r0] - cmp r1, #1 - beq rt_hw_context_switch_interrupt_do - - ldmfd sp!, {r0-r12,lr} - subs pc, lr, #4 - -rt_hw_context_switch_interrupt_do: - mov r1, #0 - str r1, [r0] - - mov r1, sp - add sp, sp, #4*4 - ldmfd sp!, {r4-r12,lr} - mrs r0, spsr - sub r2, lr, #4 - - msr cpsr_c, #I_BIT|F_BIT|MODE_SVC - - stmfd sp!, {r2} - stmfd sp!, {r4-r12,lr} - ldmfd r1, {r1-r4} - stmfd sp!, {r1-r4} - stmfd sp!, {r0} - - ldr r4, =rt_interrupt_from_thread - ldr r5, [r4] - str sp, [r5] - - ldr r6, =rt_interrupt_to_thread - ldr r6, [r6] - ldr sp, [r6] - - ldmfd sp!, {r4} - msr spsr_cxsf, r4 - - ldmfd sp!, {r0-r12,lr,pc}^ - - /* Exception */ -.macro push_svc_reg - sub sp, sp, #17 * 4 - stmia sp, {r0 - r12} - mov r0, sp - mrs r6, spsr - str lr, [r0, #15*4] - str r6, [r0, #16*4] - str sp, [r0, #13*4] - str lr, [r0, #14*4] -.endm - -vector_swi: - push_svc_reg - bl rt_hw_trap_swi - b . - -vector_undef: - push_svc_reg - bl rt_hw_trap_udef - b . - -vector_pabt: - push_svc_reg - bl rt_hw_trap_pabt - b . - -vector_dabt: - push_svc_reg - bl rt_hw_trap_dabt - b . - -vector_resv: - push_svc_reg - bl rt_hw_trap_resv - b . diff --git a/rt-thread/libcpu/arm/arm926/start_iar.S b/rt-thread/libcpu/arm/arm926/start_iar.S deleted file mode 100644 index 080acd5..0000000 --- a/rt-thread/libcpu/arm/arm926/start_iar.S +++ /dev/null @@ -1,278 +0,0 @@ -;/* -; * Copyright (c) 2006-2018, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2011-01-13 weety first version -; * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP -; * 2015-04-21 ArdaFu Remove remap code. Using mmu to map vector table -; * 2015-06-04 aozima Align stack address to 8 byte. -; */ - -#include "rt_low_level_init.h" - -#define S_FRAME_SIZE (18*4) ;72 - -;#define S_SPSR (17*4) ;SPSR -;#define S_CPSR (16*4) ;CPSR -#define S_PC (15*4) ;R15 -;#define S_LR (14*4) ;R14 -;#define S_SP (13*4) ;R13 - -;#define S_IP (12*4) ;R12 -;#define S_FP (11*4) ;R11 -;#define S_R10 (10*4) -;#define S_R9 (9*4) -;#define S_R8 (8*4) -;#define S_R7 (7*4) -;#define S_R6 (6*4) -;#define S_R5 (5*4) -;#define S_R4 (4*4) -;#define S_R3 (3*4) -;#define S_R2 (2*4) -;#define S_R1 (1*4) -;#define S_R0 (0*4) - -#define MODE_SYS 0x1F -#define MODE_FIQ 0x11 -#define MODE_IRQ 0x12 -#define MODE_SVC 0x13 -#define MODE_ABT 0x17 -#define MODE_UND 0x1B -#define MODEMASK 0x1F - -#define NOINT 0xC0 - -;----------------------- Stack and Heap Definitions ---------------------------- - MODULE ?cstartup - SECTION .noinit:DATA:NOROOT(3) - DATA - - ALIGNRAM 3 - DS8 UND_STK_SIZE - PUBLIC UND_STACK_START -UND_STACK_START: - - ALIGNRAM 3 - DS8 ABT_STK_SIZE - PUBLIC ABT_STACK_START -ABT_STACK_START: - - ALIGNRAM 3 - DS8 FIQ_STK_SIZE - PUBLIC FIQ_STACK_START -FIQ_STACK_START: - - ALIGNRAM 3 - DS8 IRQ_STK_SIZE - PUBLIC IRQ_STACK_START -IRQ_STACK_START: - - ALIGNRAM 3 - DS8 SYS_STK_SIZE - PUBLIC SYS_STACK_START -SYS_STACK_START: - - ALIGNRAM 3 - DS8 SVC_STK_SIZE - PUBLIC SVC_STACK_START -SVC_STACK_START: - -;--------------Jump vector table------------------------------------------------ - SECTION .intvec:CODE:ROOT(2) - ARM - PUBLIC Entry_Point -Entry_Point: -__iar_init$$done: ; The interrupt vector is not needed - ; until after copy initialization is done - LDR PC, vector_reset - LDR PC, vector_undef - LDR PC, vector_swi - LDR PC, vector_pabt - LDR PC, vector_dabt - LDR PC, vector_resv - LDR PC, vector_irq - LDR PC, vector_fiq - -vector_reset: - DC32 Reset_Handler -vector_undef: - DC32 Undef_Handler -vector_swi: - DC32 SWI_Handler -vector_pabt: - DC32 PAbt_Handler -vector_dabt: - DC32 DAbt_Handler -vector_resv: - DC32 Resv_Handler -vector_irq: - DC32 IRQ_Handler -vector_fiq: - DC32 FIQ_Handler - -;----------------- Reset Handler ----------------------------------------------- - EXTERN rt_low_level_init - EXTERN ?main - PUBLIC __iar_program_start -__iar_program_start: -Reset_Handler: - ; Set the cpu to SVC32 mode - MRS R0, CPSR - BIC R0, R0, #MODEMASK - ORR R0, R0, #MODE_SVC|NOINT - MSR CPSR_cxsf, R0 - - ; Set CO-Processor - ; little-end，disbale I/D Cache MMU, vector table is 0x00000000 - MRC P15, 0, R0, C1, C0, 0 ; Read CP15 - LDR R1, =0x00003085 ; set clear bits - BIC R0, R0, R1 - MCR P15, 0, R0, C1, C0, 0 ; Write CP15 - - ; Call low level init function, - ; disable and clear all IRQs, Init MMU, Init interrupt controller, etc. - LDR SP, =SVC_STACK_START - LDR R0, =rt_low_level_init - BLX R0 - -Setup_Stack: - ; Setup Stack for each mode - MRS R0, CPSR - BIC R0, R0, #MODEMASK - - ORR R1, R0, #MODE_UND|NOINT - MSR CPSR_cxsf, R1 ; Undef mode - LDR SP, =UND_STACK_START - - ORR R1,R0,#MODE_ABT|NOINT - MSR CPSR_cxsf,R1 ; Abort mode - LDR SP, =ABT_STACK_START - - ORR R1,R0,#MODE_IRQ|NOINT - MSR CPSR_cxsf,R1 ; IRQ mode - LDR SP, =IRQ_STACK_START - - ORR R1,R0,#MODE_FIQ|NOINT - MSR CPSR_cxsf,R1 ; FIQ mode - LDR SP, =FIQ_STACK_START - - ORR R1,R0,#MODE_SYS|NOINT - MSR CPSR_cxsf,R1 ; SYS/User mode - LDR SP, =SYS_STACK_START - - ORR R1,R0,#MODE_SVC|NOINT - MSR CPSR_cxsf,R1 ; SVC mode - LDR SP, =SVC_STACK_START - - ; Enter the C code - LDR R0, =?main - BLX R0 - -;----------------- Exception Handler ------------------------------------------- - IMPORT rt_hw_trap_udef - IMPORT rt_hw_trap_swi - IMPORT rt_hw_trap_pabt - IMPORT rt_hw_trap_dabt - IMPORT rt_hw_trap_resv - IMPORT rt_hw_trap_irq - IMPORT rt_hw_trap_fiq - - IMPORT rt_interrupt_enter - IMPORT rt_interrupt_leave - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - - SECTION .text:CODE:ROOT(2) - ARM -Undef_Handler: - SUB SP, SP, #S_FRAME_SIZE - STMIA SP, {R0 - R12} ; Calling R0-R12 - ADD R8, SP, #S_PC - STMDB R8, {SP, LR} ; Calling SP, LR - STR LR, [R8, #0] ; Save calling PC - MRS R6, SPSR - STR R6, [R8, #4] ; Save CPSR - STR R0, [R8, #8] ; Save SPSR - MOV R0, SP - BL rt_hw_trap_udef - -SWI_Handler: - BL rt_hw_trap_swi - -PAbt_Handler: - BL rt_hw_trap_pabt - -DAbt_Handler: - SUB SP, SP, #S_FRAME_SIZE - STMIA SP, {R0 - R12} ; Calling R0-R12 - ADD R8, SP, #S_PC - STMDB R8, {SP, LR} ; Calling SP, LR - STR LR, [R8, #0] ; Save calling PC - MRS R6, SPSR - STR R6, [R8, #4] ; Save CPSR - STR R0, [R8, #8] ; Save SPSR - MOV R0, SP - BL rt_hw_trap_dabt - -Resv_Handler: - BL rt_hw_trap_resv - -IRQ_Handler: - STMFD SP!, {R0-R12,LR} - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; If rt_thread_switch_interrupt_flag set, - ; jump to rt_hw_context_switch_interrupt_do and don't return - LDR R0, =rt_thread_switch_interrupt_flag - LDR R1, [R0] - CMP R1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD SP!, {R0-R12,LR} - SUBS PC, LR, #4 - -FIQ_Handler: - STMFD SP!, {R0-R7,LR} - BL rt_hw_trap_fiq - LDMFD SP!, {R0-R7,LR} - SUBS PC, LR, #4 - -;------ void rt_hw_context_switch_interrupt_do(rt_base_t flag) ----------------- -rt_hw_context_switch_interrupt_do: - MOV R1, #0 ; Clear flag - STR R1, [R0] ; Save to flag variable - - LDMFD SP!, {R0-R12,LR} ; Reload saved registers - STMFD SP, {R0-R2} ; Save R0-R2 - SUB R1, SP, #4*3 ; Save old task's SP to R1 - SUB R2, LR, #4 ; Save old task's PC to R2 - - MRS R0, SPSR ; Get CPSR of interrupt thread - - MSR CPSR_c, #MODE_SVC|NOINT ; Switch to SVC mode and no interrupt - - STMFD SP!, {R2} ; Push old task's PC - STMFD SP!, {R3-R12,LR} ; Push old task's LR,R12-R3 - LDMFD R1, {R1-R3} - STMFD SP!, {R1-R3} ; Push old task's R2-R0 - STMFD SP!, {R0} ; Push old task's CPSR - - LDR R4, =rt_interrupt_from_thread - LDR R5, [R4] ; R5 = stack ptr in old tasks's TCB - STR SP, [R5] ; Store SP in preempted tasks's TCB - - LDR R6, =rt_interrupt_to_thread - LDR R6, [R6] ; R6 = stack ptr in new tasks's TCB - LDR SP, [R6] ; Get new task's stack pointer - - LDMFD SP!, {R4} ; Pop new task's SPSR - MSR SPSR_cxsf, R4 - - LDMFD SP!, {R0-R12,LR,PC}^ ; pop new task's R0-R12,LR & PC SPSR to CPSR - END diff --git a/rt-thread/libcpu/arm/arm926/start_rvds.S b/rt-thread/libcpu/arm/arm926/start_rvds.S deleted file mode 100644 index fc7e84f..0000000 --- a/rt-thread/libcpu/arm/arm926/start_rvds.S +++ /dev/null @@ -1,301 +0,0 @@ -;/* -; * Copyright (c) 2006-2018, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2011-08-14 weety first version -; * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP -; * 2015-04-21 ArdaFu Remove remap code. Using mmu to map vector table -; * 2015-06-04 aozima Align stack address to 8 byte. -; */ - -UND_STK_SIZE EQU 512 -SVC_STK_SIZE EQU 4096 -ABT_STK_SIZE EQU 512 -IRQ_STK_SIZE EQU 1024 -FIQ_STK_SIZE EQU 1024 -SYS_STK_SIZE EQU 512 -Heap_Size EQU 512 - -S_FRAME_SIZE EQU (18*4) ;72 -S_PC EQU (15*4) ;R15 - -MODE_USR EQU 0X10 -MODE_FIQ EQU 0X11 -MODE_IRQ EQU 0X12 -MODE_SVC EQU 0X13 -MODE_ABT EQU 0X17 -MODE_UND EQU 0X1B -MODE_SYS EQU 0X1F -MODEMASK EQU 0X1F - -NOINT EQU 0xC0 - -;----------------------- Stack and Heap Definitions ---------------------------- - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem - - SPACE UND_STK_SIZE - EXPORT UND_STACK_START -UND_STACK_START - - ALIGN 8 - SPACE ABT_STK_SIZE - EXPORT ABT_STACK_START -ABT_STACK_START - - ALIGN 8 - SPACE FIQ_STK_SIZE - EXPORT FIQ_STACK_START -FIQ_STACK_START - - ALIGN 8 - SPACE IRQ_STK_SIZE - EXPORT IRQ_STACK_START -IRQ_STACK_START - - ALIGN 8 - SPACE SYS_STK_SIZE - EXPORT SYS_STACK_START -SYS_STACK_START - - ALIGN 8 - SPACE SVC_STK_SIZE - EXPORT SVC_STACK_START -SVC_STACK_START -Stack_Top -__initial_sp - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 -;--------------Jump vector table------------------------------------------------ - EXPORT Entry_Point - AREA RESET, CODE, READONLY - ARM -Entry_Point - LDR PC, vector_reset - LDR PC, vector_undef - LDR PC, vector_swi - LDR PC, vector_pabt - LDR PC, vector_dabt - LDR PC, vector_resv - LDR PC, vector_irq - LDR PC, vector_fiq - -vector_reset - DCD Reset_Handler -vector_undef - DCD Undef_Handler -vector_swi - DCD SWI_Handler -vector_pabt - DCD PAbt_Handler -vector_dabt - DCD DAbt_Handler -vector_resv - DCD Resv_Handler -vector_irq - DCD IRQ_Handler -vector_fiq - DCD FIQ_Handler - -;----------------- Reset Handler ----------------------------------------------- - IMPORT rt_low_level_init - IMPORT __main - EXPORT Reset_Handler -Reset_Handler - ; set the cpu to SVC32 mode - MRS R0,CPSR - BIC R0,R0,#MODEMASK - ORR R0,R0,#MODE_SVC:OR:NOINT - MSR CPSR_cxsf,R0 - - ; Set CO-Processor - ; little-end，disbale I/D Cache MMU, vector table is 0x00000000 - MRC p15, 0, R0, c1, c0, 0 ; Read CP15 - LDR R1, =0x00003085 ; set clear bits - BIC R0, R0, R1 - MCR p15, 0, R0, c1, c0, 0 ; Write CP15 - - ; Call low level init function, - ; disable and clear all IRQs, Init MMU, Init interrupt controller, etc. - LDR SP, =SVC_STACK_START - LDR R0, =rt_low_level_init - BLX R0 - -Setup_Stack - ; Setup Stack for each mode - MRS R0, CPSR - BIC R0, R0, #MODEMASK - - ORR R1, R0, #MODE_UND:OR:NOINT - MSR CPSR_cxsf, R1 ; Undef mode - LDR SP, =UND_STACK_START - - ORR R1,R0,#MODE_ABT:OR:NOINT - MSR CPSR_cxsf,R1 ; Abort mode - LDR SP, =ABT_STACK_START - - ORR R1,R0,#MODE_IRQ:OR:NOINT - MSR CPSR_cxsf,R1 ; IRQ mode - LDR SP, =IRQ_STACK_START - - ORR R1,R0,#MODE_FIQ:OR:NOINT - MSR CPSR_cxsf,R1 ; FIQ mode - LDR SP, =FIQ_STACK_START - - ORR R1,R0,#MODE_SYS:OR:NOINT - MSR CPSR_cxsf,R1 ; SYS/User mode - LDR SP, =SYS_STACK_START - - ORR R1,R0,#MODE_SVC:OR:NOINT - MSR CPSR_cxsf,R1 ; SVC mode - LDR SP, =SVC_STACK_START - - ; Enter the C code - LDR R0, =__main - BLX R0 - -;----------------- Exception Handler ------------------------------------------- - IMPORT rt_hw_trap_udef - IMPORT rt_hw_trap_swi - IMPORT rt_hw_trap_pabt - IMPORT rt_hw_trap_dabt - IMPORT rt_hw_trap_resv - IMPORT rt_hw_trap_irq - IMPORT rt_hw_trap_fiq - - IMPORT rt_interrupt_enter - IMPORT rt_interrupt_leave - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -Undef_Handler PROC - SUB SP, SP, #S_FRAME_SIZE - STMIA SP, {R0 - R12} ; Calling R0-R12 - ADD R8, SP, #S_PC - STMDB R8, {SP, LR} ; Calling SP, LR - STR LR, [R8, #0] ; Save calling PC - MRS R6, SPSR - STR R6, [R8, #4] ; Save CPSR - STR R0, [R8, #8] ; Save SPSR - MOV R0, SP - BL rt_hw_trap_udef - ENDP - -SWI_Handler PROC - BL rt_hw_trap_swi - ENDP - -PAbt_Handler PROC - BL rt_hw_trap_pabt - ENDP - -DAbt_Handler PROC - SUB SP, SP, #S_FRAME_SIZE - STMIA SP, {R0 - R12} ; Calling R0-R12 - ADD R8, SP, #S_PC - STMDB R8, {SP, LR} ; Calling SP, LR - STR LR, [R8, #0] ; Save calling PC - MRS R6, SPSR - STR R6, [R8, #4] ; Save CPSR - STR R0, [R8, #8] ; Save SPSR - MOV R0, SP - BL rt_hw_trap_dabt - ENDP - -Resv_Handler PROC - BL rt_hw_trap_resv - ENDP - -FIQ_Handler PROC - STMFD SP!, {R0-R7,LR} - BL rt_hw_trap_fiq - LDMFD SP!, {R0-R7,LR} - SUBS PC, LR, #4 - ENDP - -IRQ_Handler PROC - STMFD SP!, {R0-R12,LR} - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; If rt_thread_switch_interrupt_flag set, - ; jump to rt_hw_context_switch_interrupt_do and don't return - LDR R0, =rt_thread_switch_interrupt_flag - LDR R1, [R0] - CMP R1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD SP!, {R0-R12,LR} - SUBS PC, LR, #4 - ENDP - -;------ void rt_hw_context_switch_interrupt_do(rt_base_t flag) ----------------- -rt_hw_context_switch_interrupt_do PROC - MOV R1, #0 ; Clear flag - STR R1, [R0] ; Save to flag variable - - LDMFD SP!, {R0-R12,LR} ; Reload saved registers - STMFD SP, {R0-R2} ; Save R0-R2 - SUB R1, SP, #4*3 ; Save old task's SP to R1 - SUB R2, LR, #4 ; Save old task's PC to R2 - - MRS R0, SPSR ; Get CPSR of interrupt thread - - MSR CPSR_c, #MODE_SVC:OR:NOINT ; Switch to SVC mode and no interrupt - - STMFD SP!, {R2} ; Push old task's PC - STMFD SP!, {R3-R12,LR} ; Push old task's LR,R12-R3 - LDMFD R1, {R1-R3} - STMFD SP!, {R1-R3} ; Push old task's R2-R0 - STMFD SP!, {R0} ; Push old task's CPSR - - LDR R4, =rt_interrupt_from_thread - LDR R5, [R4] ; R5 = stack ptr in old tasks's TCB - STR SP, [R5] ; Store SP in preempted tasks's TCB - - LDR R6, =rt_interrupt_to_thread - LDR R6, [R6] ; R6 = stack ptr in new tasks's TCB - LDR SP, [R6] ; Get new task's stack pointer - - LDMFD SP!, {R4} ; Pop new task's SPSR - MSR SPSR_cxsf, R4 - - LDMFD SP!, {R0-R12,LR,PC}^ ; pop new task's R0-R12,LR & PC SPSR to CPSR - ENDP - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem ; heap base - LDR R1, = SVC_STACK_START ; stack base (top-address) - LDR R2, = (Heap_Mem + Heap_Size) ; heap limit - LDR R3, = (SVC_STACK_START - SVC_STK_SIZE) ; stack limit (low-address) - BX LR - - ALIGN - - ENDIF - - END diff --git a/rt-thread/libcpu/arm/arm926/trap.c b/rt-thread/libcpu/arm/arm926/trap.c deleted file mode 100644 index a1458f9..0000000 --- a/rt-thread/libcpu/arm/arm926/trap.c +++ /dev/null @@ -1,210 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety modified from mini2440 - * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP - */ - -#include -#include - -#define INT_IRQ 0x00 -#define INT_FIQ 0x01 - -extern struct rt_thread *rt_current_thread; -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) -extern long list_thread(void); -#endif - -struct rt_hw_register -{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; -}; -static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL; -void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context)) -{ - rt_exception_hook = exception_handle; -} -/** - * this function will show registers of CPU - * - * @param regs the registers point - */ - -void rt_hw_show_register(struct rt_hw_register *regs) -{ - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", - regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", - regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", - regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", - regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", - regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); -} - -/** - * When ARM7TDMI comes across an instruction which it cannot handle, - * it takes the undefined instruction trap. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_udef(struct rt_hw_register *regs) -{ - if (rt_exception_hook != RT_NULL) - { - rt_err_t result; - - result = rt_exception_hook(regs); - if (result == RT_EOK) return; - } - rt_hw_show_register(regs); - - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * The software interrupt instruction (SWI) is used for entering - * Supervisor mode, usually to request a particular supervisor - * function. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_swi(struct rt_hw_register *regs) -{ - if (rt_exception_hook != RT_NULL) - { - rt_err_t result; - - result = rt_exception_hook(regs); - if (result == RT_EOK) return; - } - rt_hw_show_register(regs); - - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during an instruction prefetch. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_pabt(struct rt_hw_register *regs) -{ - if (rt_exception_hook != RT_NULL) - { - rt_err_t result; - - result = rt_exception_hook(regs); - if (result == RT_EOK) return; - } - rt_hw_show_register(regs); - - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); - -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during a data access. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_dabt(struct rt_hw_register *regs) -{ - if (rt_exception_hook != RT_NULL) - { - rt_err_t result; - - result = rt_exception_hook(regs); - if (result == RT_EOK) return; - } - rt_hw_show_register(regs); - - rt_kprintf("data abort\n"); - rt_kprintf("thread - %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); - -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * Normally, system will never reach here - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_resv(struct rt_hw_register *regs) -{ - if (rt_exception_hook != RT_NULL) - { - rt_err_t result; - - result = rt_exception_hook(regs); - if (result == RT_EOK) return; - } - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); -} - -extern void rt_interrupt_dispatch(rt_uint32_t fiq_irq); - -void rt_hw_trap_irq(void) -{ - rt_interrupt_dispatch(INT_IRQ); -} - -void rt_hw_trap_fiq(void) -{ - rt_interrupt_dispatch(INT_FIQ); -} diff --git a/rt-thread/libcpu/arm/armv6/SConscript b/rt-thread/libcpu/arm/armv6/SConscript deleted file mode 100644 index b259a94..0000000 --- a/rt-thread/libcpu/arm/armv6/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/armv6/arm_entry_gcc.S b/rt-thread/libcpu/arm/armv6/arm_entry_gcc.S deleted file mode 100644 index c11c691..0000000 --- a/rt-thread/libcpu/arm/armv6/arm_entry_gcc.S +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2014-11-07 weety first version - */ - -#include - -#include "armv6.h" - -//#define DEBUG - -.macro PRINT, str -#ifdef DEBUG - stmfd sp!, {r0-r3, ip, lr} - add r0, pc, #4 - bl rt_kprintf - b 1f - .asciz "UNDEF: \str\n" - .balign 4 -1: ldmfd sp!, {r0-r3, ip, lr} -#endif - .endm - -.macro PRINT1, str, arg -#ifdef DEBUG - stmfd sp!, {r0-r3, ip, lr} - mov r1, \arg - add r0, pc, #4 - bl rt_kprintf - b 1f - .asciz "UNDEF: \str\n" - .balign 4 -1: ldmfd sp!, {r0-r3, ip, lr} -#endif - .endm - -.macro PRINT3, str, arg1, arg2, arg3 -#ifdef DEBUG - stmfd sp!, {r0-r3, ip, lr} - mov r3, \arg3 - mov r2, \arg2 - mov r1, \arg1 - add r0, pc, #4 - bl rt_kprintf - b 1f - .asciz "UNDEF: \str\n" - .balign 4 -1: ldmfd sp!, {r0-r3, ip, lr} -#endif - .endm - -.macro get_current_thread, rd - ldr \rd, .current_thread - ldr \rd, [\rd] - .endm - -.current_thread: - .word rt_current_thread - -#ifdef RT_USING_NEON - .align 6 - -/* is the neon instuction on arm mode? */ -.neon_opcode: - .word 0xfe000000 @ mask - .word 0xf2000000 @ opcode - - .word 0xff100000 @ mask - .word 0xf4000000 @ opcode - - .word 0x00000000 @ end mask - .word 0x00000000 @ end opcode -#endif - -/* undefined instruction exception processing */ -.globl undef_entry -undef_entry: - PRINT1 "r0=0x%08x", r0 - PRINT1 "r2=0x%08x", r2 - PRINT1 "r9=0x%08x", r9 - PRINT1 "sp=0x%08x", sp - -#ifdef RT_USING_NEON - ldr r6, .neon_opcode -__check_neon_instruction: - ldr r7, [r6], #4 @ load mask value - cmp r7, #0 @ end mask? - beq __check_vfp_instruction - and r8, r0, r7 - ldr r7, [r6], #4 @ load opcode value - cmp r8, r7 @ is NEON instruction? - bne __check_neon_instruction - b vfp_entry -__check_vfp_instruction: -#endif - tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC instruction has bit 27 - tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 instruction - moveq pc, lr @ no vfp coprocessor instruction, return - get_current_thread r10 - and r8, r0, #0x00000f00 @ get coprocessor number - PRINT1 "CP=0x%08x", r8 - add pc, pc, r8, lsr #6 - nop - mov pc, lr @ CP0 - mov pc, lr @ CP1 - mov pc, lr @ CP2 - mov pc, lr @ CP3 - mov pc, lr @ CP4 - mov pc, lr @ CP5 - mov pc, lr @ CP6 - mov pc, lr @ CP7 - mov pc, lr @ CP8 - mov pc, lr @ CP9 - mov pc, lr @ CP10 VFP - mov pc, lr @ CP11 VFP - mov pc, lr @ CP12 - mov pc, lr @ CP13 - mov pc, lr @ CP14 DEBUG - mov pc, lr @ CP15 SYS CONTROL - - diff --git a/rt-thread/libcpu/arm/armv6/armv6.h b/rt-thread/libcpu/arm/armv6/armv6.h deleted file mode 100644 index 522c358..0000000 --- a/rt-thread/libcpu/arm/armv6/armv6.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ - -#ifndef __ARMV6_H__ -#define __ARMV6_H__ - - -/*****************************/ -/* CPU Mode */ -/*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -#ifndef __ASSEMBLY__ -struct rt_hw_register -{ - rt_uint32_t cpsr; - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; -}; -#if(0) -struct rt_hw_register{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; -}; -#endif -#endif - -/* rt_hw_register offset */ -#define S_FRAME_SIZE 68 - -#define S_PC 64 -#define S_LR 60 -#define S_SP 56 -#define S_IP 52 -#define S_FP 48 -#define S_R10 44 -#define S_R9 40 -#define S_R8 36 -#define S_R7 32 -#define S_R6 28 -#define S_R5 24 -#define S_R4 20 -#define S_R3 16 -#define S_R2 12 -#define S_R1 8 -#define S_R0 4 -#define S_CPSR 0 - - -#endif diff --git a/rt-thread/libcpu/arm/armv6/context_gcc.S b/rt-thread/libcpu/arm/armv6/context_gcc.S deleted file mode 100644 index 0446109..0000000 --- a/rt-thread/libcpu/arm/armv6/context_gcc.S +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety copy from mini2440 - */ - -/*! - * \addtogroup ARMv6 - */ -/*@{*/ - -#include - -#define NOINT 0xc0 -#define FPEXC_EN (1 << 30) /* VFP enable bit */ - -/* - * rt_base_t rt_hw_interrupt_disable(); - */ -.globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mrs r0, cpsr - cpsid if - bx lr - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ -.globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - msr cpsr_c, r0 - bx lr - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to - */ -.globl rt_hw_context_switch -rt_hw_context_switch: - stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) - stmfd sp!, {r0-r12, lr} @ push lr & register file - - mrs r4, cpsr - tst lr, #0x01 - orrne r4, r4, #0x20 @ it's thumb code - - stmfd sp!, {r4} @ push cpsr - - str sp, [r0] @ store sp in preempted tasks TCB - ldr sp, [r1] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task cpsr to spsr - msr spsr_cxsf, r4 -_do_switch: - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to - */ -.globl rt_hw_context_switch_to -rt_hw_context_switch_to: - ldr sp, [r0] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - - bic r4, r4, #0x20 @ must be ARM mode - msr cpsr_cxsf, r4 - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - */ -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -.globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - ldr r2, =rt_thread_switch_interrupt_flag - ldr r3, [r2] - cmp r3, #1 - beq _reswitch - mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 - str r3, [r2] - ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread - str r0, [r2] -_reswitch: - ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread - str r1, [r2] - bx lr diff --git a/rt-thread/libcpu/arm/armv6/cpuport.c b/rt-thread/libcpu/arm/armv6/cpuport.c deleted file mode 100644 index 232e7f0..0000000 --- a/rt-thread/libcpu/arm/armv6/cpuport.c +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety modified from mini2440 - */ - -#include -#include - -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) - -extern void machine_reset(void); -extern void machine_shutdown(void); - -#ifdef __GNUC__ -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); -} - - -#endif - -#ifdef __CC_ARM -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - __asm - { - mrc p15, 0, i, c1, c0, 0 - } - - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } -} -#endif - -/** - * enable I-Cache - * - */ -void rt_hw_cpu_icache_enable() -{ - cache_enable(ICACHE_MASK); -} - -/** - * disable I-Cache - * - */ -void rt_hw_cpu_icache_disable() -{ - cache_disable(ICACHE_MASK); -} - -/** - * return the status of I-Cache - * - */ -rt_base_t rt_hw_cpu_icache_status() -{ - return (cp15_rd() & ICACHE_MASK); -} - -/** - * enable D-Cache - * - */ -void rt_hw_cpu_dcache_enable() -{ - cache_enable(DCACHE_MASK); -} - -/** - * disable D-Cache - * - */ -void rt_hw_cpu_dcache_disable() -{ - cache_disable(DCACHE_MASK); -} - -/** - * return the status of D-Cache - * - */ -rt_base_t rt_hw_cpu_dcache_status() -{ - return (cp15_rd() & DCACHE_MASK); -} - -/** - * reset cpu by dog's time-out - * - */ -RT_WEAK void rt_hw_cpu_reset() -{ - - rt_kprintf("Restarting system...\n"); - machine_reset(); - - while(1); /* loop forever and wait for reset to happen */ - - /* NEVER REACHED */ -} - -/** - * shutdown CPU - * - */ -RT_WEAK void rt_hw_cpu_shutdown() -{ - rt_base_t level; - rt_kprintf("shutdown...\n"); - - level = rt_hw_interrupt_disable(); - machine_shutdown(); - while (level) - { - RT_ASSERT(0); - } -} - -#ifdef RT_USING_CPU_FFS -/** - * This function finds the first bit set (beginning with the least significant bit) - * in value and return the index of that bit. - * - * Bits are numbered starting at 1 (the least significant bit). A return value of - * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function - * shall return 0. - */ -#if defined(__CC_ARM) -int __rt_ffs(int value) -{ - register rt_uint32_t x; - - if (value == 0) - return value; - - __asm - { - rsb x, value, #0 - and x, x, value - clz x, x - rsb x, x, #32 - } - - return x; -} -#elif defined(__IAR_SYSTEMS_ICC__) -int __rt_ffs(int value) -{ - if (value == 0) - return value; - - __ASM("RSB r4, r0, #0"); - __ASM("AND r4, r4, r0"); - __ASM("CLZ r4, r4"); - __ASM("RSB r0, r4, #32"); -} -#elif defined(__GNUC__) -int __rt_ffs(int value) -{ - if (value == 0) - return value; - - value &= (-value); - asm ("clz %0, %1": "=r"(value) :"r"(value)); - - return (32 - value); -} -#endif - -#endif - - -/*@}*/ diff --git a/rt-thread/libcpu/arm/armv6/mmu.c b/rt-thread/libcpu/arm/armv6/mmu.c deleted file mode 100644 index deb2f83..0000000 --- a/rt-thread/libcpu/arm/armv6/mmu.c +++ /dev/null @@ -1,548 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ - -#include "mmu.h" - -#ifdef __CC_ARM -void mmu_setttbase(rt_uint32_t i) -{ - register rt_uint32_t value; - - /* Invalidates all TLBs.Domain access is selected as - * client by configuring domain access register, - * in that case access controlled by permission value - * set by page table entry - */ - value = 0; - __asm volatile - { - mcr p15, 0, value, c8, c7, 0 - } - - value = 0x55555555; - __asm volatile - { - mcr p15, 0, value, c3, c0, 0 - mcr p15, 0, i, c2, c0, 0 - } -} - -void mmu_set_domain(rt_uint32_t i) -{ - __asm volatile - { - mcr p15,0, i, c3, c0, 0 - } -} - -void mmu_enable() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_enable_icache() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_enable_dcache() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable_icache() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable_dcache() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_enable_alignfault() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable_alignfault() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_clean_invalidated_cache_index(int index) -{ - __asm volatile - { - mcr p15, 0, index, c7, c14, 2 - } -} - -void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~(CACHE_LINE_SIZE - 1); - - while(ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c14, 1 - } - ptr += CACHE_LINE_SIZE; - } -} - -void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~(CACHE_LINE_SIZE - 1); - - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c10, 1 - } - ptr += CACHE_LINE_SIZE; - } -} - -void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~(CACHE_LINE_SIZE - 1); - - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c6, 1 - } - ptr += CACHE_LINE_SIZE; - } -} - -void mmu_invalidate_tlb() -{ - register rt_uint32_t value; - - value = 0; - __asm volatile - { - mcr p15, 0, value, c8, c7, 0 - } -} - -void mmu_invalidate_icache() -{ - register rt_uint32_t value; - - value = 0; - - __asm volatile - { - mcr p15, 0, value, c7, c5, 0 - } -} - - -void mmu_invalidate_dcache_all() -{ - register rt_uint32_t value; - - value = 0; - - __asm volatile - { - mcr p15, 0, value, c7, c6, 0 - } -} -#elif defined(__GNUC__) -void mmu_setttbase(register rt_uint32_t i) -{ - register rt_uint32_t value; - - /* Invalidates all TLBs.Domain access is selected as - * client by configuring domain access register, - * in that case access controlled by permission value - * set by page table entry - */ - value = 0; - asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); - - value = 0x55555555; - asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); - asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); -} - -void mmu_set_domain(register rt_uint32_t i) -{ - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); -} - -void mmu_enable() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= 0x1; - /* Enables the extended page tables to be configured for - the hardware page translation mechanism, Subpage AP bits disabled */ - i |= (1 << 23); /* support for ARMv6 MMU features */ - i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~0x1; - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_enable_icache() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= (1 << 12); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_enable_dcache() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= (1 << 2); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable_icache() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~(1 << 12); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable_dcache() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~(1 << 2); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_enable_alignfault() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= (1 << 1); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable_alignfault() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~(1 << 1); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_clean_invalidated_cache_index(int index) -{ - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); -} - -void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~(CACHE_LINE_SIZE - 1); - - while(ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } -} - - -void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~(CACHE_LINE_SIZE - 1); - - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } -} - -void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~(CACHE_LINE_SIZE - 1); - - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } -} - -void mmu_invalidate_tlb() -{ - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); -} - -void mmu_invalidate_icache() -{ - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); -} - -void mmu_invalidate_dcache_all() -{ - asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0)); -} -#endif - -/* level1 page table */ -static volatile unsigned int _pgd_table[4*1024] ALIGN(16*1024); -/* - * level2 page table - * RT_MMU_PTE_SIZE must be 1024*n - */ -#define RT_MMU_PTE_SIZE 4096 -static volatile unsigned int _pte_table[RT_MMU_PTE_SIZE] ALIGN(1*1024); - -void mmu_create_pgd(struct mem_desc *mdesc) -{ - volatile rt_uint32_t *pTT; - volatile int i, nSec; - pTT = (rt_uint32_t *)_pgd_table + (mdesc->vaddr_start >> 20); - nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20); - for(i = 0; i <= nSec; i++) - { - *pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20); - pTT++; - } -} - -void mmu_create_pte(struct mem_desc *mdesc) -{ - volatile rt_uint32_t *pTT; - volatile rt_uint32_t *p_pteentry; - int i; - rt_uint32_t vaddr; - rt_uint32_t total_page = 0; - rt_uint32_t pte_offset = 0; - rt_uint32_t sect_attr = 0; - - total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1; - pte_offset = mdesc->sect_attr & 0xfffffc00; - sect_attr = mdesc->sect_attr & 0x3ff; - vaddr = mdesc->vaddr_start; - - for(i = 0; i < total_page; i++) - { - pTT = (rt_uint32_t *)_pgd_table + (vaddr >> 20); - if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */ - { - *pTT = pte_offset | sect_attr; - p_pteentry = (rt_uint32_t *)pte_offset + - ((vaddr & 0x000ff000) >> 12); - pte_offset += 1024; - } - else /* using old Level 1 page table item */ - { - p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + - ((vaddr & 0x000ff000) >> 12); - } - - - *p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12); - vaddr += 0x1000; - } -} - -static void build_pte_mem_desc(struct mem_desc *mdesc, rt_uint32_t size) -{ - rt_uint32_t pte_offset = 0; - rt_uint32_t nsec = 0; - /* set page table */ - for (; size > 0; size--) - { - if (mdesc->mapped_mode == PAGE_MAPPED) - { - nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20; - mdesc->sect_attr |= (((rt_uint32_t)_pte_table)& 0xfffffc00) + pte_offset; - pte_offset += nsec << 10; - } - if (pte_offset >= RT_MMU_PTE_SIZE) - { - rt_kprintf("PTE table size too little\n"); - RT_ASSERT(0); - } - - mdesc++; - } -} - - -void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size) -{ - /* disable I/D cache */ - mmu_disable_dcache(); - mmu_disable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); - - /* clear pgd and pte table */ - rt_memset((void *)_pgd_table, 0, 16*1024); - rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE); - build_pte_mem_desc(mdesc, size); - /* set page table */ - for (; size > 0; size--) - { - if (mdesc->mapped_mode == SECT_MAPPED) - { - mmu_create_pgd(mdesc); - } - else - { - mmu_create_pte(mdesc); - } - - mdesc++; - } - - /* set MMU table address */ - mmu_setttbase((rt_uint32_t)_pgd_table); - - /* enables MMU */ - mmu_enable(); - - /* enable Instruction Cache */ - mmu_enable_icache(); - - /* enable Data Cache */ - mmu_enable_dcache(); - - mmu_invalidate_icache(); - mmu_invalidate_dcache_all(); -} - diff --git a/rt-thread/libcpu/arm/armv6/mmu.h b/rt-thread/libcpu/arm/armv6/mmu.h deleted file mode 100644 index 1835537..0000000 --- a/rt-thread/libcpu/arm/armv6/mmu.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ - -#ifndef __MMU_H__ -#define __MMU_H__ - -#include - -#define CACHE_LINE_SIZE 32 - -/* - * Hardware page table definitions. - * - * + Level 1 descriptor (PGD) - * - common - */ -#define PGD_TYPE_MASK (3 << 0) -#define PGD_TYPE_FAULT (0 << 0) -#define PGD_TYPE_TABLE (1 << 0) -#define PGD_TYPE_SECT (2 << 0) -#define PGD_BIT4 (1 << 4) -#define PGD_DOMAIN(x) ((x) << 5) -#define PGD_PROTECTION (1 << 9) /* ARMv5 */ -/* - * - section - */ -#define PGD_SECT_BUFFERABLE (1 << 2) -#define PGD_SECT_CACHEABLE (1 << 3) -#define PGD_SECT_XN (1 << 4) /* ARMv6 */ -#define PGD_SECT_AP0 (1 << 10) -#define PGD_SECT_AP1 (1 << 11) -#define PGD_SECT_TEX(x) ((x) << 12) /* ARMv5 */ -#define PGD_SECT_APX (1 << 15) /* ARMv6 */ -#define PGD_SECT_S (1 << 16) /* ARMv6 */ -#define PGD_SECT_nG (1 << 17) /* ARMv6 */ -#define PGD_SECT_SUPER (1 << 18) /* ARMv6 */ - -#define PGD_SECT_UNCACHED (0) -#define PGD_SECT_BUFFERED (PGD_SECT_BUFFERABLE) -#define PGD_SECT_WT (PGD_SECT_CACHEABLE) -#define PGD_SECT_WB (PGD_SECT_CACHEABLE | PGD_SECT_BUFFERABLE) -#define PGD_SECT_MINICACHE (PGD_SECT_TEX(1) | PGD_SECT_CACHEABLE) -#define PGD_SECT_WBWA (PGD_SECT_TEX(1) | PGD_SECT_CACHEABLE | PGD_SECT_BUFFERABLE) -#define PGD_SECT_NONSHARED_DEV (PGD_SECT_TEX(2)) - - -/* - * + Level 2 descriptor (PTE) - * - common - */ -#define PTE_TYPE_MASK (3 << 0) -#define PTE_TYPE_FAULT (0 << 0) -#define PTE_TYPE_LARGE (1 << 0) -#define PTE_TYPE_SMALL (2 << 0) -#define PTE_TYPE_EXT (3 << 0) /* ARMv5 */ -#define PTE_BUFFERABLE (1 << 2) -#define PTE_CACHEABLE (1 << 3) - -/* - * - extended small page/tiny page - */ -#define PTE_EXT_XN (1 << 0) /* ARMv6 */ -#define PTE_EXT_AP_MASK (3 << 4) -#define PTE_EXT_AP0 (1 << 4) -#define PTE_EXT_AP1 (2 << 4) -#define PTE_EXT_AP_UNO_SRO (0 << 4) -#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) -#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) -#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) -#define PTE_EXT_TEX(x) ((x) << 6) /* ARMv5 */ -#define PTE_EXT_APX (1 << 9) /* ARMv6 */ -#define PTE_EXT_SHARED (1 << 10) /* ARMv6 */ -#define PTE_EXT_NG (1 << 11) /* ARMv6 */ - -/* - * - small page - */ -#define PTE_SMALL_AP_MASK (0xff << 4) -#define PTE_SMALL_AP_UNO_SRO (0x00 << 4) -#define PTE_SMALL_AP_UNO_SRW (0x55 << 4) -#define PTE_SMALL_AP_URO_SRW (0xaa << 4) -#define PTE_SMALL_AP_URW_SRW (0xff << 4) - - -/* - * sector table properities - */ -#define SECT_CB (PGD_SECT_CACHEABLE|PGD_SECT_BUFFERABLE) //cache_on, write_back -#define SECT_CNB (PGD_SECT_CACHEABLE) //cache_on, write_through -#define SECT_NCB (PGD_SECT_BUFFERABLE) //cache_off,WR_BUF on -#define SECT_NCNB (0 << 2) //cache_off,WR_BUF off - -#define SECT_AP_RW (PGD_SECT_AP0|PGD_SECT_AP1) //supervisor=RW, user=RW -#define SECT_AP_RO (PGD_SECT_AP0|PGD_SECT_AP1|PGD_SECT_APX) //supervisor=RO, user=RO - -#define SECT_RWX_CB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT) /* Read/Write/executable, cache, write back */ -#define SECT_RWX_CNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT) /* Read/Write/executable, cache, write through */ -#define SECT_RWX_NCNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_TYPE_SECT) /* Read/Write/executable without cache and write buffer */ -#define SECT_RWX_FAULT (SECT_AP_RW|PGD_DOMAIN(1)|PGD_TYPE_SECT) /* Read/Write without cache and write buffer */ - -#define SECT_RWNX_CB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write, cache, write back */ -#define SECT_RWNX_CNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write, cache, write through */ -#define SECT_RWNX_NCNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write without cache and write buffer */ -#define SECT_RWNX_FAULT (SECT_AP_RW|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write without cache and write buffer */ - - -#define SECT_ROX_CB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT) /* Read Only/executable, cache, write back */ -#define SECT_ROX_CNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT) /* Read Only/executable, cache, write through */ -#define SECT_ROX_NCNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_TYPE_SECT) /* Read Only/executable without cache and write buffer */ -#define SECT_ROX_FAULT (SECT_AP_RO|PGD_DOMAIN(1)|PGD_TYPE_SECT) /* Read Only without cache and write buffer */ - -#define SECT_RONX_CB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_SECT_XN) /* Read Only, cache, write back */ -#define SECT_RONX_CNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_SECT_XN) /* Read Only, cache, write through */ -#define SECT_RONX_NCNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_SECT_XN) /* Read Only without cache and write buffer */ -#define SECT_RONX_FAULT (SECT_AP_RO|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_SECT_XN) /* Read Only without cache and write buffer */ - -#define SECT_TO_PAGE (PGD_DOMAIN(0)|PGD_TYPE_TABLE) /* Level 2 descriptor (PTE) entry properity */ - -/* - * page table properities - */ -#define PAGE_CB (PTE_BUFFERABLE|PTE_CACHEABLE) //cache_on, write_back -#define PAGE_CNB (PTE_CACHEABLE) //cache_on, write_through -#define PAGE_NCB (PTE_BUFFERABLE) //cache_off,WR_BUF on -#define PAGE_NCNB (0 << 2) //cache_off,WR_BUF off - -#define PAGE_AP_RW (PTE_EXT_AP0|PTE_EXT_AP1) //supervisor=RW, user=RW -#define PAGE_AP_RO (PTE_EXT_AP0|PTE_EXT_AP1|PTE_EXT_APX) //supervisor=RO, user=RO - -#define PAGE_RWX_CB (PAGE_AP_RW|PAGE_CB|PTE_TYPE_SMALL) /* Read/Write/executable, cache, write back */ -#define PAGE_RWX_CNB (PAGE_AP_RW|PAGE_CNB|PTE_TYPE_SMALL) /* Read/Write/executable, cache, write through */ -#define PAGE_RWX_NCNB (PAGE_AP_RW|PTE_TYPE_SMALL) /* Read/Write/executable without cache and write buffer */ -#define PAGE_RWX_FAULT (PAGE_AP_RW|PTE_TYPE_SMALL) /* Read/Write without cache and write buffer */ - -#define PAGE_RWNX_CB (PAGE_AP_RW|PAGE_CB|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read/Write, cache, write back */ -#define PAGE_RWNX_CNB (PAGE_AP_RW|PAGE_CNB|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read/Write, cache, write through */ -#define PAGE_RWNX_NCNB (PAGE_AP_RW|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read/Write without cache and write buffer */ -#define PAGE_RWNX_FAULT (PAGE_AP_RW|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read/Write without cache and write buffer */ - - -#define PAGE_ROX_CB (PAGE_AP_RO|PAGE_CB|PTE_TYPE_SMALL) /* Read Only/executable, cache, write back */ -#define PAGE_ROX_CNB (PAGE_AP_RO|PAGE_CNB|PTE_TYPE_SMALL) /* Read Only/executable, cache, write through */ -#define PAGE_ROX_NCNB (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only/executable without cache and write buffer */ -#define PAGE_ROX_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */ - -#define PAGE_RONX_CB (PAGE_AP_RO|PAGE_CB|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only, cache, write back */ -#define PAGE_RONX_CNB (PAGE_AP_RO|PAGE_CNB|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only, cache, write through */ -#define PAGE_RONX_NCNB (PAGE_AP_RO|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only without cache and write buffer */ -#define PAGE_RONX_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only without cache and write buffer */ - - -#define DESC_SEC (0x2|(1<<4)) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO - -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) - -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) - -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ - -struct mem_desc { - rt_uint32_t vaddr_start; - rt_uint32_t vaddr_end; - rt_uint32_t paddr_start; - rt_uint32_t sect_attr; /* when page mapped */ - rt_uint32_t page_attr; /* only sector mapped valid */ - rt_uint32_t mapped_mode; -#define SECT_MAPPED 0 -#define PAGE_MAPPED 1 -}; - -void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size); - -#endif - diff --git a/rt-thread/libcpu/arm/armv6/stack.c b/rt-thread/libcpu/arm/armv6/stack.c deleted file mode 100644 index 33a8d96..0000000 --- a/rt-thread/libcpu/arm/armv6/stack.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety copy from mini2440 - */ -#include - -/*****************************/ -/* CPU Mode */ -/*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - - stack_addr += sizeof(rt_uint32_t); - stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); - stk = (rt_uint32_t *)stack_addr; - - *(--stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0xdeadbeef; /* r12 */ - *(--stk) = 0xdeadbeef; /* r11 */ - *(--stk) = 0xdeadbeef; /* r10 */ - *(--stk) = 0xdeadbeef; /* r9 */ - *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = 0xdeadbeef; /* r4 */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = 0xdeadbeef; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - diff --git a/rt-thread/libcpu/arm/armv6/vfp.c b/rt-thread/libcpu/arm/armv6/vfp.c deleted file mode 100644 index fc07f5a..0000000 --- a/rt-thread/libcpu/arm/armv6/vfp.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2014-11-07 weety first version - */ - -#include -#include -#include "vfp.h" - -#ifdef RT_USING_VFP - -void vfp_init(void) -{ - int ret = 0; - unsigned int value; - asm volatile ("mrc p15, 0, %0, c1, c0, 2" - :"=r"(value) - :); - value |= 0xf00000;/*enable CP10, CP11 user access*/ - asm volatile("mcr p15, 0, %0, c1, c0, 2" - : - :"r"(value)); - - asm volatile("fmrx %0, fpexc" - :"=r"(value)); - value |=(1<<30); - asm volatile("fmxr fpexc, %0" - : - :"r"(value)); - -} - -#endif diff --git a/rt-thread/libcpu/arm/armv6/vfp.h b/rt-thread/libcpu/arm/armv6/vfp.h deleted file mode 100644 index fd084f3..0000000 --- a/rt-thread/libcpu/arm/armv6/vfp.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2014-11-07 weety first version - */ - -#ifndef __VFP_H__ -#define __VFP_H__ - -/* FPSID register bits */ -#define FPSID_IMPLEMENTER_BIT (24) -#define FPSID_IMPLEMENTER_MASK (0xff << FPSID_IMPLEMENTER_BIT) -#define FPSID_SW (1 << 23) -#define FPSID_FORMAT_BIT (21) -#define FPSID_FORMAT_MASK (0x3 << FPSID_FORMAT_BIT) -#define FPSID_NODOUBLE (1 << 20) -#define FPSID_ARCH_BIT (16) -#define FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) -#define FPSID_PART_BIT (8) -#define FPSID_PART_MASK (0xFF << FPSID_PART_BIT) -#define FPSID_VARIANT_BIT (4) -#define FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) -#define FPSID_REVISION_BIT (0) -#define FPSID_REVISION_MASK (0xF << FPSID_REVISION_BIT) - -/* FPSCR register bits */ -#define FPSCR_DN (1<<25) /* Default NaN mode enable bit */ -#define FPSCR_FZ (1<<24) /* Flush-to-zero mode enable bit */ -#define FPSCR_RN (0<<22) /* Round to nearest (RN) mode */ -#define FPSCR_RP (1<<22) /* Round towards plus infinity (RP) mode */ -#define FPSCR_RM (2<<22) /* Round towards minus infinity (RM) mode */ -#define FPSCR_RZ (3<<22) /* Round towards zero (RZ) mode */ -#define FPSCR_RMODE_BIT (22) -#define FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) -#define FPSCR_STRIDE_BIT (20) -#define FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) -#define FPSCR_LENGTH_BIT (16) -#define FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) -#define FPSCR_IDE (1<<15) /* Input Subnormal exception trap enable bit */ -#define FPSCR_IXE (1<<12) /* Inexact exception trap enable bit */ -#define FPSCR_UFE (1<<11) /* Underflow exception trap enable bit */ -#define FPSCR_OFE (1<<10) /* Overflow exception trap enable bit */ -#define FPSCR_DZE (1<<9) /* Division by Zero exception trap enable bit */ -#define FPSCR_IOE (1<<8) /* Invalid Operation exception trap enable bit */ -#define FPSCR_IDC (1<<7) /* Input Subnormal cumulative exception flag */ -#define FPSCR_IXC (1<<4) /* Inexact cumulative exception flag */ -#define FPSCR_UFC (1<<3) /* Underflow cumulative exception flag */ -#define FPSCR_OFC (1<<2) /* Overflow cumulative exception flag */ -#define FPSCR_DZC (1<<1) /* Division by Zero cumulative exception flag */ -#define FPSCR_IOC (1<<0) /* Invalid Operation cumulative exception flag */ - -/* FPEXC register bits */ -#define FPEXC_EX (1 << 31) /* When EX is set, the VFP coprocessor is in the exceptional state */ -#define FPEXC_EN (1 << 30) /* VFP enable bit */ -#define FPEXC_DEX (1 << 29) /* Defined synchronous instruction exceptional flag */ -#define FPEXC_FP2V (1 << 28) /* FPINST2 instruction valid flag */ -#define FPEXC_LENGTH_BIT (8) -#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT) -#define FPEXC_INV (1 << 7) /* Input exception flag */ -#define FPEXC_UFC (1 << 3) /* Potential underflow flag */ -#define FPEXC_OFC (1 << 2) /* Potential overflow flag */ -#define FPEXC_IOC (1 << 0) /* Potential invalid operation flag */ -#define FPEXC_TRAP_MASK (FPEXC_INV|FPEXC_UFC|FPEXC_OFC|FPEXC_IOC) - - -/* MVFR0 register bits */ -#define MVFR0_A_SIMD_BIT (0) -#define MVFR0_A_SIMD_MASK (0xf << MVFR0_A_SIMD_BIT) - - -/* thread switch micro */ -#define THREAD_INIT 0 -#define THREAD_EXIT 1 - -/* - * get VFP register - */ - -#define vmrs(vfp) ({ \ - rt_uint32_t var; \ - asm("vmrs %0, "#vfp"" : "=r" (var) : : "cc"); \ - var; \ - }) - -#define vmsr(vfp, var) \ - asm("vmsr "#vfp", %0" \ - : : "r" (var) : "cc") - - -#endif - - diff --git a/rt-thread/libcpu/arm/cortex-a/SConscript b/rt-thread/libcpu/arm/cortex-a/SConscript deleted file mode 100644 index 78a5e64..0000000 --- a/rt-thread/libcpu/arm/cortex-a/SConscript +++ /dev/null @@ -1,41 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Split(''' -cache.c -cpu.c -mmu.c -stack.c -''') -CPPPATH = [cwd] - -if GetDepend('RT_USING_GIC_V2'): - src += ['interrupt.c'] - src += ['gic.c'] - src += ['trap.c'] - -if GetDepend('RT_USING_GIC_V3'): - src += ['interrupt.c'] - src += ['gicv3.c'] - src += ['trap.c'] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/cortex-a/armv7.h b/rt-thread/libcpu/arm/cortex-a/armv7.h deleted file mode 100644 index 325d0ed..0000000 --- a/rt-thread/libcpu/arm/cortex-a/armv7.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ -#ifndef __ARMV7_H__ -#define __ARMV7_H__ - -/* the exception stack without VFP registers */ -struct rt_hw_exp_stack -{ - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; -}; - -struct rt_hw_stack -{ - unsigned long cpsr; - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long lr; - unsigned long pc; -}; - -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define MONITORMODE 0x16 -#define ABORTMODE 0x17 -#define HYPMODE 0x1b -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -#define T_Bit (1<<5) -#define F_Bit (1<<6) -#define I_Bit (1<<7) -#define A_Bit (1<<8) -#define E_Bit (1<<9) -#define J_Bit (1<<24) - -#define PABT_EXCEPTION 0x1 -#define DABT_EXCEPTION 0x2 -#define UND_EXCEPTION 0x3 -#define SWI_EXCEPTION 0x4 -#define RESV_EXCEPTION 0xF - -#endif diff --git a/rt-thread/libcpu/arm/cortex-a/cache.c b/rt-thread/libcpu/arm/cortex-a/cache.c deleted file mode 100644 index a6b5918..0000000 --- a/rt-thread/libcpu/arm/cortex-a/cache.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-29 quanzhao the first version - */ -#include -#include - -rt_inline rt_uint32_t rt_cpu_icache_line_size(void) -{ - rt_uint32_t ctr; - asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r"(ctr)); - return 4 << (ctr & 0xF); -} - -rt_inline rt_uint32_t rt_cpu_dcache_line_size(void) -{ - rt_uint32_t ctr; - asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r"(ctr)); - return 4 << ((ctr >> 16) & 0xF); -} - -void rt_hw_cpu_icache_invalidate(void *addr, int size) -{ - rt_uint32_t line_size = rt_cpu_icache_line_size(); - rt_uint32_t start_addr = (rt_uint32_t)addr; - rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; - - asm volatile ("dmb":::"memory"); - start_addr &= ~(line_size-1); - end_addr &= ~(line_size-1); - while (start_addr < end_addr) - { - asm volatile ("mcr p15, 0, %0, c7, c5, 1" :: "r"(start_addr)); /* icimvau */ - start_addr += line_size; - } - asm volatile ("dsb\n\tisb":::"memory"); -} - -void rt_hw_cpu_dcache_invalidate(void *addr, int size) -{ - rt_uint32_t line_size = rt_cpu_dcache_line_size(); - rt_uint32_t start_addr = (rt_uint32_t)addr; - rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; - - asm volatile ("dmb":::"memory"); - start_addr &= ~(line_size-1); - end_addr &= ~(line_size-1); - while (start_addr < end_addr) - { - asm volatile ("mcr p15, 0, %0, c7, c6, 1" :: "r"(start_addr)); /* dcimvac */ - start_addr += line_size; - } - asm volatile ("dsb":::"memory"); -} - -void rt_hw_cpu_dcache_inv_range(void *addr, int size) -{ - rt_uint32_t line_size = rt_cpu_dcache_line_size(); - rt_uint32_t start_addr = (rt_uint32_t)addr; - rt_uint32_t end_addr = (rt_uint32_t)addr + size; - - asm volatile ("dmb":::"memory"); - - if ((start_addr & (line_size - 1)) != 0) - { - start_addr &= ~(line_size - 1); - asm volatile ("mcr p15, 0, %0, c7, c14, 1" :: "r"(start_addr)); - start_addr += line_size; - asm volatile ("dsb":::"memory"); - } - - if ((end_addr & (line_size - 1)) != 0) - { - end_addr &= ~(line_size - 1); - asm volatile ("mcr p15, 0, %0, c7, c14, 1" :: "r"(end_addr)); - asm volatile ("dsb":::"memory"); - } - - while (start_addr < end_addr) - { - asm volatile ("mcr p15, 0, %0, c7, c6, 1" :: "r"(start_addr)); /* dcimvac */ - start_addr += line_size; - } - asm volatile ("dsb":::"memory"); -} - -void rt_hw_cpu_dcache_clean(void *addr, int size) -{ - rt_uint32_t line_size = rt_cpu_dcache_line_size(); - rt_uint32_t start_addr = (rt_uint32_t)addr; - rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; - - asm volatile ("dmb":::"memory"); - start_addr &= ~(line_size-1); - end_addr &= ~(line_size-1); - while (start_addr < end_addr) - { - asm volatile ("mcr p15, 0, %0, c7, c10, 1" :: "r"(start_addr)); /* dccmvac */ - start_addr += line_size; - } - asm volatile ("dsb":::"memory"); -} - -void rt_hw_cpu_dcache_clean_inv(void *addr, int size) -{ - rt_uint32_t line_size = rt_cpu_dcache_line_size(); - rt_uint32_t start_addr = (rt_uint32_t)addr; - rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; - - asm volatile ("dmb":::"memory"); - start_addr &= ~(line_size-1); - end_addr &= ~(line_size-1); - while (start_addr < end_addr) - { - asm volatile ("mcr p15, 0, %0, c7, c14, 1" :: "r"(start_addr)); - start_addr += line_size; - } - asm volatile ("dsb":::"memory"); -} - -void rt_hw_cpu_icache_ops(int ops, void *addr, int size) -{ - if (ops == RT_HW_CACHE_INVALIDATE) - rt_hw_cpu_icache_invalidate(addr, size); -} - -void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) -{ - if (ops == RT_HW_CACHE_FLUSH) - rt_hw_cpu_dcache_clean(addr, size); - else if (ops == RT_HW_CACHE_INVALIDATE) - rt_hw_cpu_dcache_invalidate(addr, size); -} - -rt_base_t rt_hw_cpu_icache_status(void) -{ - return 0; -} - -rt_base_t rt_hw_cpu_dcache_status(void) -{ - return 0; -} diff --git a/rt-thread/libcpu/arm/cortex-a/context_gcc.S b/rt-thread/libcpu/arm/cortex-a/context_gcc.S deleted file mode 100644 index 768c513..0000000 --- a/rt-thread/libcpu/arm/cortex-a/context_gcc.S +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - */ - -#include "rtconfig.h" -.section .text, "ax" - -#ifdef RT_USING_SMP -#define rt_hw_interrupt_disable rt_hw_local_irq_disable -#define rt_hw_interrupt_enable rt_hw_local_irq_enable -#endif - -/* - * rt_base_t rt_hw_interrupt_disable(); - */ -.globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mrs r0, cpsr - cpsid i - bx lr - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ -.globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - msr cpsr, r0 - bx lr - -/* - * void rt_hw_context_switch_to(rt_uint32 to, struct rt_thread *to_thread); - * r0 --> to (thread stack) - * r1 --> to_thread - */ -.globl rt_hw_context_switch_to -rt_hw_context_switch_to: - ldr sp, [r0] @ get new task stack pointer - -#ifdef RT_USING_SMP - mov r0, r1 - bl rt_cpus_lock_status_restore -#endif /*RT_USING_SMP*/ - b rt_hw_context_switch_exit - -.section .bss.share.isr -_guest_switch_lvl: - .word 0 - -.globl vmm_virq_update - -.section .text.isr, "ax" -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to, struct rt_thread *to_thread); - * r0 --> from (from_thread stack) - * r1 --> to (to_thread stack) - * r2 --> to_thread - */ -.globl rt_hw_context_switch -rt_hw_context_switch: - stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) - stmfd sp!, {r0-r12, lr} @ push lr & register file - - mrs r4, cpsr - tst lr, #0x01 - orrne r4, r4, #0x20 @ it's thumb code - - stmfd sp!, {r4} @ push cpsr - -#ifdef RT_USING_LWP - stmfd sp, {r13, r14}^ @ push usr_sp usr_lr - sub sp, #8 -#endif -#ifdef RT_USING_FPU - /* fpu context */ - vmrs r6, fpexc - tst r6, #(1<<30) - beq 1f - vstmdb sp!, {d0-d15} - vstmdb sp!, {d16-d31} - vmrs r5, fpscr - stmfd sp!, {r5} -1: - stmfd sp!, {r6} -#endif - - str sp, [r0] @ store sp in preempted tasks TCB - ldr sp, [r1] @ get new task stack pointer - -#ifdef RT_USING_SMP - mov r0, r2 - bl rt_cpus_lock_status_restore -#endif /*RT_USING_SMP*/ - b rt_hw_context_switch_exit - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - */ -.equ Mode_USR, 0x10 -.equ Mode_FIQ, 0x11 -.equ Mode_IRQ, 0x12 -.equ Mode_SVC, 0x13 -.equ Mode_ABT, 0x17 -.equ Mode_UND, 0x1B -.equ Mode_SYS, 0x1F - -.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled -.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled - -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -.globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: -#ifdef RT_USING_SMP - /* r0 :svc_mod context - * r1 :addr of from_thread's sp - * r2 :addr of to_thread's sp - * r3 :to_thread's tcb - */ - - str r0, [r1] - - ldr sp, [r2] - mov r0, r3 - bl rt_cpus_lock_status_restore - - b rt_hw_context_switch_exit - -#else /*RT_USING_SMP*/ - ldr r2, =rt_thread_switch_interrupt_flag - ldr r3, [r2] - cmp r3, #1 - beq _reswitch - ldr ip, =rt_interrupt_from_thread @ set rt_interrupt_from_thread - mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 - str r0, [ip] - str r3, [r2] -_reswitch: - ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread - str r1, [r2] - bx lr -#endif /*RT_USING_SMP*/ - -.global rt_hw_context_switch_exit -rt_hw_context_switch_exit: - -#ifdef RT_USING_SMP -#ifdef RT_USING_SIGNALS - mov r0, sp - cps #Mode_IRQ - bl rt_signal_check - cps #Mode_SVC - mov sp, r0 -#endif -#endif -#ifdef RT_USING_FPU -/* fpu context */ - ldmfd sp!, {r6} - vmsr fpexc, r6 - tst r6, #(1<<30) - beq 1f - ldmfd sp!, {r5} - vmsr fpscr, r5 - vldmia sp!, {d16-d31} - vldmia sp!, {d0-d15} -1: -#endif - -#ifdef RT_USING_LWP - ldmfd sp, {r13, r14}^ /* usr_sp, usr_lr */ - add sp, #8 -#endif - ldmfd sp!, {r1} - msr spsr_cxsf, r1 /* original mode */ - ldmfd sp!, {r0-r12,lr,pc}^ /* irq return */ - diff --git a/rt-thread/libcpu/arm/cortex-a/cp15.h b/rt-thread/libcpu/arm/cortex-a/cp15.h deleted file mode 100644 index 2bf91ac..0000000 --- a/rt-thread/libcpu/arm/cortex-a/cp15.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-03-25 quanzhao the first version - */ -#ifndef __CP15_H__ -#define __CP15_H__ - -#define __get_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) -#define __set_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) -#define __get_cp64(cp, op1, Rt, CRm) __asm__ volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) -#define __set_cp64(cp, op1, Rt, CRm) __asm__ volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) - -int rt_hw_cpu_id(void); -void rt_cpu_mmu_disable(void); -void rt_cpu_mmu_enable(void); -void rt_cpu_tlb_set(volatile unsigned long*); - -void rt_cpu_dcache_clean_flush(void); -void rt_cpu_icache_flush(void); - -void rt_cpu_vector_set_base(unsigned int addr); - -#endif diff --git a/rt-thread/libcpu/arm/cortex-a/cp15_gcc.S b/rt-thread/libcpu/arm/cortex-a/cp15_gcc.S deleted file mode 100644 index 983ae52..0000000 --- a/rt-thread/libcpu/arm/cortex-a/cp15_gcc.S +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - */ - -.weak rt_hw_cpu_id -rt_hw_cpu_id: - mrc p15, #0, r0, c0, c0, #5 @ read multiprocessor affinity register - ldr r1, =0xFFFF03 @ Affinity mask off, leaving CPU ID field, [0:1]CPU ID, [8:15]Cluster ID Aff1, [16:23]Cluster ID Aff2 - and r0, r0, r1 - bx lr - -.globl rt_cpu_vector_set_base -rt_cpu_vector_set_base: - /* clear SCTRL.V to customize the vector address */ - mrc p15, #0, r1, c1, c0, #0 - bic r1, #(1 << 13) - mcr p15, #0, r1, c1, c0, #0 - /* set up the vector address */ - mcr p15, #0, r0, c12, c0, #0 - dsb - bx lr - -.globl rt_hw_cpu_dcache_enable -rt_hw_cpu_dcache_enable: - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x00000004 - mcr p15, #0, r0, c1, c0, #0 - bx lr - -.globl rt_hw_cpu_icache_enable -rt_hw_cpu_icache_enable: - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x00001000 - mcr p15, #0, r0, c1, c0, #0 - bx lr - -_FLD_MAX_WAY: - .word 0x3ff -_FLD_MAX_IDX: - .word 0x7fff - -.globl rt_cpu_dcache_clean_flush -rt_cpu_dcache_clean_flush: - push {r4-r11} - dmb - mrc p15, #1, r0, c0, c0, #1 @ read clid register - ands r3, r0, #0x7000000 @ get level of coherency - mov r3, r3, lsr #23 - beq finished - mov r10, #0 -loop1: - add r2, r10, r10, lsr #1 - mov r1, r0, lsr r2 - and r1, r1, #7 - cmp r1, #2 - blt skip - mcr p15, #2, r10, c0, c0, #0 - isb - mrc p15, #1, r1, c0, c0, #0 - and r2, r1, #7 - add r2, r2, #4 - ldr r4, _FLD_MAX_WAY - ands r4, r4, r1, lsr #3 - clz r5, r4 - ldr r7, _FLD_MAX_IDX - ands r7, r7, r1, lsr #13 -loop2: - mov r9, r4 -loop3: - orr r11, r10, r9, lsl r5 - orr r11, r11, r7, lsl r2 - mcr p15, #0, r11, c7, c14, #2 - subs r9, r9, #1 - bge loop3 - subs r7, r7, #1 - bge loop2 -skip: - add r10, r10, #2 - cmp r3, r10 - bgt loop1 - -finished: - dsb - isb - pop {r4-r11} - bx lr - -.globl rt_cpu_icache_flush -rt_cpu_icache_flush: - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate - dsb - isb - bx lr - -.globl rt_hw_cpu_dcache_disable -rt_hw_cpu_dcache_disable: - push {r4-r11, lr} - bl rt_cpu_dcache_clean_flush - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #0x00000004 - mcr p15, #0, r0, c1, c0, #0 - pop {r4-r11, lr} - bx lr - -.globl rt_hw_cpu_icache_disable -rt_hw_cpu_icache_disable: - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #0x00001000 - mcr p15, #0, r0, c1, c0, #0 - bx lr - -.globl rt_cpu_mmu_disable -rt_cpu_mmu_disable: - mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #1 - mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit - dsb - bx lr - -.globl rt_cpu_mmu_enable -rt_cpu_mmu_enable: - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x001 - mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit - dsb - bx lr - -.globl rt_cpu_tlb_set -rt_cpu_tlb_set: - mcr p15, #0, r0, c2, c0, #0 - dmb - bx lr diff --git a/rt-thread/libcpu/arm/cortex-a/cpu.c b/rt-thread/libcpu/arm/cortex-a/cpu.c deleted file mode 100644 index 7d1a389..0000000 --- a/rt-thread/libcpu/arm/cortex-a/cpu.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-09-15 Bernard first version - * 2018-11-22 Jesven add rt_hw_cpu_id() - */ - -#include -#include -#include - -#ifdef RT_USING_SMP - -void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock) -{ - lock->slock = 0; -} - -void rt_hw_spin_lock(rt_hw_spinlock_t *lock) -{ - unsigned long tmp; - unsigned long newval; - rt_hw_spinlock_t lockval; - - __asm__ __volatile__( - "pld [%0]" - ::"r"(&lock->slock) - ); - - __asm__ __volatile__( - "1: ldrex %0, [%3]\n" - " add %1, %0, %4\n" - " strex %2, %1, [%3]\n" - " teq %2, #0\n" - " bne 1b" - : "=&r" (lockval), "=&r" (newval), "=&r" (tmp) - : "r" (&lock->slock), "I" (1 << 16) - : "cc"); - - while (lockval.tickets.next != lockval.tickets.owner) { - __asm__ __volatile__("wfe":::"memory"); - lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner); - } - - __asm__ volatile ("dmb":::"memory"); -} - -void rt_hw_spin_unlock(rt_hw_spinlock_t *lock) -{ - __asm__ volatile ("dmb":::"memory"); - lock->tickets.owner++; - __asm__ volatile ("dsb ishst\nsev":::"memory"); -} -#endif /*RT_USING_SMP*/ - -/** - * @addtogroup ARM CPU - */ -/*@{*/ - -/** shutdown CPU */ -RT_WEAK void rt_hw_cpu_shutdown() -{ - rt_base_t level; - rt_kprintf("shutdown...\n"); - - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } -} - -#ifdef RT_USING_CPU_FFS -/** - * This function finds the first bit set (beginning with the least significant bit) - * in value and return the index of that bit. - * - * Bits are numbered starting at 1 (the least significant bit). A return value of - * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function - * shall return 0. - */ -int __rt_ffs(int value) -{ - return __builtin_ffs(value); -} -#endif - -/*@}*/ diff --git a/rt-thread/libcpu/arm/cortex-a/gic.c b/rt-thread/libcpu/arm/cortex-a/gic.c deleted file mode 100644 index 5dda225..0000000 --- a/rt-thread/libcpu/arm/cortex-a/gic.c +++ /dev/null @@ -1,495 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - * 2014-04-03 Grissiom many enhancements - * 2018-11-22 Jesven add rt_hw_ipi_send() - * add rt_hw_ipi_handler_install() - */ - -#include -#include - -#include "gic.h" -#include "cp15.h" - -struct arm_gic -{ - rt_uint32_t offset; /* the first interrupt index in the vector table */ - - rt_uint32_t dist_hw_base; /* the base address of the gic distributor */ - rt_uint32_t cpu_hw_base; /* the base addrees of the gic cpu interface */ -}; - -/* 'ARM_GIC_MAX_NR' is the number of cores */ -static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; - -/** Macro to access the Generic Interrupt Controller Interface (GICC) -*/ -#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) -#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) -#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) -#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) -#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) -#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) -#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) -#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) - -/** Macro to access the Generic Interrupt Controller Distributor (GICD) -*/ -#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) -#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) -#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) -#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U) -#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) -#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U) -#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U) -#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U) -#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U) -#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U) -#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U) -#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) -#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) -#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U) -#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) - -static unsigned int _gic_max_irq; - -int arm_gic_get_active_irq(rt_uint32_t index) -{ - int irq; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base); - irq += _gic_table[index].offset; - return irq; -} - -void arm_gic_ack(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1U << (irq % 32U); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; - GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; -} - -void arm_gic_mask(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1U << (irq % 32U); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; -} - -void arm_gic_umask(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1U << (irq % 32U); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; -} - -rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq) -{ - rt_uint32_t pend; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - if (irq >= 16U) - { - pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; - } - else - { - /* INTID 0-15 Software Generated Interrupt */ - pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; - /* No CPU identification offered */ - if (pend != 0U) - { - pend = 1U; - } - else - { - pend = 0U; - } - } - - return (pend); -} - -void arm_gic_set_pending_irq(rt_uint32_t index, int irq) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - if (irq >= 16U) - { - GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); - } - else - { - /* INTID 0-15 Software Generated Interrupt */ - /* Forward the interrupt to the CPU interface that requested it */ - GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); - } -} - -void arm_gic_clear_pending_irq(rt_uint32_t index, int irq) -{ - rt_uint32_t mask; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - if (irq >= 16U) - { - mask = 1U << (irq % 32U); - GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; - } - else - { - mask = 1U << ((irq % 4U) * 8U); - GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -void arm_gic_set_configuration(rt_uint32_t index, int irq, rt_uint32_t config) -{ - rt_uint32_t icfgr; - rt_uint32_t shift; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); - shift = (irq % 16U) << 1U; - - icfgr &= (~(3U << shift)); - icfgr |= (config << shift); - - GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; -} - -rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); -} - -void arm_gic_clear_active(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1U << (irq % 32U); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; -} - -/* Set up the cpu mask for the specific interrupt */ -void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) -{ - rt_uint32_t old_tgt; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); - - old_tgt &= ~(0x0FFUL << ((irq % 4U)*8U)); - old_tgt |= cpumask << ((irq % 4U)*8U); - - GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; -} - -rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; -} - -void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority) -{ - rt_uint32_t mask; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); - mask &= ~(0xFFUL << ((irq % 4U) * 8U)); - mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); - GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; -} - -rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; -} - -void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - /* set priority mask */ - GIC_CPU_PRIMASK(_gic_table[index].cpu_hw_base) = priority & 0xFFUL; -} - -rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - return GIC_CPU_PRIMASK(_gic_table[index].cpu_hw_base); -} - -void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point) -{ - GIC_CPU_BINPOINT(_gic_table[index].cpu_hw_base) = binary_point & 0x7U; -} - -rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index) -{ - return GIC_CPU_BINPOINT(_gic_table[index].cpu_hw_base); -} - -rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq) -{ - rt_uint32_t pending; - rt_uint32_t active; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; - pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; - - return ((active << 1U) | pending); -} - -void arm_gic_send_sgi(rt_uint32_t index, int irq, rt_uint32_t target_list, rt_uint32_t filter_list) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = ((filter_list & 0x3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (irq & 0x0FUL); -} - -rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - return GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); -} - -rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); -} - -void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group) -{ - rt_uint32_t igroupr; - rt_uint32_t shift; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - RT_ASSERT(group <= 1U); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); - shift = (irq % 32U); - igroupr &= (~(1U << shift)); - igroupr |= ( (group & 0x1U) << shift); - - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; -} - -rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; -} - -int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) -{ - unsigned int gic_type, i; - rt_uint32_t cpumask = 1U << 0U; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - _gic_table[index].dist_hw_base = dist_base; - _gic_table[index].offset = irq_start; - - /* Find out how many interrupts are supported. */ - gic_type = GIC_DIST_TYPE(dist_base); - _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U; - - /* - * The GIC only supports up to 1020 interrupt sources. - * Limit this to either the architected maximum, or the - * platform maximum. - */ - if (_gic_max_irq > 1020U) - _gic_max_irq = 1020U; - if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ - _gic_max_irq = ARM_GIC_NR_IRQS; - - cpumask |= cpumask << 8U; - cpumask |= cpumask << 16U; - cpumask |= cpumask << 24U; - - GIC_DIST_CTRL(dist_base) = 0x0U; - - /* Set all global interrupts to be level triggered, active low. */ - for (i = 32U; i < _gic_max_irq; i += 16U) - GIC_DIST_CONFIG(dist_base, i) = 0x0U; - - /* Set all global interrupts to this CPU only. */ - for (i = 32U; i < _gic_max_irq; i += 4U) - GIC_DIST_TARGET(dist_base, i) = cpumask; - - /* Set priority on all interrupts. */ - for (i = 0U; i < _gic_max_irq; i += 4U) - GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U; - - /* Disable all interrupts. */ - for (i = 0U; i < _gic_max_irq; i += 32U) - GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; - -#if 0 - /* All interrupts defaults to IGROUP1(IRQ). */ - for (i = 0; i < _gic_max_irq; i += 32) - GIC_DIST_IGROUP(dist_base, i) = 0xffffffff; -#endif - for (i = 0U; i < _gic_max_irq; i += 32U) - GIC_DIST_IGROUP(dist_base, i) = 0U; - - /* Enable group0 and group1 interrupt forwarding. */ - GIC_DIST_CTRL(dist_base) = 0x01U; - - return 0; -} - -int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - _gic_table[index].cpu_hw_base = cpu_base; - - GIC_CPU_PRIMASK(cpu_base) = 0xf0U; - GIC_CPU_BINPOINT(cpu_base) = 0x7U; - /* Enable CPU interrupt */ - GIC_CPU_CTRL(cpu_base) = 0x01U; - - return 0; -} - -void arm_gic_dump_type(rt_uint32_t index) -{ - unsigned int gic_type; - - gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); - rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", - (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, - _gic_table[index].dist_hw_base, - _gic_max_irq, - gic_type & (1U << 10U) ? "has" : "no", - gic_type); -} - -void arm_gic_dump(rt_uint32_t index) -{ - unsigned int i, k; - - k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); - rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); - rt_kprintf("--- hw mask ---\n"); - for (i = 0U; i < _gic_max_irq / 32U; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, - i * 32U)); - } - rt_kprintf("\n--- hw pending ---\n"); - for (i = 0U; i < _gic_max_irq / 32U; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, - i * 32U)); - } - rt_kprintf("\n--- hw active ---\n"); - for (i = 0U; i < _gic_max_irq / 32U; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, - i * 32U)); - } - rt_kprintf("\n"); -} - -long gic_dump(void) -{ - arm_gic_dump_type(0); - arm_gic_dump(0); - - return 0; -} -MSH_CMD_EXPORT(gic_dump, show gic status); - diff --git a/rt-thread/libcpu/arm/cortex-a/gic.h b/rt-thread/libcpu/arm/cortex-a/gic.h deleted file mode 100644 index 0171122..0000000 --- a/rt-thread/libcpu/arm/cortex-a/gic.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#ifndef __GIC_H__ -#define __GIC_H__ - -#include -#include - -int arm_gic_get_active_irq(rt_uint32_t index); -void arm_gic_ack(rt_uint32_t index, int irq); - -void arm_gic_mask(rt_uint32_t index, int irq); -void arm_gic_umask(rt_uint32_t index, int irq); - -rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq); -void arm_gic_set_pending_irq(rt_uint32_t index, int irq); -void arm_gic_clear_pending_irq(rt_uint32_t index, int irq); - -void arm_gic_set_configuration(rt_uint32_t index, int irq, rt_uint32_t config); -rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq); - -void arm_gic_clear_active(rt_uint32_t index, int irq); - -void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); -rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq); - -void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority); -rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq); - -void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority); -rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index); - -void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point); -rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index); - -rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq); - -void arm_gic_send_sgi(rt_uint32_t index, int irq, rt_uint32_t target_list, rt_uint32_t filter_list); - -rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index); - -rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index); - -void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group); -rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq); - -int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); -int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); - -void arm_gic_dump_type(rt_uint32_t index); -void arm_gic_dump(rt_uint32_t index); - -#endif - diff --git a/rt-thread/libcpu/arm/cortex-a/gicv3.c b/rt-thread/libcpu/arm/cortex-a/gicv3.c deleted file mode 100644 index ce9833a..0000000 --- a/rt-thread/libcpu/arm/cortex-a/gicv3.c +++ /dev/null @@ -1,708 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - * 2014-04-03 Grissiom many enhancements - * 2018-11-22 Jesven add rt_hw_ipi_send() - * add rt_hw_ipi_handler_install() - */ - -#include -#include - -#include "gicv3.h" -#include "cp15.h" - -#ifndef RT_CPUS_NR -#define RT_CPUS_NR 1 -#endif - -struct arm_gic_v3 -{ - rt_uint32_t offset; /* the first interrupt index in the vector table */ - rt_uint32_t redist_hw_base[RT_CPUS_NR]; /* the pointer of the gic redistributor */ - rt_uint32_t dist_hw_base; /* the base address of the gic distributor */ - rt_uint32_t cpu_hw_base[RT_CPUS_NR]; /* the base addrees of the gic cpu interface */ -}; - -/* 'ARM_GIC_MAX_NR' is the number of cores */ -static struct arm_gic_v3 _gic_table[ARM_GIC_MAX_NR]; -static unsigned int _gic_max_irq; - -/** - * @name: arm_gic_cpumask_to_affval - * @msg: - * @in param cpu_mask: - * @out param cluster_id: aff1 [0:7],aff2 [8:15],aff3 [16:23] - * @out param target_list: Target List. The set of PEs for which SGI interrupts will be generated. Each bit corresponds to the - * PE within a cluster with an Affinity 0 value equal to the bit number. - * @return {rt_uint32_t} 0 is finish , 1 is data valid - */ -RT_WEAK rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluster_id, rt_uint32_t *target_list) -{ - return 0; -} - -RT_WEAK rt_uint64_t get_main_cpu_affval(void) -{ - return 0; -} - -int arm_gic_get_active_irq(rt_uint32_t index) -{ - int irq; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - __get_gicv3_reg(ICC_IAR1, irq); - - irq = (irq & 0x1FFFFFF) + _gic_table[index].offset; - return irq; -} - -void arm_gic_ack(rt_uint32_t index, int irq) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - RT_ASSERT(irq >= 0U); - - __asm__ volatile("dsb 0xF" :: - : "memory"); - __set_gicv3_reg(ICC_EOIR1, irq); -} - -void arm_gic_mask(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1U << (irq % 32U); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - if (irq < 32U) - { - rt_int32_t cpu_id = rt_hw_cpu_id(); - RT_ASSERT((cpu_id) < RT_CPUS_NR); - GIC_RDISTSGI_ICENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; - } - else - { - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -void arm_gic_umask(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1U << (irq % 32U); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - if (irq < 32U) - { - rt_int32_t cpu_id = rt_hw_cpu_id(); - RT_ASSERT((cpu_id) < RT_CPUS_NR); - GIC_RDISTSGI_ISENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; - } - else - { - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq) -{ - rt_uint32_t pend; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - if (irq >= 16U) - { - pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; - } - else - { - /* INTID 0-15 Software Generated Interrupt */ - pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; - /* No CPU identification offered */ - if (pend != 0U) - { - pend = 1U; - } - else - { - pend = 0U; - } - } - - return (pend); -} - -void arm_gic_set_pending_irq(rt_uint32_t index, int irq) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - if (irq >= 16U) - { - GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); - } - else - { - /* INTID 0-15 Software Generated Interrupt */ - /* Forward the interrupt to the CPU interface that requested it */ - GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); - } -} - -void arm_gic_clear_pending_irq(rt_uint32_t index, int irq) -{ - rt_uint32_t mask; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - if (irq >= 16U) - { - mask = 1U << (irq % 32U); - GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; - } - else - { - mask = 1U << ((irq % 4U) * 8U); - GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -void arm_gic_set_configuration(rt_uint32_t index, int irq, rt_uint32_t config) -{ - rt_uint32_t icfgr; - rt_uint32_t shift; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); - shift = (irq % 16U) << 1U; - - icfgr &= (~(3U << shift)); - icfgr |= (config << shift); - - GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; -} - -rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); -} - -void arm_gic_clear_active(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1U << (irq % 32U); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; -} - -/* Set up the cpu mask for the specific interrupt */ -void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) -{ - rt_uint32_t old_tgt; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); - - old_tgt &= ~(0x0FFUL << ((irq % 4U) * 8U)); - old_tgt |= cpumask << ((irq % 4U) * 8U); - - GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; -} - -rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; -} - -void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority) -{ - rt_uint32_t mask; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - if (irq < 32U) - { - rt_int32_t cpu_id = rt_hw_cpu_id(); - RT_ASSERT((cpu_id) < RT_CPUS_NR); - - mask = GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq); - mask &= ~(0xFFUL << ((irq % 4U) * 8U)); - mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); - GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) = mask; - } - else - { - mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); - mask &= ~(0xFFUL << ((irq % 4U) * 8U)); - mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); - GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - if (irq < 32U) - { - rt_int32_t cpu_id = rt_hw_cpu_id(); - - RT_ASSERT((cpu_id) < RT_CPUS_NR); - return (GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) >> ((irq % 4U) * 8U)) & 0xFFUL; - } - else - { - return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; - } -} - -void arm_gic_set_system_register_enable_mask(rt_uint32_t index, rt_uint32_t value) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - value &= 0xFFUL; - /* set priority mask */ - __set_gicv3_reg(ICC_SRE, value); - __asm__ volatile ("isb 0xF":: - :"memory"); -} - -rt_uint32_t arm_gic_get_system_register_enable_mask(rt_uint32_t index) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - rt_uint32_t value; - - __get_gicv3_reg(ICC_SRE, value); - return value; -} - -void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - priority &= 0xFFUL; - /* set priority mask */ - __set_gicv3_reg(ICC_PMR, priority); -} - -rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - rt_uint32_t priority; - - __get_gicv3_reg(ICC_PMR, priority); - return priority; -} - -void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point) -{ - index = index; - binary_point &= 0x7U; - - __set_gicv3_reg(ICC_BPR1, binary_point); -} - -rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index) -{ - rt_uint32_t binary_point; - - index = index; - __get_gicv3_reg(ICC_BPR1, binary_point); - return binary_point; -} - -rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq) -{ - rt_uint32_t pending; - rt_uint32_t active; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; - pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; - - return ((active << 1U) | pending); -} - -void arm_gic_send_affinity_sgi(rt_uint32_t index, int irq, rt_uint32_t cpu_mask, rt_uint32_t routing_mode) -{ - rt_uint64_t sgi_val; - - if (routing_mode) - { - sgi_val = (1ULL << 40) | ((irq & 0x0FULL) << 24); //Interrupts routed to all PEs in the system, excluding "self". - /* Write the ICC_SGI1R registers */ - __asm__ volatile("dsb 0xF" :: - : "memory"); - __set_cp64(15, 0, sgi_val, 12); - __asm__ volatile("isb 0xF" :: - : "memory"); - } - else - { - rt_uint32_t cluster_id, target_list; - while (arm_gic_cpumask_to_affval(&cpu_mask, &cluster_id, &target_list)) - { - sgi_val = ((irq & 0x0FULL) << 24 | - target_list | - ((cluster_id >> 8) & 0xFFULL) << GIC_RSGI_AFF1_OFFSET | - ((cluster_id >> 16) & 0xFFULL) << GIC_RSGI_AFF2_OFFSET | - ((cluster_id >> 24) & 0xFFull) << GIC_RSGI_AFF3_OFFSET); - - __asm__ volatile("dsb 0xF" :: - : "memory"); - __set_cp64(15, 0, sgi_val, 12); - __asm__ volatile("isb 0xF" :: - : "memory"); - } - } -} - -rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index) -{ - rt_uint32_t irq; - RT_ASSERT(index < ARM_GIC_MAX_NR); - - index = index; - __get_gicv3_reg(ICC_HPPIR1, irq); - return irq; -} - -rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); -} - -void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group) -{ - rt_uint32_t igroupr; - rt_uint32_t shift; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - RT_ASSERT(group <= 1U); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); - shift = (irq % 32U); - igroupr &= (~(1U << shift)); - igroupr |= ((group & 0x1U) << shift); - - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; -} - -rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0U); - - return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; -} - -static int arm_gicv3_wait_rwp(rt_uint32_t index, rt_uint32_t irq) -{ - rt_uint32_t rwp_bit; - rt_uint32_t base; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - if (irq < 32u) - { - rt_int32_t cpu_id = rt_hw_cpu_id(); - - RT_ASSERT((cpu_id) < RT_CPUS_NR); - base = _gic_table[index].redist_hw_base[cpu_id]; - rwp_bit = GICR_CTLR_RWP; - } - else - { - base = _gic_table[index].dist_hw_base; - rwp_bit = GICD_CTLR_RWP; - } - - while (__REG32(base) & rwp_bit) - { - ; - } - - return 0; -} - -int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) -{ - rt_uint64_t cpu0_affval; - unsigned int gic_type, i; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - _gic_table[index].dist_hw_base = dist_base; - _gic_table[index].offset = irq_start; - - /* Find out how many interrupts are supported. */ - gic_type = GIC_DIST_TYPE(dist_base); - _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U; - - /* - * The GIC only supports up to 1020 interrupt sources. - * Limit this to either the architected maximum, or the - * platform maximum. - */ - if (_gic_max_irq > 1020U) - _gic_max_irq = 1020U; - if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ - _gic_max_irq = ARM_GIC_NR_IRQS; - - GIC_DIST_CTRL(dist_base) = 0x0U; - /* Wait for register write pending */ - arm_gicv3_wait_rwp(0, 32); - - /* Set all global interrupts to be level triggered, active low. */ - for (i = 32U; i < _gic_max_irq; i += 16U) - GIC_DIST_CONFIG(dist_base, i) = 0x0U; - - arm_gicv3_wait_rwp(0, 32); - - cpu0_affval = get_main_cpu_affval(); - /* Set all global interrupts to this CPU only. */ - for (i = 32U; i < _gic_max_irq; i++) - { - GIC_DIST_IROUTER_LOW(dist_base, i) = cpu0_affval; - GIC_DIST_IROUTER_HIGH(dist_base, i) = cpu0_affval >> 32; - } - - arm_gicv3_wait_rwp(0, 32); - - /* Set priority on spi interrupts. */ - for (i = 32U; i < _gic_max_irq; i += 4U) - GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U; - - arm_gicv3_wait_rwp(0, 32); - /* Disable all interrupts. */ - for (i = 0U; i < _gic_max_irq; i += 32U) - { - GIC_DIST_PENDING_CLEAR(dist_base, i) = 0xffffffffU; - GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; - } - - arm_gicv3_wait_rwp(0, 32); - /* All interrupts defaults to IGROUP1(IRQ). */ - for (i = 0U; i < _gic_max_irq; i += 32U) - GIC_DIST_IGROUP(dist_base, i) = 0xffffffffU; - - arm_gicv3_wait_rwp(0, 32); - - /* - The Distributor control register (GICD_CTLR) must be configured to enable the interrupt groups and to set the routing mode. - Enable Affinity routing (ARE bits) The ARE bits in GICD_CTLR control whether affinity routing is enabled. - If affinity routing is not enabled, GICv3 can be configured for legacy operation. - Whether affinity routing is enabled or not can be controlled separately for Secure and Non-secure state. - Enables GICD_CTLR contains separate enable bits for Group 0, Secure Group 1 and Non-secure Group 1: - GICD_CTLR.EnableGrp1S enables distribution of Secure Group 1 interrupts. - GICD_CTLR.EnableGrp1NS enables distribution of Non-secure Group 1 interrupts. - GICD_CTLR.EnableGrp0 enables distribution of Group 0 interrupts. - */ - GIC_DIST_CTRL(dist_base) = GICD_CTLR_ARE_NS | GICD_CTLR_ENGRP1NS; - - return 0; -} - -int arm_gic_redist_address_set(rt_uint32_t index, rt_uint32_t redist_addr, rt_uint32_t cpu_id) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - RT_ASSERT((cpu_id) < RT_CPUS_NR); - _gic_table[index].redist_hw_base[cpu_id] = redist_addr; - - return 0; -} - -int arm_gic_cpu_interface_address_set(rt_uint32_t index, rt_uint32_t interface_addr, rt_uint32_t cpu_id) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - RT_ASSERT((cpu_id) < RT_CPUS_NR); - _gic_table[index].cpu_hw_base[cpu_id] = interface_addr; - - return 0; -} - -int arm_gic_redist_init(rt_uint32_t index) -{ - unsigned int i; - rt_uint32_t base; - rt_int32_t cpu_id = rt_hw_cpu_id(); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - RT_ASSERT((cpu_id) < RT_CPUS_NR); - - base = _gic_table[index].redist_hw_base[cpu_id]; - /* redistributor enable */ - GIC_RDIST_WAKER(base) &= ~(1U << 1); - while (GIC_RDIST_WAKER(base) & (1 << 2)) - { - ; - } - - /* Disable all sgi and ppi interrupt */ - GIC_RDISTSGI_ICENABLER0(base) = 0xFFFFFFFF; - arm_gicv3_wait_rwp(0, 0); - - /* Clear all inetrrupt pending */ - GIC_RDISTSGI_ICPENDR0(base) = 0xFFFFFFFF; - - /* the corresponding interrupt is Group 1 or Non-secure Group 1. */ - GIC_RDISTSGI_IGROUPR0(base, 0) = 0xFFFFFFFF; - GIC_RDISTSGI_IGRPMODR0(base, 0) = 0xFFFFFFFF; - - /* Configure default priorities for SGI 0:15 and PPI 16:31. */ - for (i = 0; i < 32; i += 4) - { - GIC_RDISTSGI_IPRIORITYR(base, i) = 0xa0a0a0a0U; - } - - /* Trigger level for PPI interrupts*/ - GIC_RDISTSGI_ICFGR1(base) = 0x0U; // PPI is level-sensitive. - return 0; -} - -int arm_gic_cpu_init(rt_uint32_t index) -{ - rt_uint32_t value; - RT_ASSERT(index < ARM_GIC_MAX_NR); - - value = arm_gic_get_system_register_enable_mask(index); - value |= (1U << 0); - arm_gic_set_system_register_enable_mask(index, value); - __set_gicv3_reg(ICC_CTLR, 0); - - arm_gic_set_interface_prior_mask(index, 0xFFU); - - /* Enable group1 interrupt */ - value = 0x1U; - __set_gicv3_reg(ICC_IGRPEN1, value); - - arm_gic_set_binary_point(0, 0); - - /* ICC_BPR0_EL1 determines the preemption group for both - Group 0 and Group 1 interrupts. - */ - value = 0x1U; - __set_gicv3_reg(ICC_CTLR, value); - - return 0; -} - -#ifdef RT_USING_SMP -void arm_gic_secondary_cpu_init(void) -{ - arm_gic_redist_init(0); - - arm_gic_cpu_init(0); -} -#endif - -void arm_gic_dump_type(rt_uint32_t index) -{ - unsigned int gic_type; - - gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); - rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", - (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, - _gic_table[index].dist_hw_base, - _gic_max_irq, - gic_type & (1U << 10U) ? "has" : "no", - gic_type); -} - -void arm_gic_dump(rt_uint32_t index) -{ - unsigned int i, k; - - k = arm_gic_get_high_pending_irq(0); - rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); - rt_kprintf("--- hw mask ---\n"); - for (i = 0U; i < _gic_max_irq / 32U; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, - i * 32U)); - } - rt_kprintf("\n--- hw pending ---\n"); - for (i = 0U; i < _gic_max_irq / 32U; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, - i * 32U)); - } - rt_kprintf("\n--- hw active ---\n"); - for (i = 0U; i < _gic_max_irq / 32U; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, - i * 32U)); - } - rt_kprintf("\n"); -} - -long gic_dump(void) -{ - arm_gic_dump_type(0); - arm_gic_dump(0); - - return 0; -} -MSH_CMD_EXPORT(gic_dump, show gic status); diff --git a/rt-thread/libcpu/arm/cortex-a/gicv3.h b/rt-thread/libcpu/arm/cortex-a/gicv3.h deleted file mode 100644 index d379552..0000000 --- a/rt-thread/libcpu/arm/cortex-a/gicv3.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#ifndef __GIC_V3_H__ -#define __GIC_V3_H__ - -#include -#include - -#define __get_gicv3_reg(CR, Rt) __asm__ volatile("MRC " CR \ - : "=r"(Rt) \ - : \ - : "memory") -#define __set_gicv3_reg(CR, Rt) __asm__ volatile("MCR " CR \ - : \ - : "r"(Rt) \ - : "memory") - - -/* AArch32 System register interface to GICv3 */ -#define ICC_IAR0 "p15, 0, %0, c12, c8, 0" -#define ICC_IAR1 "p15, 0, %0, c12, c12, 0" -#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1" -#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1" -#define ICC_HPPIR0 "p15, 0, %0, c12, c8, 2" -#define ICC_HPPIR1 "p15, 0, %0, c12, c12, 2" -#define ICC_BPR0 "p15, 0, %0, c12, c8, 3" -#define ICC_BPR1 "p15, 0, %0, c12, c12, 3" -#define ICC_DIR "p15, 0, %0, c12, c11, 1" -#define ICC_PMR "p15, 0, %0, c4, c6, 0" -#define ICC_RPR "p15, 0, %0, c12, c11, 3" -#define ICC_CTLR "p15, 0, %0, c12, c12, 4" -#define ICC_MCTLR "p15, 6, %0, c12, c12, 4" -#define ICC_SRE "p15, 0, %0, c12, c12, 5" -#define ICC_HSRE "p15, 4, %0, c12, c9, 5" -#define ICC_MSRE "p15, 6, %0, c12, c12, 5" -#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6" -#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7" -#define ICC_MGRPEN1 "p15, 6, %0, c12, c12, 7" - -#define __REG32(x) (*((volatile unsigned int*)((rt_uint32_t)x))) - -#define ROUTED_TO_ALL (1) -#define ROUTED_TO_SPEC (0) - -/** Macro to access the Distributor Control Register (GICD_CTLR) -*/ -#define GICD_CTLR_RWP (1<<31) -#define GICD_CTLR_E1NWF (1<<7) -#define GICD_CTLR_DS (1<<6) -#define GICD_CTLR_ARE_NS (1<<5) -#define GICD_CTLR_ARE_S (1<<4) -#define GICD_CTLR_ENGRP1S (1<<2) -#define GICD_CTLR_ENGRP1NS (1<<1) -#define GICD_CTLR_ENGRP0 (1<<0) - -/** Macro to access the Redistributor Control Register (GICR_CTLR) -*/ -#define GICR_CTLR_UWP (1<<31) -#define GICR_CTLR_DPG1S (1<<26) -#define GICR_CTLR_DPG1NS (1<<25) -#define GICR_CTLR_DPG0 (1<<24) -#define GICR_CTLR_RWP (1<<3) -#define GICR_CTLR_IR (1<<2) -#define GICR_CTLR_CES (1<<1) -#define GICR_CTLR_EnableLPI (1<<0) - -/** Macro to access the Generic Interrupt Controller Interface (GICC) -*/ -#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) -#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) -#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) -#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) -#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) -#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) -#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) -#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) - -/** Macro to access the Generic Interrupt Controller Distributor (GICD) -*/ -#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) -#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) -#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) -#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U) -#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) -#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U) -#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U) -#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U) -#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U) -#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U) -#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U) -#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) -#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) -#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U) -#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) -#define GIC_DIST_IROUTER_LOW(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U) -#define GIC_DIST_IROUTER_HIGH(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U + 4) - -/* SGI base address is at 64K offset from Redistributor base address */ -#define GIC_RSGI_OFFSET 0x10000 - -/** Macro to access the Generic Interrupt Controller Redistributor (GICD) -*/ -#define GIC_RDIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) -#define GIC_RDIST_IIDR(hw_base) __REG32((hw_base) + 0x004U) -#define GIC_RDIST_TYPER(hw_base) __REG32((hw_base) + 0x008U) -#define GIC_RDIST_TSTATUSR(hw_base) __REG32((hw_base) + 0x010U) -#define GIC_RDIST_WAKER(hw_base) __REG32((hw_base) + 0x014U) -#define GIC_RDIST_SETLPIR(hw_base) __REG32((hw_base) + 0x040U) -#define GIC_RDIST_CLRLPIR(hw_base) __REG32((hw_base) + 0x048U) -#define GIC_RDIST_PROPBASER(hw_base) __REG32((hw_base) + 0x070U) -#define GIC_RDIST_PENDBASER(hw_base) __REG32((hw_base) + 0x078U) -#define GIC_RDIST_INVLPIR(hw_base) __REG32((hw_base) + 0x0A0U) -#define GIC_RDIST_INVALLR(hw_base) __REG32((hw_base) + 0x0B0U) -#define GIC_RDIST_SYNCR(hw_base) __REG32((hw_base) + 0x0C0U) - -#define GIC_RDISTSGI_IGROUPR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n)*4U) -#define GIC_RDISTSGI_ISENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x100U) -#define GIC_RDISTSGI_ICENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U) -#define GIC_RDISTSGI_ISPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x200U) -#define GIC_RDISTSGI_ICPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x280U) -#define GIC_RDISTSGI_ISACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x300U) -#define GIC_RDISTSGI_ICACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x380U) -#define GIC_RDISTSGI_IPRIORITYR(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U) -#define GIC_RDISTSGI_ICFGR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U) -#define GIC_RDISTSGI_ICFGR1(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U) -#define GIC_RDISTSGI_IGRPMODR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n)*4) -#define GIC_RDISTSGI_NSACR(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U) - -#define GIC_RSGI_AFF1_OFFSET 16 -#define GIC_RSGI_AFF2_OFFSET 32 -#define GIC_RSGI_AFF3_OFFSET 48 - -rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluster_id, rt_uint32_t *target_list); -rt_uint64_t get_main_cpu_affval(void); -int arm_gic_get_active_irq(rt_uint32_t index); -void arm_gic_ack(rt_uint32_t index, int irq); - -void arm_gic_mask(rt_uint32_t index, int irq); -void arm_gic_umask(rt_uint32_t index, int irq); - -rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq); -void arm_gic_set_pending_irq(rt_uint32_t index, int irq); -void arm_gic_clear_pending_irq(rt_uint32_t index, int irq); - -void arm_gic_set_configuration(rt_uint32_t index, int irq, rt_uint32_t config); -rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq); - -void arm_gic_clear_active(rt_uint32_t index, int irq); - -void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); -rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq); - -void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority); -rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq); - -void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority); -rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index); - -void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point); -rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index); - -rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq); - -void arm_gic_send_affinity_sgi(rt_uint32_t index, int irq, rt_uint32_t cpu_mask, rt_uint32_t routing_mode); -rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index); - -rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index); - -void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group); -rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq); - -int arm_gic_redist_address_set(rt_uint32_t index, rt_uint32_t redist_addr, rt_uint32_t cpu_id); -int arm_gic_cpu_interface_address_set(rt_uint32_t index, rt_uint32_t interface_addr, rt_uint32_t cpu_id); -int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); -int arm_gic_cpu_init(rt_uint32_t index); -int arm_gic_redist_init(rt_uint32_t index); - -void arm_gic_dump_type(rt_uint32_t index); -void arm_gic_dump(rt_uint32_t index); - -void arm_gic_set_system_register_enable_mask(rt_uint32_t index, rt_uint32_t value); -rt_uint32_t arm_gic_get_system_register_enable_mask(rt_uint32_t index); -void arm_gic_secondary_cpu_init(void); -#endif - diff --git a/rt-thread/libcpu/arm/cortex-a/interrupt.c b/rt-thread/libcpu/arm/cortex-a/interrupt.c deleted file mode 100644 index f90f1c0..0000000 --- a/rt-thread/libcpu/arm/cortex-a/interrupt.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-06 Bernard first version - * 2018-11-22 Jesven add smp support - */ - -#include -#include -#include "interrupt.h" - -#ifdef RT_USING_GIC_V2 -#include "gic.h" -#else -#include "gicv3.h" -#endif - -/* exception and interrupt handler table */ -struct rt_irq_desc isr_table[MAX_HANDLERS]; - -#ifndef RT_USING_SMP -/* Those varibles will be accessed in ISR, so we need to share them. */ -rt_uint32_t rt_interrupt_from_thread = 0; -rt_uint32_t rt_interrupt_to_thread = 0; -rt_uint32_t rt_thread_switch_interrupt_flag = 0; - -#ifdef RT_USING_HOOK -static void (*rt_interrupt_switch_hook)(void); - -void rt_interrupt_switch_sethook(void (*hook)(void)) -{ - rt_interrupt_switch_hook = hook; -} -#endif - -void rt_interrupt_hook(void) -{ - RT_OBJECT_HOOK_CALL(rt_interrupt_switch_hook, ()); -} -#endif - -const unsigned int VECTOR_BASE = 0x00; -extern void rt_cpu_vector_set_base(unsigned int addr); -extern int system_vectors; - -void rt_hw_vector_init(void) -{ - rt_cpu_vector_set_base((unsigned int)&system_vectors); -} - -#ifdef RT_USING_GIC_V2 -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - rt_uint32_t gic_cpu_base; - rt_uint32_t gic_dist_base; - rt_uint32_t gic_irq_start; - - /* initialize vector table */ - rt_hw_vector_init(); - - /* initialize exceptions table */ - rt_memset(isr_table, 0x00, sizeof(isr_table)); - - /* initialize ARM GIC */ - gic_dist_base = platform_get_gic_dist_base(); - gic_cpu_base = platform_get_gic_cpu_base(); - - gic_irq_start = GIC_IRQ_START; - - arm_gic_dist_init(0, gic_dist_base, gic_irq_start); - arm_gic_cpu_init(0, gic_cpu_base); -} -#else -/** - * This function will initialize hardware interrupt - * Called by the primary cpu(cpu0) - */ -void rt_hw_interrupt_init(void) -{ - rt_uint32_t gic_dist_base; - rt_uint32_t gic_irq_start; - - /* initialize vector table */ - rt_hw_vector_init(); - - /* initialize exceptions table */ - rt_memset(isr_table, 0x00, sizeof(isr_table)); - - /* initialize ARM GIC */ - gic_dist_base = platform_get_gic_dist_base(); - gic_irq_start = GIC_IRQ_START; - - arm_gic_dist_init(0, gic_dist_base, gic_irq_start); - - arm_gic_cpu_init(0); - arm_gic_redist_init(0); -} - -#endif - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - arm_gic_mask(0, vector); -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - arm_gic_umask(0, vector); -} - -/** - * This function returns the active interrupt number. - * @param none - */ -int rt_hw_interrupt_get_irq(void) -{ - return arm_gic_get_active_irq(0); -} - -/** - * This function acknowledges the interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_ack(int vector) -{ - arm_gic_ack(0, vector); -} - -/** - * This function set interrupt CPU targets. - * @param vector: the interrupt number - * cpu_mask: target cpus mask, one bit for one core - */ -void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask) -{ - arm_gic_set_cpu(0, vector, cpu_mask); -} - -/** - * This function get interrupt CPU targets. - * @param vector: the interrupt number - * @return target cpus mask, one bit for one core - */ -unsigned int rt_hw_interrupt_get_target_cpus(int vector) -{ - return arm_gic_get_target_cpu(0, vector); -} - -/** - * This function set interrupt triger mode. - * @param vector: the interrupt number - * mode: interrupt triger mode; 0: level triger, 1: edge triger - */ -void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode) -{ - arm_gic_set_configuration(0, vector, mode); -} - -/** - * This function get interrupt triger mode. - * @param vector: the interrupt number - * @return interrupt triger mode; 0: level triger, 1: edge triger - */ -unsigned int rt_hw_interrupt_get_triger_mode(int vector) -{ - return arm_gic_get_configuration(0, vector); -} - -/** - * This function set interrupt pending flag. - * @param vector: the interrupt number - */ -void rt_hw_interrupt_set_pending(int vector) -{ - arm_gic_set_pending_irq(0, vector); -} - -/** - * This function get interrupt pending flag. - * @param vector: the interrupt number - * @return interrupt pending flag, 0: not pending; 1: pending - */ -unsigned int rt_hw_interrupt_get_pending(int vector) -{ - return arm_gic_get_pending_irq(0, vector); -} - -/** - * This function clear interrupt pending flag. - * @param vector: the interrupt number - */ -void rt_hw_interrupt_clear_pending(int vector) -{ - arm_gic_clear_pending_irq(0, vector); -} - -/** - * This function set interrupt priority value. - * @param vector: the interrupt number - * priority: the priority of interrupt to set - */ -void rt_hw_interrupt_set_priority(int vector, unsigned int priority) -{ - arm_gic_set_priority(0, vector, priority); -} - -/** - * This function get interrupt priority. - * @param vector: the interrupt number - * @return interrupt priority value - */ -unsigned int rt_hw_interrupt_get_priority(int vector) -{ - return arm_gic_get_priority(0, vector); -} - -/** - * This function set priority masking threshold. - * @param priority: priority masking threshold - */ -void rt_hw_interrupt_set_priority_mask(unsigned int priority) -{ - arm_gic_set_interface_prior_mask(0, priority); -} - -/** - * This function get priority masking threshold. - * @param none - * @return priority masking threshold - */ -unsigned int rt_hw_interrupt_get_priority_mask(void) -{ - return arm_gic_get_interface_prior_mask(0); -} - -/** - * This function set priority grouping field split point. - * @param bits: priority grouping field split point - * @return 0: success; -1: failed - */ -int rt_hw_interrupt_set_prior_group_bits(unsigned int bits) -{ - int status; - - if (bits < 8) - { - arm_gic_set_binary_point(0, (7 - bits)); - status = 0; - } - else - { - status = -1; - } - - return (status); -} - -/** - * This function get priority grouping field split point. - * @param none - * @return priority grouping field split point - */ -unsigned int rt_hw_interrupt_get_prior_group_bits(void) -{ - unsigned int bp; - - bp = arm_gic_get_binary_point(0) & 0x07; - - return (7 - bp); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param new_handler the interrupt service routine to be installed - * @param old_handler the old interrupt service routine - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if (vector < MAX_HANDLERS) - { - old_handler = isr_table[vector].handler; - - if (handler != RT_NULL) - { -#ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); -#endif /* RT_USING_INTERRUPT_INFO */ - isr_table[vector].handler = handler; - isr_table[vector].param = param; - } - } - - return old_handler; -} - -#ifdef RT_USING_SMP -void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) -{ -#ifdef RT_USING_GIC_V2 - arm_gic_send_sgi(0, ipi_vector, cpu_mask, 0); -#else - arm_gic_send_affinity_sgi(0, ipi_vector, cpu_mask, ROUTED_TO_SPEC); -#endif -} - -void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler) -{ - /* note: ipi_vector maybe different with irq_vector */ - rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER"); -} -#endif - diff --git a/rt-thread/libcpu/arm/cortex-a/interrupt.h b/rt-thread/libcpu/arm/cortex-a/interrupt.h deleted file mode 100644 index dda6c55..0000000 --- a/rt-thread/libcpu/arm/cortex-a/interrupt.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-06 Bernard first version - */ - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#include -#include - -#define INT_IRQ 0x00 -#define INT_FIQ 0x01 - -#define IRQ_MODE_TRIG_LEVEL (0x00) /* Trigger: level triggered interrupt */ -#define IRQ_MODE_TRIG_EDGE (0x01) /* Trigger: edge triggered interrupt */ - -void rt_hw_vector_init(void); - -void rt_hw_interrupt_init(void); -void rt_hw_interrupt_mask(int vector); -void rt_hw_interrupt_umask(int vector); - -int rt_hw_interrupt_get_irq(void); -void rt_hw_interrupt_ack(int vector); - -void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask); -unsigned int rt_hw_interrupt_get_target_cpus(int vector); - -void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode); -unsigned int rt_hw_interrupt_get_triger_mode(int vector); - -void rt_hw_interrupt_set_pending(int vector); -unsigned int rt_hw_interrupt_get_pending(int vector); -void rt_hw_interrupt_clear_pending(int vector); - -void rt_hw_interrupt_set_priority(int vector, unsigned int priority); -unsigned int rt_hw_interrupt_get_priority(int vector); - -void rt_hw_interrupt_set_priority_mask(unsigned int priority); -unsigned int rt_hw_interrupt_get_priority_mask(void); - -int rt_hw_interrupt_set_prior_group_bits(unsigned int bits); -unsigned int rt_hw_interrupt_get_prior_group_bits(void); - -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name); - -#ifdef RT_USING_SMP -void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask); -void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler); -#endif - -#endif - diff --git a/rt-thread/libcpu/arm/cortex-a/mmu.c b/rt-thread/libcpu/arm/cortex-a/mmu.c deleted file mode 100644 index 243fe19..0000000 --- a/rt-thread/libcpu/arm/cortex-a/mmu.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2012-01-10 bernard porting to AM1808 - */ - -#include -#include -#include - -#include "cp15.h" -#include "mmu.h" - -/* dump 2nd level page table */ -void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb) -{ - int i; - int fcnt = 0; - - for (i = 0; i < 256; i++) - { - rt_uint32_t pte2 = ptb[i]; - if ((pte2 & 0x3) == 0) - { - if (fcnt == 0) - rt_kprintf(" "); - rt_kprintf("%04x: ", i); - fcnt++; - if (fcnt == 16) - { - rt_kprintf("fault\n"); - fcnt = 0; - } - continue; - } - if (fcnt != 0) - { - rt_kprintf("fault\n"); - fcnt = 0; - } - - rt_kprintf(" %04x: %x: ", i, pte2); - if ((pte2 & 0x3) == 0x1) - { - rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n", - ((pte2 >> 7) | (pte2 >> 4))& 0xf, - (pte2 >> 15) & 0x1, - ((pte2 >> 10) | (pte2 >> 2)) & 0x1f); - } - else - { - rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n", - ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1, - ((pte2 >> 4) | (pte2 >> 2)) & 0x1f); - } - } -} - -void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) -{ - int i; - int fcnt = 0; - - rt_kprintf("page table@%p\n", ptb); - for (i = 0; i < 1024*4; i++) - { - rt_uint32_t pte1 = ptb[i]; - if ((pte1 & 0x3) == 0) - { - rt_kprintf("%03x: ", i); - fcnt++; - if (fcnt == 16) - { - rt_kprintf("fault\n"); - fcnt = 0; - } - continue; - } - if (fcnt != 0) - { - rt_kprintf("fault\n"); - fcnt = 0; - } - - rt_kprintf("%03x: %08x: ", i, pte1); - if ((pte1 & 0x3) == 0x3) - { - rt_kprintf("LPAE\n"); - } - else if ((pte1 & 0x3) == 0x1) - { - rt_kprintf("pte,ns:%d,domain:%d\n", - (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); - /* - *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) - * - 0x80000000 + 0xC0000000)); - */ - } - else if (pte1 & (1 << 18)) - { - rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", - (pte1 >> 19) & 0x1, - ((pte1 >> 13) | (pte1 >> 10))& 0xf, - (pte1 >> 4) & 0x1, - ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); - } - else - { - rt_kprintf("section,ns:%d,ap:%x," - "xn:%d,texcb:%02x,domain:%d\n", - (pte1 >> 19) & 0x1, - ((pte1 >> 13) | (pte1 >> 10))& 0xf, - (pte1 >> 4) & 0x1, - (((pte1 & (0x7 << 12)) >> 10) | - ((pte1 & 0x0c) >> 2)) & 0x1f, - (pte1 >> 5) & 0xf); - } - } -} - -/* level1 page table, each entry for 1MB memory. */ -volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); -void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, - rt_uint32_t vaddrEnd, - rt_uint32_t paddrStart, - rt_uint32_t attr) -{ - volatile rt_uint32_t *pTT; - volatile int i, nSec; - pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20); - nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); - for(i = 0; i <= nSec; i++) - { - *pTT = attr | (((paddrStart >> 20) + i) << 20); - pTT++; - } -} - -unsigned long rt_hw_set_domain_register(unsigned long domain_val) -{ - unsigned long old_domain; - - asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); - asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); - - return old_domain; -} - -void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size) -{ - /* set page table */ - for(; size > 0; size--) - { - rt_hw_mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end, - mdesc->paddr_start, mdesc->attr); - mdesc++; - } -} - -void rt_hw_mmu_init(void) -{ - rt_cpu_dcache_clean_flush(); - rt_cpu_icache_flush(); - rt_hw_cpu_dcache_disable(); - rt_hw_cpu_icache_disable(); - rt_cpu_mmu_disable(); - - /*rt_hw_cpu_dump_page_table(MMUTable);*/ - rt_hw_set_domain_register(0x55555555); - - rt_cpu_tlb_set(MMUTable); - - rt_cpu_mmu_enable(); - - rt_hw_cpu_icache_enable(); - rt_hw_cpu_dcache_enable(); -} - diff --git a/rt-thread/libcpu/arm/cortex-a/mmu.h b/rt-thread/libcpu/arm/cortex-a/mmu.h deleted file mode 100644 index 5cc60a7..0000000 --- a/rt-thread/libcpu/arm/cortex-a/mmu.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-25 quanzhao the first version - */ -#ifndef __MMU_H_ -#define __MMU_H_ - -#include - -#define DESC_SEC (0x2) -#define MEMWBWA ((1<<12)|(3<<2)) /* write back, write allocate */ -#define MEMWB (3<<2) /* write back, no write allocate */ -#define MEMWT (2<<2) /* write through, no write allocate */ -#define SHAREDEVICE (1<<2) /* shared device */ -#define STRONGORDER (0<<2) /* strong ordered */ -#define XN (1<<4) /* eXecute Never */ -#define AP_RW (3<<10) /* supervisor=RW, user=RW */ -#define AP_RO (2<<10) /* supervisor=RW, user=RO */ -#define SHARED (1<<16) /* shareable */ - -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) - -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) - -/* device mapping type */ -#define DEVICE_MEM (SHARED|AP_RW|DOMAIN0|SHAREDEVICE|DESC_SEC|XN) -/* normal memory mapping type */ -#define NORMAL_MEM (SHARED|AP_RW|DOMAIN0|MEMWBWA|DESC_SEC) - -struct mem_desc -{ - rt_uint32_t vaddr_start; - rt_uint32_t vaddr_end; - rt_uint32_t paddr_start; - rt_uint32_t attr; -}; - - -#endif diff --git a/rt-thread/libcpu/arm/cortex-a/stack.c b/rt-thread/libcpu/arm/cortex-a/stack.c deleted file mode 100644 index e68b324..0000000 --- a/rt-thread/libcpu/arm/cortex-a/stack.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-09-23 Bernard the first version - * 2011-10-05 Bernard add thumb mode - */ -#include -#include -#include - -/** - * @addtogroup AM33xx - */ -/*@{*/ - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - - stack_addr += sizeof(rt_uint32_t); - stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); - stk = (rt_uint32_t *)stack_addr; - *(--stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0xdeadbeef; /* r12 */ - *(--stk) = 0xdeadbeef; /* r11 */ - *(--stk) = 0xdeadbeef; /* r10 */ - *(--stk) = 0xdeadbeef; /* r9 */ - *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = 0xdeadbeef; /* r4 */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = 0xdeadbeef; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ - -#ifdef RT_USING_LWP - *(--stk) = 0; /* user lr */ - *(--stk) = 0; /* user sp*/ -#endif -#ifdef RT_USING_FPU - *(--stk) = 0; /* not use fpu*/ -#endif - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/cortex-a/start_gcc.S b/rt-thread/libcpu/arm/cortex-a/start_gcc.S deleted file mode 100644 index f73b678..0000000 --- a/rt-thread/libcpu/arm/cortex-a/start_gcc.S +++ /dev/null @@ -1,487 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - * 2018-11-22 Jesven in the interrupt context, use rt_scheduler_do_irq_switch checks - * and switches to a new thread - */ - -#include "rtconfig.h" -.equ Mode_USR, 0x10 -.equ Mode_FIQ, 0x11 -.equ Mode_IRQ, 0x12 -.equ Mode_SVC, 0x13 -.equ Mode_ABT, 0x17 -.equ Mode_UND, 0x1B -.equ Mode_SYS, 0x1F - -.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled -.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled - -.equ UND_Stack_Size, 0x00000400 -.equ SVC_Stack_Size, 0x00000400 -.equ ABT_Stack_Size, 0x00000400 -.equ RT_FIQ_STACK_PGSZ, 0x00000000 -.equ RT_IRQ_STACK_PGSZ, 0x00000800 -.equ USR_Stack_Size, 0x00000400 - -.equ SUB_UND_Stack_Size, 0x00000400 -.equ SUB_SVC_Stack_Size, 0x00000400 -.equ SUB_ABT_Stack_Size, 0x00000400 -.equ SUB_RT_FIQ_STACK_PGSZ, 0x00000000 -.equ SUB_RT_IRQ_STACK_PGSZ, 0x00000400 -.equ SUB_USR_Stack_Size, 0x00000400 - -#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ) - -#define SUB_ISR_Stack_Size (SUB_UND_Stack_Size + SUB_SVC_Stack_Size + SUB_ABT_Stack_Size + \ - SUB_RT_FIQ_STACK_PGSZ + SUB_RT_IRQ_STACK_PGSZ) - -.section .bss.share.isr -/* stack */ -.globl stack_start -.globl stack_top - -.align 3 -stack_start: -.rept ISR_Stack_Size -.byte 0 -.endr -stack_top: - -.text -/* reset entry */ -.globl _reset -_reset: -#ifdef ARCH_ARMV8 - /* Check for HYP mode */ - mrs r0, cpsr_all - and r0, r0, #0x1F - mov r8, #0x1A - cmp r0, r8 - beq overHyped - b continue - -overHyped: /* Get out of HYP mode */ - adr r1, continue - msr ELR_hyp, r1 - mrs r1, cpsr_all - and r1, r1, #0x1f ;@ CPSR_MODE_MASK - orr r1, r1, #0x13 ;@ CPSR_MODE_SUPERVISOR - msr SPSR_hyp, r1 - eret - -continue: -#endif - /* set the cpu to SVC32 mode and disable interrupt */ - cps #Mode_SVC - -#ifdef RT_USING_FPU - mov r4, #0xfffffff - mcr p15, 0, r4, c1, c0, 2 -#endif - - /* disable the data alignment check */ - mrc p15, 0, r1, c1, c0, 0 - bic r1, #(1<<0) /* Disable MMU */ - bic r1, #(1<<1) /* Disable Alignment fault checking */ - bic r1, #(1<<2) /* Disable data cache */ - bic r1, #(1<<11) /* Disable program flow prediction */ - bic r1, #(1<<12) /* Disable instruction cache */ - bic r1, #(3<<19) /* bit[20:19] must be zero */ - mcr p15, 0, r1, c1, c0, 0 - - @ get cpu id, and subtract the offset from the stacks base address - bl rt_hw_cpu_id - mov r5, r0 - - cmp r5, #0 @ cpu id == 0 - beq normal_setup - - @ cpu id > 0, stop or wait -#ifdef RT_SMP_AUTO_BOOT - ldr r0, =secondary_cpu_entry - mov r1, #0 - str r1, [r0] /* clean secondary_cpu_entry */ -#endif /* RT_SMP_AUTO_BOOT */ - -secondary_loop: - @ cpu core 1 goes into sleep until core 0 wakeup it - wfe -#ifdef RT_SMP_AUTO_BOOT - ldr r1, =secondary_cpu_entry - ldr r0, [r1] - cmp r0, #0 - blxne r0 /* if(secondary_cpu_entry) secondary_cpu_entry(); */ -#endif /* RT_SMP_AUTO_BOOT */ - b secondary_loop - -normal_setup: - /* setup stack */ - bl stack_setup - - /* clear .bss */ - mov r0,#0 /* get a zero */ - ldr r1,=__bss_start /* bss start */ - ldr r2,=__bss_end /* bss end */ - -bss_loop: - cmp r1,r2 /* check if data to clear */ - strlo r0,[r1],#4 /* clear 4 bytes */ - blo bss_loop /* loop until done */ - -#ifdef RT_USING_SMP - mrc p15, 0, r1, c1, c0, 1 - mov r0, #(1<<6) - orr r1, r0 - mcr p15, 0, r1, c1, c0, 1 //enable smp -#endif - - /* enable branch prediction */ - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #(1<<11) - mcr p15, 0, r0, c1, c0, 0 - - /* initialize the mmu table and enable mmu */ - ldr r0, =platform_mem_desc - ldr r1, =platform_mem_desc_size - ldr r1, [r1] - bl rt_hw_init_mmu_table - bl rt_hw_mmu_init - - /* start RT-Thread Kernel */ - ldr pc, _rtthread_startup -_rtthread_startup: - .word rtthread_startup - -stack_setup: - ldr r0, =stack_top - - @ Set the startup stack for svc - mov sp, r0 - sub r0, r0, #SVC_Stack_Size - - @ Enter Undefined Instruction Mode and set its Stack Pointer - msr cpsr_c, #Mode_UND|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #UND_Stack_Size - - @ Enter Abort Mode and set its Stack Pointer - msr cpsr_c, #Mode_ABT|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #ABT_Stack_Size - - @ Enter FIQ Mode and set its Stack Pointer - msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #RT_FIQ_STACK_PGSZ - - @ Enter IRQ Mode and set its Stack Pointer - msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #RT_IRQ_STACK_PGSZ - - /* come back to SVC mode */ - msr cpsr_c, #Mode_SVC|I_Bit|F_Bit - bx lr - -/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */ -.section .text.isr, "ax" - .align 5 -.globl vector_fiq -vector_fiq: - stmfd sp!,{r0-r7,lr} - bl rt_hw_trap_fiq - ldmfd sp!,{r0-r7,lr} - subs pc, lr, #4 - -.globl rt_interrupt_enter -.globl rt_interrupt_leave -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread - -.globl rt_current_thread -.globl vmm_thread -.globl vmm_virq_check - - .align 5 -.globl vector_irq -vector_irq: -#ifdef RT_USING_SMP - clrex - - stmfd sp!, {r0, r1} - cps #Mode_SVC - mov r0, sp /* svc_sp */ - mov r1, lr /* svc_lr */ - - cps #Mode_IRQ - sub lr, #4 - stmfd r0!, {r1, lr} /* svc_lr, svc_pc */ - stmfd r0!, {r2 - r12} - ldmfd sp!, {r1, r2} /* original r0, r1 */ - stmfd r0!, {r1 - r2} - mrs r1, spsr /* original mode */ - stmfd r0!, {r1} - -#ifdef RT_USING_LWP - stmfd r0, {r13, r14}^ /* usr_sp, usr_lr */ - sub r0, #8 -#endif -#ifdef RT_USING_FPU - /* fpu context */ - vmrs r6, fpexc - tst r6, #(1<<30) - beq 1f - vstmdb r0!, {d0-d15} - vstmdb r0!, {d16-d31} - vmrs r5, fpscr - stmfd r0!, {r5} -1: - stmfd r0!, {r6} -#endif - - /* now irq stack is clean */ - /* r0 is task svc_sp */ - /* backup r0 -> r8 */ - mov r8, r0 - - bl rt_interrupt_enter - bl rt_hw_trap_irq - bl rt_interrupt_leave - - cps #Mode_SVC - mov sp, r8 - mov r0, r8 - bl rt_scheduler_do_irq_switch - - b rt_hw_context_switch_exit - -#else - stmfd sp!, {r0-r12,lr} - - bl rt_interrupt_enter - bl rt_hw_trap_irq - bl rt_interrupt_leave - - @ if rt_thread_switch_interrupt_flag set, jump to - @ rt_hw_context_switch_interrupt_do and don't return - ldr r0, =rt_thread_switch_interrupt_flag - ldr r1, [r0] - cmp r1, #1 - beq rt_hw_context_switch_interrupt_do - - ldmfd sp!, {r0-r12,lr} - subs pc, lr, #4 - -rt_hw_context_switch_interrupt_do: - mov r1, #0 @ clear flag - str r1, [r0] - - mov r1, sp @ r1 point to {r0-r3} in stack - add sp, sp, #4*4 - ldmfd sp!, {r4-r12,lr}@ reload saved registers - mrs r0, spsr @ get cpsr of interrupt thread - sub r2, lr, #4 @ save old task's pc to r2 - - @ Switch to SVC mode with no interrupt. If the usr mode guest is - @ interrupted, this will just switch to the stack of kernel space. - @ save the registers in kernel space won't trigger data abort. - msr cpsr_c, #I_Bit|F_Bit|Mode_SVC - - stmfd sp!, {r2} @ push old task's pc - stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4 - ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread - stmfd sp!, {r1-r4} @ push old task's r0-r3 - stmfd sp!, {r0} @ push old task's cpsr - -#ifdef RT_USING_LWP - stmfd sp, {r13, r14}^ @push usr_sp, usr_lr - sub sp, #8 -#endif -#ifdef RT_USING_FPU - /* fpu context */ - vmrs r6, fpexc - tst r6, #(1<<30) - beq 1f - vstmdb sp!, {d0-d15} - vstmdb sp!, {d16-d31} - vmrs r5, fpscr - stmfd sp!, {r5} -1: - stmfd sp!, {r6} -#endif - - ldr r4, =rt_interrupt_from_thread - ldr r5, [r4] - str sp, [r5] @ store sp in preempted tasks's TCB - - ldr r6, =rt_interrupt_to_thread - ldr r6, [r6] - ldr sp, [r6] @ get new task's stack pointer - - bl rt_interrupt_hook - -#ifdef RT_USING_FPU -/* fpu context */ - ldmfd sp!, {r6} - vmsr fpexc, r6 - tst r6, #(1<<30) - beq 1f - ldmfd sp!, {r5} - vmsr fpscr, r5 - vldmia sp!, {d16-d31} - vldmia sp!, {d0-d15} -1: -#endif - -#ifdef RT_USING_LWP - ldmfd sp, {r13, r14}^ @pop usr_sp, usr_lr - add sp, #8 -#endif - - ldmfd sp!, {r4} @ pop new task's cpsr to spsr - msr spsr_cxsf, r4 - - ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr - -#endif - -.macro push_svc_reg - sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ - stmia sp, {r0 - r12} @/* Calling r0-r12 */ - mov r0, sp - mrs r6, spsr @/* Save CPSR */ - str lr, [r0, #15*4] @/* Push PC */ - str r6, [r0, #16*4] @/* Push CPSR */ - mrs r5, cpsr @/* Save CPSR */ - - and r4, r6, #0x1F - cmp r4, #Mode_USR - moveq r6, #Mode_SYS - - orr r6, r6, #0x80 @/* Switch to previous mode, then save SP & PC */ - msr cpsr_c, r6 - str sp, [r0, #13*4] @/* Save calling SP */ - str lr, [r0, #14*4] @/* Save calling PC */ - - msr cpsr_c, r5 @/* Switch back to current mode */ -.endm - - .align 5 -.weak vector_swi -vector_swi: - push_svc_reg - bl rt_hw_trap_swi - b . - - .align 5 - .globl vector_undef -vector_undef: - push_svc_reg - cps #Mode_UND - bl rt_hw_trap_undef -#ifdef RT_USING_FPU - ldr lr, [sp, #15*4] - ldmia sp, {r0 - r12} - add sp, sp, #17 * 4 - movs pc, lr -#endif - b . - - .align 5 - .globl vector_pabt -vector_pabt: - push_svc_reg - bl rt_hw_trap_pabt - b . - - .align 5 - .globl vector_dabt -vector_dabt: - push_svc_reg - bl rt_hw_trap_dabt - b . - - .align 5 - .globl vector_resv -vector_resv: - push_svc_reg - bl rt_hw_trap_resv - b . - -#ifdef RT_USING_SMP -.global secondary_cpu_start -secondary_cpu_start: - -#ifdef RT_USING_FPU - mov r4, #0xfffffff - mcr p15, 0, r4, c1, c0, 2 -#endif - - mrc p15, 0, r1, c1, c0, 1 - mov r0, #(1<<6) - orr r1, r0 - mcr p15, 0, r1, c1, c0, 1 //enable smp - - mrc p15, 0, r0, c1, c0, 0 - bic r0, #(1<<13) - mcr p15, 0, r0, c1, c0, 0 - - /* enable branch prediction */ - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #(1<<11) - mcr p15, 0, r0, c1, c0, 0 - - @ get cpu id, and subtract the offset from the stacks base address - bl rt_hw_cpu_id - sub r5, r0, #1 - - ldr r0, =SUB_ISR_Stack_Size - mul r0, r0, r5 @r0 = SUB_ISR_Stack_Size * (cpuid - 1) - ldr r1, =sub_stack_top - sub r0, r1, r0 @r0 = sub_stack_top - (SUB_ISR_Stack_Size * (cpuid - 1)) - - cps #Mode_SVC - mov sp, r0 - sub r0, r0, #SUB_SVC_Stack_Size - - cps #Mode_UND - mov sp, r0 - sub r0, r0, #SUB_UND_Stack_Size - - cps #Mode_ABT - mov sp, r0 - sub r0, r0, #SUB_ABT_Stack_Size - - cps #Mode_FIQ - mov sp, r0 - sub r0, r0, #SUB_RT_FIQ_STACK_PGSZ - - cps #Mode_IRQ - mov sp, r0 - sub r0, r0, #SUB_RT_IRQ_STACK_PGSZ - - cps #Mode_SVC - - /* initialize the mmu table and enable mmu */ - bl rt_hw_mmu_init - - b secondary_cpu_c_start - -.bss -.align 2 //align to 2~2=4 - -.global sub_stack_top /* used for backtrace to calculate stack top of irq mode */ - -sub_stack_start: - .space (SUB_ISR_Stack_Size * (RT_CPUS_NR-1)) -sub_stack_top: - -#endif diff --git a/rt-thread/libcpu/arm/cortex-a/trap.c b/rt-thread/libcpu/arm/cortex-a/trap.c deleted file mode 100644 index e8b3c8f..0000000 --- a/rt-thread/libcpu/arm/cortex-a/trap.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#include -#include -#include - -#include "armv7.h" -#include "interrupt.h" - -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) -extern long list_thread(void); -#endif - -static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL; - -/** - * This function set the hook, which is invoked on fault exception handling. - * - * @param exception_handle the exception handling hook function. - */ -void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context)) -{ - rt_exception_hook = exception_handle; -} - -/** - * this function will show registers of CPU - * - * @param regs the registers point - */ -void rt_hw_show_register(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); - if (rt_exception_hook != RT_NULL) - { - rt_err_t result; - - result = rt_exception_hook(regs); - if (result == RT_EOK) return; - } -} - -void (*rt_trap_hook)(struct rt_hw_exp_stack *regs, const char *ex, unsigned int exception_type); - -/** - * This function will set a hook function to trap handler. - * - * @param hook the hook function - */ -void rt_hw_trap_set_hook(void (*hook)(struct rt_hw_exp_stack *regs, const char *ex, unsigned int exception_type)) -{ - rt_trap_hook = hook; -} - -/** - * When comes across an instruction which it cannot handle, - * it takes the undefined instruction trap. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) -{ -#ifdef RT_USING_FPU - { - uint32_t val; - uint32_t addr; - - if (regs->cpsr & (1 << 5)) - { - /* thumb mode */ - addr = regs->pc - 2; - } - else - { - addr = regs->pc - 4; - } - asm volatile ("vmrs %0, fpexc" : "=r"(val)::"memory"); - - if (!(val & 0x40000000)) - { - /* float ins */ - val = (1U << 30); - - asm volatile ("vmsr fpexc, %0"::"r"(val):"memory"); - regs->pc = addr; - return; - } - } -#endif - - if (rt_trap_hook == RT_NULL) - { - rt_kprintf("undefined instruction:\n"); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); - } - else - { - rt_trap_hook(regs, "undefined instruction", UND_EXCEPTION); - } -} - -/** - * The software interrupt instruction (SWI) is used for entering - * Supervisor mode, usually to request a particular supervisor - * function. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_swi(struct rt_hw_exp_stack *regs) -{ - if (rt_trap_hook == RT_NULL) - { - rt_kprintf("software interrupt:\n"); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); - } - else - { - rt_trap_hook(regs, "software instruction", SWI_EXCEPTION); - } -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during an instruction prefetch. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) -{ - if (rt_trap_hook == RT_NULL) - { - rt_kprintf("prefetch abort:\n"); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); - } - else - { - rt_trap_hook(regs, "prefetch abort", PABT_EXCEPTION); - } -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during a data access. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) -{ - if (rt_trap_hook == RT_NULL) - { - rt_kprintf("data abort:"); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); - } - else - { - rt_trap_hook(regs, "data abort", DABT_EXCEPTION); - } -} - -/** - * Normally, system will never reach here - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) -{ - if (rt_trap_hook == RT_NULL) - { - rt_kprintf("reserved trap:\n"); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); - } - else - { - rt_trap_hook(regs, "reserved trap", RESV_EXCEPTION); - } -} - -void rt_hw_trap_irq(void) -{ - void *param; - int int_ack; - int ir; - rt_isr_handler_t isr_func; - extern struct rt_irq_desc isr_table[]; - - int_ack = rt_hw_interrupt_get_irq(); - - ir = int_ack & GIC_ACK_INTID_MASK; - if (ir == 1023) - { - /* Spurious interrupt */ - return; - } - - /* get interrupt service routine */ - isr_func = isr_table[ir].handler; -#ifdef RT_USING_INTERRUPT_INFO - isr_table[ir].counter++; -#endif - if (isr_func) - { - /* Interrupt for myself. */ - param = isr_table[ir].param; - /* turn to interrupt service routine */ - isr_func(ir, param); - } - - /* end of interrupt */ - rt_hw_interrupt_ack(int_ack); -} - -void rt_hw_trap_fiq(void) -{ - void *param; - int ir; - rt_isr_handler_t isr_func; - extern struct rt_irq_desc isr_table[]; - - ir = rt_hw_interrupt_get_irq(); - - /* get interrupt service routine */ - isr_func = isr_table[ir].handler; - param = isr_table[ir].param; - - /* turn to interrupt service routine */ - isr_func(ir, param); - - /* end of interrupt */ - rt_hw_interrupt_ack(ir); -} - diff --git a/rt-thread/libcpu/arm/cortex-a/vector_gcc.S b/rt-thread/libcpu/arm/cortex-a/vector_gcc.S deleted file mode 100644 index 60d3c6c..0000000 --- a/rt-thread/libcpu/arm/cortex-a/vector_gcc.S +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - */ - -.section .vectors, "ax" -.code 32 - -.globl system_vectors -system_vectors: - ldr pc, _vector_reset - ldr pc, _vector_undef - ldr pc, _vector_swi - ldr pc, _vector_pabt - ldr pc, _vector_dabt - ldr pc, _vector_resv - ldr pc, _vector_irq - ldr pc, _vector_fiq - -.globl _reset -.globl vector_undef -.globl vector_swi -.globl vector_pabt -.globl vector_dabt -.globl vector_resv -.globl vector_irq -.globl vector_fiq - -_vector_reset: - .word _reset -_vector_undef: - .word vector_undef -_vector_swi: - .word vector_swi -_vector_pabt: - .word vector_pabt -_vector_dabt: - .word vector_dabt -_vector_resv: - .word vector_resv -_vector_irq: - .word vector_irq -_vector_fiq: - .word vector_fiq - -.balignl 16,0xdeadbeef diff --git a/rt-thread/libcpu/arm/cortex-m0/SConscript b/rt-thread/libcpu/arm/cortex-m0/SConscript deleted file mode 100644 index b259a94..0000000 --- a/rt-thread/libcpu/arm/cortex-m0/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/cortex-m0/context_gcc.S b/rt-thread/libcpu/arm/cortex-m0/context_gcc.S deleted file mode 100644 index 59a81bc..0000000 --- a/rt-thread/libcpu/arm/cortex-m0/context_gcc.S +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-01-25 Bernard first version - * 2012-06-01 aozima set pendsv priority to 0xFF. - * 2012-08-17 aozima fixed bug: store r8 - r11. - * 2013-02-20 aozima port to gcc. - * 2013-06-18 aozima add restore MSP feature. - * 2013-11-04 bright fixed hardfault bug for gcc. - */ - - .cpu cortex-m0 - .fpu softvfp - .syntax unified - .thumb - .text - - .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ - .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ - .equ NVIC_SHPR3, 0xE000ED20 /* system priority register (3) */ - .equ NVIC_PENDSV_PRI, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */ - .equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ - -/* - * rt_base_t rt_hw_interrupt_disable(); - */ - .global rt_hw_interrupt_disable - .type rt_hw_interrupt_disable, %function -rt_hw_interrupt_disable: - MRS R0, PRIMASK - CPSID I - BX LR - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ - .global rt_hw_interrupt_enable - .type rt_hw_interrupt_enable, %function -rt_hw_interrupt_enable: - MSR PRIMASK, R0 - BX LR - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * R0 --> from - * R1 --> to - */ - .global rt_hw_context_switch_interrupt - .type rt_hw_context_switch_interrupt, %function - .global rt_hw_context_switch - .type rt_hw_context_switch, %function -rt_hw_context_switch_interrupt: -rt_hw_context_switch: - /* set rt_thread_switch_interrupt_flag to 1 */ - LDR R2, =rt_thread_switch_interrupt_flag - LDR R3, [R2] - CMP R3, #1 - BEQ _reswitch - MOVS R3, #1 - STR R3, [R2] - - LDR R2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - STR R0, [R2] - -_reswitch: - LDR R2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - STR R1, [R2] - - LDR R0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ - LDR R1, =NVIC_PENDSVSET - STR R1, [R0] - BX LR - -/* R0 --> switch from thread stack - * R1 --> switch to thread stack - * psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack - */ - .global PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - /* disable interrupt to protect context switch */ - MRS R2, PRIMASK - CPSID I - - /* get rt_thread_switch_interrupt_flag */ - LDR R0, =rt_thread_switch_interrupt_flag - LDR R1, [R0] - CMP R1, #0x00 - BEQ pendsv_exit /* pendsv already handled */ - - /* clear rt_thread_switch_interrupt_flag to 0 */ - MOVS R1, #0 - STR R1, [R0] - - LDR R0, =rt_interrupt_from_thread - LDR R1, [R0] - CMP R1, #0x00 - BEQ switch_to_thread /* skip register save at the first time */ - - MRS R1, PSP /* get from thread stack pointer */ - - SUBS R1, R1, #0x20 /* space for {R4 - R7} and {R8 - R11} */ - LDR R0, [R0] - STR R1, [R0] /* update from thread stack pointer */ - - STMIA R1!, {R4 - R7} /* push thread {R4 - R7} register to thread stack */ - - MOV R4, R8 /* mov thread {R8 - R11} to {R4 - R7} */ - MOV R5, R9 - MOV R6, R10 - MOV R7, R11 - STMIA R1!, {R4 - R7} /* push thread {R8 - R11} high register to thread stack */ -switch_to_thread: - LDR R1, =rt_interrupt_to_thread - LDR R1, [R1] - LDR R1, [R1] /* load thread stack pointer */ - - LDMIA R1!, {R4 - R7} /* pop thread {R4 - R7} register from thread stack */ - PUSH {R4 - R7} /* push {R4 - R7} to MSP for copy {R8 - R11} */ - - LDMIA R1!, {R4 - R7} /* pop thread {R8 - R11} high register from thread stack to {R4 - R7} */ - MOV R8, R4 /* mov {R4 - R7} to {R8 - R11} */ - MOV R9, R5 - MOV R10, R6 - MOV R11, R7 - - POP {R4 - R7} /* pop {R4 - R7} from MSP */ - - MSR PSP, R1 /* update stack pointer */ - -pendsv_exit: - /* restore interrupt */ - MSR PRIMASK, R2 - - MOVS R0, #0x04 - RSBS R0, R0, #0x00 - BX R0 -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * R0 --> to - */ - .global rt_hw_context_switch_to - .type rt_hw_context_switch_to, %function -rt_hw_context_switch_to: - LDR R1, =rt_interrupt_to_thread - STR R0, [R1] - - /* set from thread to 0 */ - LDR R1, =rt_interrupt_from_thread - MOVS R0, #0 - STR R0, [R1] - - /* set interrupt flag to 1 */ - LDR R1, =rt_thread_switch_interrupt_flag - MOVS R0, #1 - STR R0, [R1] - - /* set the PendSV and SysTick exception priority */ - LDR R0, =NVIC_SHPR3 - LDR R1, =NVIC_PENDSV_PRI - LDR R2, [R0,#0x00] /* read */ - ORRS R1, R1, R2 /* modify */ - STR R1, [R0] /* write-back */ - - LDR R0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ - LDR R1, =NVIC_PENDSVSET - STR R1, [R0] - NOP - /* restore MSP */ - LDR R0, =SCB_VTOR - LDR R0, [R0] - LDR R0, [R0] - NOP - MSR MSP, R0 - - /* enable interrupts at processor level */ - CPSIE I - - /* ensure PendSV exception taken place before subsequent operation */ - DSB - ISB - - /* never reach here! */ - -/* compatible with old version */ - .global rt_hw_interrupt_thread_switch - .type rt_hw_interrupt_thread_switch, %function -rt_hw_interrupt_thread_switch: - BX LR - NOP - - .global HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - /* get current context */ - MRS R0, PSP /* get fault thread stack pointer */ - PUSH {LR} - BL rt_hw_hard_fault_exception - POP {PC} - - -/* - * rt_uint32_t rt_hw_interrupt_check(void); - * R0 --> state - */ - .global rt_hw_interrupt_check - .type rt_hw_interrupt_check, %function -rt_hw_interrupt_check: - MRS R0, IPSR - BX LR diff --git a/rt-thread/libcpu/arm/cortex-m0/context_iar.S b/rt-thread/libcpu/arm/cortex-m0/context_iar.S deleted file mode 100644 index f00d034..0000000 --- a/rt-thread/libcpu/arm/cortex-m0/context_iar.S +++ /dev/null @@ -1,210 +0,0 @@ -;/* -; * Copyright (c) 2006-2018, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2010-01-25 Bernard first version -; * 2012-06-01 aozima set pendsv priority to 0xFF. -; * 2012-08-17 aozima fixed bug: store r8 - r11. -; * 2013-06-18 aozima add restore MSP feature. -; */ - -;/** -; * @addtogroup CORTEX-M0 -; */ -;/*@{*/ - -SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register -NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register -NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) -NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception - - SECTION .text:CODE(2) - THUMB - REQUIRE8 - PRESERVE8 - - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ - EXPORT rt_hw_interrupt_disable -rt_hw_interrupt_disable: - MRS r0, PRIMASK - CPSID I - BX LR - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ - EXPORT rt_hw_interrupt_enable -rt_hw_interrupt_enable: - MSR PRIMASK, r0 - BX LR - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ - EXPORT rt_hw_context_switch_interrupt - EXPORT rt_hw_context_switch -rt_hw_context_switch_interrupt: -rt_hw_context_switch: - ; set rt_thread_switch_interrupt_flag to 1 - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOVS r3, #0x1 - STR r3, [r2] - - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] - -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - BX LR - -; r0 --> switch from thread stack -; r1 --> switch to thread stack -; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack - EXPORT PendSV_Handler -PendSV_Handler: - - ; disable interrupt to protect context switch - MRS r2, PRIMASK - CPSID I - - ; get rt_thread_switch_interrupt_flag - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #0x00 - BEQ pendsv_exit ; pendsv already handled - - ; clear rt_thread_switch_interrupt_flag to 0 - MOVS r1, #0x00 - STR r1, [r0] - - LDR r0, =rt_interrupt_from_thread - LDR r1, [r0] - CMP r1, #0x00 - BEQ switch_to_thread ; skip register save at the first time - - MRS r1, psp ; get from thread stack pointer - - SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11} - LDR r0, [r0] - STR r1, [r0] ; update from thread stack pointer - - STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack - - MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7} - MOV r5, r9 - MOV r6, r10 - MOV r7, r11 - STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack - -switch_to_thread - LDR r1, =rt_interrupt_to_thread - LDR r1, [r1] - LDR r1, [r1] ; load thread stack pointer - - LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack - PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11} - - LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7} - MOV r8, r4 ; mov {r4 - r7} to {r8 - r11} - MOV r9, r5 - MOV r10, r6 - MOV r11, r7 - - POP {r4 - r7} ; pop {r4 - r7} from MSP - - MSR psp, r1 ; update stack pointer - -pendsv_exit - ; restore interrupt - MSR PRIMASK, r2 - - MOVS r0, #0x04 - RSBS r0, r0, #0x00 - BX r0 - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; * this fucntion is used to perform the first thread switch -; */ - EXPORT rt_hw_context_switch_to -rt_hw_context_switch_to: - ; set to thread - LDR r1, =rt_interrupt_to_thread - STR r0, [r1] - - ; set from thread to 0 - LDR r1, =rt_interrupt_from_thread - MOVS r0, #0x0 - STR r0, [r1] - - ; set interrupt flag to 1 - LDR r1, =rt_thread_switch_interrupt_flag - MOVS r0, #1 - STR r0, [r1] - - ; set the PendSV and SysTick exception priority - LDR r0, =NVIC_SHPR3 - LDR r1, =NVIC_PENDSV_PRI - LDR r2, [r0,#0x00] ; read - ORRS r1,r1,r2 ; modify - STR r1, [r0] ; write-back - - ; trigger the PendSV exception (causes context switch) - LDR r0, =NVIC_INT_CTRL - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - NOP - - ; restore MSP - LDR r0, =SCB_VTOR - LDR r0, [r0] - LDR r0, [r0] - NOP - MSR msp, r0 - - ; enable interrupts at processor level - CPSIE I - - ; ensure PendSV exception taken place before subsequent operation - DSB - ISB - - ; never reach here! - -; compatible with old version - EXPORT rt_hw_interrupt_thread_switch -rt_hw_interrupt_thread_switch: - BX lr - - IMPORT rt_hw_hard_fault_exception - EXPORT HardFault_Handler -HardFault_Handler: - - ; get current context - MRS r0, psp ; get fault thread stack pointer - PUSH {lr} - BL rt_hw_hard_fault_exception - POP {pc} - - END diff --git a/rt-thread/libcpu/arm/cortex-m0/context_rvds.S b/rt-thread/libcpu/arm/cortex-m0/context_rvds.S deleted file mode 100644 index 3f1a7e2..0000000 --- a/rt-thread/libcpu/arm/cortex-m0/context_rvds.S +++ /dev/null @@ -1,219 +0,0 @@ -;/* -; * Copyright (c) 2006-2022, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2010-01-25 Bernard first version -; * 2012-06-01 aozima set pendsv priority to 0xFF. -; * 2012-08-17 aozima fixed bug: store r8 - r11. -; * 2013-06-18 aozima add restore MSP feature. -; */ - -;/** -; * @addtogroup CORTEX-M0 -; */ -;/*@{*/ - -SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register -NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register -NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) -NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception - - AREA |.text|, CODE, READONLY, ALIGN=2 - THUMB - REQUIRE8 - PRESERVE8 - - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ -rt_hw_interrupt_disable PROC - EXPORT rt_hw_interrupt_disable - MRS r0, PRIMASK - CPSID I - BX LR - ENDP - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ -rt_hw_interrupt_enable PROC - EXPORT rt_hw_interrupt_enable - MSR PRIMASK, r0 - BX LR - ENDP - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ -rt_hw_context_switch_interrupt - EXPORT rt_hw_context_switch_interrupt -rt_hw_context_switch PROC - EXPORT rt_hw_context_switch - - ; set rt_thread_switch_interrupt_flag to 1 - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOVS r3, #0x01 - STR r3, [r2] - - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] - -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - BX LR - ENDP - -; r0 --> switch from thread stack -; r1 --> switch to thread stack -; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack -PendSV_Handler PROC - EXPORT PendSV_Handler - - ; disable interrupt to protect context switch - MRS r2, PRIMASK - CPSID I - - ; get rt_thread_switch_interrupt_flag - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #0x00 - BEQ pendsv_exit ; pendsv already handled - - ; clear rt_thread_switch_interrupt_flag to 0 - MOVS r1, #0x00 - STR r1, [r0] - - LDR r0, =rt_interrupt_from_thread - LDR r1, [r0] - CMP r1, #0x00 - BEQ switch_to_thread ; skip register save at the first time - - MRS r1, psp ; get from thread stack pointer - - SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11} - LDR r0, [r0] - STR r1, [r0] ; update from thread stack pointer - - STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack - - MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7} - MOV r5, r9 - MOV r6, r10 - MOV r7, r11 - STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack - -switch_to_thread - LDR r1, =rt_interrupt_to_thread - LDR r1, [r1] - LDR r1, [r1] ; load thread stack pointer - - LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack - PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11} - - LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7} - MOV r8, r4 ; mov {r4 - r7} to {r8 - r11} - MOV r9, r5 - MOV r10, r6 - MOV r11, r7 - - POP {r4 - r7} ; pop {r4 - r7} from MSP - - MSR psp, r1 ; update stack pointer - -pendsv_exit - ; restore interrupt - MSR PRIMASK, r2 - - MOVS r0, #0x04 - RSBS r0, r0, #0x00 - BX r0 - ENDP - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; * this fucntion is used to perform the first thread switch -; */ -rt_hw_context_switch_to PROC - EXPORT rt_hw_context_switch_to - ; set to thread - LDR r1, =rt_interrupt_to_thread - STR r0, [r1] - - ; set from thread to 0 - LDR r1, =rt_interrupt_from_thread - MOVS r0, #0x0 - STR r0, [r1] - - ; set interrupt flag to 1 - LDR r1, =rt_thread_switch_interrupt_flag - MOVS r0, #1 - STR r0, [r1] - - ; set the PendSV and SysTick exception priority - LDR r0, =NVIC_SHPR3 - LDR r1, =NVIC_PENDSV_PRI - LDR r2, [r0,#0x00] ; read - ORRS r1,r1,r2 ; modify - STR r1, [r0] ; write-back - - ; trigger the PendSV exception (causes context switch) - LDR r0, =NVIC_INT_CTRL - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - - ; restore MSP - LDR r0, =SCB_VTOR - LDR r0, [r0] - LDR r0, [r0] - MSR msp, r0 - - ; enable interrupts at processor level - CPSIE I - - ; ensure PendSV exception taken place before subsequent operation - DSB - ISB - - ; never reach here! - ENDP - -; compatible with old version -rt_hw_interrupt_thread_switch PROC - EXPORT rt_hw_interrupt_thread_switch - BX lr - ENDP - - IMPORT rt_hw_hard_fault_exception - -HardFault_Handler PROC - EXPORT HardFault_Handler - - ; get current context - MRS r0, psp ; get fault thread stack pointer - PUSH {lr} - BL rt_hw_hard_fault_exception - POP {pc} - ENDP - - ALIGN 4 - - END diff --git a/rt-thread/libcpu/arm/cortex-m0/cpuport.c b/rt-thread/libcpu/arm/cortex-m0/cpuport.c deleted file mode 100644 index af343aa..0000000 --- a/rt-thread/libcpu/arm/cortex-m0/cpuport.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-01-25 Bernard first version - * 2012-05-31 aozima Merge all of the C source code into cpuport.c - * 2012-08-17 aozima fixed bug: store r8 - r11. - * 2012-12-23 aozima stack addr align to 8byte. - */ - -#include - -struct exception_stack_frame -{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r12; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t psr; -}; - -struct stack_frame -{ - /* r4 ~ r7 low register */ - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - - /* r8 ~ r11 high register */ - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t r11; - - struct exception_stack_frame exception_stack_frame; -}; - -/* flag in interrupt handling */ -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, - void *parameter, - rt_uint8_t *stack_addr, - void *texit) -{ - struct stack_frame *stack_frame; - rt_uint8_t *stk; - unsigned long i; - - stk = stack_addr + sizeof(rt_uint32_t); - stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8); - stk -= sizeof(struct stack_frame); - - stack_frame = (struct stack_frame *)stk; - - /* init all register */ - for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++) - { - ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef; - } - - stack_frame->exception_stack_frame.r0 = (unsigned long)parameter; /* r0 : argument */ - stack_frame->exception_stack_frame.r1 = 0; /* r1 */ - stack_frame->exception_stack_frame.r2 = 0; /* r2 */ - stack_frame->exception_stack_frame.r3 = 0; /* r3 */ - stack_frame->exception_stack_frame.r12 = 0; /* r12 */ - stack_frame->exception_stack_frame.lr = (unsigned long)texit; /* lr */ - stack_frame->exception_stack_frame.pc = (unsigned long)tentry; /* entry point, pc */ - stack_frame->exception_stack_frame.psr = 0x01000000L; /* PSR */ - - /* return task's current stack address */ - return stk; -} - -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) -extern long list_thread(void); -#endif -extern rt_thread_t rt_current_thread; -/** - * fault exception handling - */ -void rt_hw_hard_fault_exception(struct exception_stack_frame *contex) -{ - rt_kprintf("psr: 0x%08x\n", contex->psr); - rt_kprintf(" pc: 0x%08x\n", contex->pc); - rt_kprintf(" lr: 0x%08x\n", contex->lr); - rt_kprintf("r12: 0x%08x\n", contex->r12); - rt_kprintf("r03: 0x%08x\n", contex->r3); - rt_kprintf("r02: 0x%08x\n", contex->r2); - rt_kprintf("r01: 0x%08x\n", contex->r1); - rt_kprintf("r00: 0x%08x\n", contex->r0); - - rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name); - -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - - while (1); -} - -#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */ -#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ -#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ -#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ -#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */ -#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */ - -#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ -#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ -#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */ - -/** - * reset CPU - */ -RT_WEAK void rt_hw_cpu_reset(void) -{ - SCB_AIRCR = SCB_RESET_VALUE;//((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |SCB_AIRCR_SYSRESETREQ_Msk); -} diff --git a/rt-thread/libcpu/arm/cortex-m23/SConscript b/rt-thread/libcpu/arm/cortex-m23/SConscript deleted file mode 100644 index b259a94..0000000 --- a/rt-thread/libcpu/arm/cortex-m23/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/cortex-m23/context_gcc.S b/rt-thread/libcpu/arm/cortex-m23/context_gcc.S deleted file mode 100644 index abec76f..0000000 --- a/rt-thread/libcpu/arm/cortex-m23/context_gcc.S +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-01-25 Bernard first version - * 2012-06-01 aozima set pendsv priority to 0xFF. - * 2012-08-17 aozima fixed bug: store r8 - r11. - * 2013-02-20 aozima port to gcc. - * 2013-06-18 aozima add restore MSP feature. - * 2013-11-04 bright fixed hardfault bug for gcc. - * 2019-03-31 xuzhuoyi port to Cortex-M23. - */ - - .cpu cortex-m23 - .fpu softvfp - .syntax unified - .thumb - .text - - .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ - .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ - .equ NVIC_SHPR3, 0xE000ED20 /* system priority register (3) */ - .equ NVIC_PENDSV_PRI, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */ - .equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ - -/* - * rt_base_t rt_hw_interrupt_disable(); - */ - .global rt_hw_interrupt_disable - .type rt_hw_interrupt_disable, %function -rt_hw_interrupt_disable: - MRS R0, PRIMASK - CPSID I - BX LR - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ - .global rt_hw_interrupt_enable - .type rt_hw_interrupt_enable, %function -rt_hw_interrupt_enable: - MSR PRIMASK, R0 - BX LR - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * R0 --> from - * R1 --> to - */ - .global rt_hw_context_switch_interrupt - .type rt_hw_context_switch_interrupt, %function - .global rt_hw_context_switch - .type rt_hw_context_switch, %function -rt_hw_context_switch_interrupt: -rt_hw_context_switch: - /* set rt_thread_switch_interrupt_flag to 1 */ - LDR R2, =rt_thread_switch_interrupt_flag - LDR R3, [R2] - CMP R3, #1 - BEQ _reswitch - MOVS R3, #1 - STR R3, [R2] - - LDR R2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - STR R0, [R2] - -_reswitch: - LDR R2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - STR R1, [R2] - - LDR R0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ - LDR R1, =NVIC_PENDSVSET - STR R1, [R0] - BX LR - -/* R0 --> switch from thread stack - * R1 --> switch to thread stack - * psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack - */ - .global PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - /* disable interrupt to protect context switch */ - MRS R2, PRIMASK - CPSID I - - /* get rt_thread_switch_interrupt_flag */ - LDR R0, =rt_thread_switch_interrupt_flag - LDR R1, [R0] - CMP R1, #0x00 - BEQ pendsv_exit /* pendsv already handled */ - - /* clear rt_thread_switch_interrupt_flag to 0 */ - MOVS R1, #0 - STR R1, [R0] - - LDR R0, =rt_interrupt_from_thread - LDR R1, [R0] - CMP R1, #0x00 - BEQ switch_to_thread /* skip register save at the first time */ - - MRS R1, PSP /* get from thread stack pointer */ - - SUBS R1, R1, #0x20 /* space for {R4 - R7} and {R8 - R11} */ - LDR R0, [R0] - STR R1, [R0] /* update from thread stack pointer */ - - STMIA R1!, {R4 - R7} /* push thread {R4 - R7} register to thread stack */ - - MOV R4, R8 /* mov thread {R8 - R11} to {R4 - R7} */ - MOV R5, R9 - MOV R6, R10 - MOV R7, R11 - STMIA R1!, {R4 - R7} /* push thread {R8 - R11} high register to thread stack */ -switch_to_thread: - LDR R1, =rt_interrupt_to_thread - LDR R1, [R1] - LDR R1, [R1] /* load thread stack pointer */ - - LDMIA R1!, {R4 - R7} /* pop thread {R4 - R7} register from thread stack */ - PUSH {R4 - R7} /* push {R4 - R7} to MSP for copy {R8 - R11} */ - - LDMIA R1!, {R4 - R7} /* pop thread {R8 - R11} high register from thread stack to {R4 - R7} */ - MOV R8, R4 /* mov {R4 - R7} to {R8 - R11} */ - MOV R9, R5 - MOV R10, R6 - MOV R11, R7 - - POP {R4 - R7} /* pop {R4 - R7} from MSP */ - - MSR PSP, R1 /* update stack pointer */ - -pendsv_exit: - /* restore interrupt */ - MSR PRIMASK, R2 - - MOVS R0, #0x03 - RSBS R0, R0, #0x00 - BX R0 -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * R0 --> to - */ - .global rt_hw_context_switch_to - .type rt_hw_context_switch_to, %function -rt_hw_context_switch_to: - LDR R1, =rt_interrupt_to_thread - STR R0, [R1] - - /* set from thread to 0 */ - LDR R1, =rt_interrupt_from_thread - MOVS R0, #0 - STR R0, [R1] - - /* set interrupt flag to 1 */ - LDR R1, =rt_thread_switch_interrupt_flag - MOVS R0, #1 - STR R0, [R1] - - /* set the PendSV and SysTick exception priority */ - LDR R0, =NVIC_SHPR3 - LDR R1, =NVIC_PENDSV_PRI - LDR R2, [R0,#0x00] /* read */ - ORRS R1, R1, R2 /* modify */ - STR R1, [R0] /* write-back */ - - LDR R0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ - LDR R1, =NVIC_PENDSVSET - STR R1, [R0] - NOP - /* restore MSP */ - LDR R0, =SCB_VTOR - LDR R0, [R0] - LDR R0, [R0] - NOP - MSR MSP, R0 - - /* enable interrupts at processor level */ - CPSIE I - - /* ensure PendSV exception taken place before subsequent operation */ - DSB - ISB - - /* never reach here! */ - -/* compatible with old version */ - .global rt_hw_interrupt_thread_switch - .type rt_hw_interrupt_thread_switch, %function -rt_hw_interrupt_thread_switch: - BX LR - NOP - - .global HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - /* get current context */ - MRS R0, PSP /* get fault thread stack pointer */ - PUSH {LR} - BL rt_hw_hard_fault_exception - POP {PC} - - -/* - * rt_uint32_t rt_hw_interrupt_check(void); - * R0 --> state - */ - .global rt_hw_interrupt_check - .type rt_hw_interrupt_check, %function -rt_hw_interrupt_check: - MRS R0, IPSR - BX LR diff --git a/rt-thread/libcpu/arm/cortex-m23/context_iar.S b/rt-thread/libcpu/arm/cortex-m23/context_iar.S deleted file mode 100644 index 7600ef3..0000000 --- a/rt-thread/libcpu/arm/cortex-m23/context_iar.S +++ /dev/null @@ -1,211 +0,0 @@ -;/* -; * Copyright (c) 2006-2019, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2010-01-25 Bernard first version -; * 2012-06-01 aozima set pendsv priority to 0xFF. -; * 2012-08-17 aozima fixed bug: store r8 - r11. -; * 2013-06-18 aozima add restore MSP feature. -; * 2019-03-31 xuzhuoyi port to Cortex-M23. -; */ - -;/** -; * @addtogroup CORTEX-M23 -; */ -;/*@{*/ - -SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register -NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register -NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) -NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception - - SECTION .text:CODE(2) - THUMB - REQUIRE8 - PRESERVE8 - - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ - EXPORT rt_hw_interrupt_disable -rt_hw_interrupt_disable: - MRS r0, PRIMASK - CPSID I - BX LR - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ - EXPORT rt_hw_interrupt_enable -rt_hw_interrupt_enable: - MSR PRIMASK, r0 - BX LR - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ - EXPORT rt_hw_context_switch_interrupt - EXPORT rt_hw_context_switch -rt_hw_context_switch_interrupt: -rt_hw_context_switch: - ; set rt_thread_switch_interrupt_flag to 1 - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOVS r3, #0x1 - STR r3, [r2] - - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] - -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - BX LR - -; r0 --> switch from thread stack -; r1 --> switch to thread stack -; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack - EXPORT PendSV_Handler -PendSV_Handler: - - ; disable interrupt to protect context switch - MRS r2, PRIMASK - CPSID I - - ; get rt_thread_switch_interrupt_flag - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #0x00 - BEQ pendsv_exit ; pendsv already handled - - ; clear rt_thread_switch_interrupt_flag to 0 - MOVS r1, #0x00 - STR r1, [r0] - - LDR r0, =rt_interrupt_from_thread - LDR r1, [r0] - CMP r1, #0x00 - BEQ switch_to_thread ; skip register save at the first time - - MRS r1, psp ; get from thread stack pointer - - SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11} - LDR r0, [r0] - STR r1, [r0] ; update from thread stack pointer - - STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack - - MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7} - MOV r5, r9 - MOV r6, r10 - MOV r7, r11 - STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack - -switch_to_thread - LDR r1, =rt_interrupt_to_thread - LDR r1, [r1] - LDR r1, [r1] ; load thread stack pointer - - LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack - PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11} - - LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7} - MOV r8, r4 ; mov {r4 - r7} to {r8 - r11} - MOV r9, r5 - MOV r10, r6 - MOV r11, r7 - - POP {r4 - r7} ; pop {r4 - r7} from MSP - - MSR psp, r1 ; update stack pointer - -pendsv_exit - ; restore interrupt - MSR PRIMASK, r2 - - MOVS r0, #0x03 - RSBS r0, r0, #0x00 - BX r0 - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; * this fucntion is used to perform the first thread switch -; */ - EXPORT rt_hw_context_switch_to -rt_hw_context_switch_to: - ; set to thread - LDR r1, =rt_interrupt_to_thread - STR r0, [r1] - - ; set from thread to 0 - LDR r1, =rt_interrupt_from_thread - MOVS r0, #0x0 - STR r0, [r1] - - ; set interrupt flag to 1 - LDR r1, =rt_thread_switch_interrupt_flag - MOVS r0, #1 - STR r0, [r1] - - ; set the PendSV and SysTick exception priority - LDR r0, =NVIC_SHPR3 - LDR r1, =NVIC_PENDSV_PRI - LDR r2, [r0,#0x00] ; read - ORRS r1,r1,r2 ; modify - STR r1, [r0] ; write-back - - ; trigger the PendSV exception (causes context switch) - LDR r0, =NVIC_INT_CTRL - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - NOP - - ; restore MSP - LDR r0, =SCB_VTOR - LDR r0, [r0] - LDR r0, [r0] - NOP - MSR msp, r0 - - ; enable interrupts at processor level - CPSIE I - - ; ensure PendSV exception taken place before subsequent operation - DSB - ISB - - ; never reach here! - -; compatible with old version - EXPORT rt_hw_interrupt_thread_switch -rt_hw_interrupt_thread_switch: - BX lr - - IMPORT rt_hw_hard_fault_exception - EXPORT HardFault_Handler -HardFault_Handler: - - ; get current context - MRS r0, psp ; get fault thread stack pointer - PUSH {lr} - BL rt_hw_hard_fault_exception - POP {pc} - - END diff --git a/rt-thread/libcpu/arm/cortex-m23/context_rvds.S b/rt-thread/libcpu/arm/cortex-m23/context_rvds.S deleted file mode 100644 index 38c3c36..0000000 --- a/rt-thread/libcpu/arm/cortex-m23/context_rvds.S +++ /dev/null @@ -1,220 +0,0 @@ -;/* -; * Copyright (c) 2006-2022, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2010-01-25 Bernard first version -; * 2012-06-01 aozima set pendsv priority to 0xFF. -; * 2012-08-17 aozima fixed bug: store r8 - r11. -; * 2013-06-18 aozima add restore MSP feature. -; * 2019-03-31 xuzhuoyi port to Cortex-M23. -; */ - -;/** -; * @addtogroup CORTEX-M23 -; */ -;/*@{*/ - -SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register -NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register -NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) -NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception - - AREA |.text|, CODE, READONLY, ALIGN=2 - THUMB - REQUIRE8 - PRESERVE8 - - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ -rt_hw_interrupt_disable PROC - EXPORT rt_hw_interrupt_disable - MRS r0, PRIMASK - CPSID I - BX LR - ENDP - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ -rt_hw_interrupt_enable PROC - EXPORT rt_hw_interrupt_enable - MSR PRIMASK, r0 - BX LR - ENDP - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ -rt_hw_context_switch_interrupt - EXPORT rt_hw_context_switch_interrupt -rt_hw_context_switch PROC - EXPORT rt_hw_context_switch - - ; set rt_thread_switch_interrupt_flag to 1 - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOVS r3, #0x01 - STR r3, [r2] - - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] - -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - BX LR - ENDP - -; r0 --> switch from thread stack -; r1 --> switch to thread stack -; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack -PendSV_Handler PROC - EXPORT PendSV_Handler - - ; disable interrupt to protect context switch - MRS r2, PRIMASK - CPSID I - - ; get rt_thread_switch_interrupt_flag - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #0x00 - BEQ pendsv_exit ; pendsv already handled - - ; clear rt_thread_switch_interrupt_flag to 0 - MOVS r1, #0x00 - STR r1, [r0] - - LDR r0, =rt_interrupt_from_thread - LDR r1, [r0] - CMP r1, #0x00 - BEQ switch_to_thread ; skip register save at the first time - - MRS r1, psp ; get from thread stack pointer - - SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11} - LDR r0, [r0] - STR r1, [r0] ; update from thread stack pointer - - STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack - - MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7} - MOV r5, r9 - MOV r6, r10 - MOV r7, r11 - STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack - -switch_to_thread - LDR r1, =rt_interrupt_to_thread - LDR r1, [r1] - LDR r1, [r1] ; load thread stack pointer - - LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack - PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11} - - LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7} - MOV r8, r4 ; mov {r4 - r7} to {r8 - r11} - MOV r9, r5 - MOV r10, r6 - MOV r11, r7 - - POP {r4 - r7} ; pop {r4 - r7} from MSP - - MSR psp, r1 ; update stack pointer - -pendsv_exit - ; restore interrupt - MSR PRIMASK, r2 - - MOVS r0, #0x03 - RSBS r0, r0, #0x00 - BX r0 - ENDP - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; * this fucntion is used to perform the first thread switch -; */ -rt_hw_context_switch_to PROC - EXPORT rt_hw_context_switch_to - ; set to thread - LDR r1, =rt_interrupt_to_thread - STR r0, [r1] - - ; set from thread to 0 - LDR r1, =rt_interrupt_from_thread - MOVS r0, #0x0 - STR r0, [r1] - - ; set interrupt flag to 1 - LDR r1, =rt_thread_switch_interrupt_flag - MOVS r0, #1 - STR r0, [r1] - - ; set the PendSV and SysTick exception priority - LDR r0, =NVIC_SHPR3 - LDR r1, =NVIC_PENDSV_PRI - LDR r2, [r0,#0x00] ; read - ORRS r1,r1,r2 ; modify - STR r1, [r0] ; write-back - - ; trigger the PendSV exception (causes context switch) - LDR r0, =NVIC_INT_CTRL - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - - ; restore MSP - LDR r0, =SCB_VTOR - LDR r0, [r0] - LDR r0, [r0] - MSR msp, r0 - - ; enable interrupts at processor level - CPSIE I - - ; ensure PendSV exception taken place before subsequent operation - DSB - ISB - - ; never reach here! - ENDP - -; compatible with old version -rt_hw_interrupt_thread_switch PROC - EXPORT rt_hw_interrupt_thread_switch - BX lr - ENDP - - IMPORT rt_hw_hard_fault_exception - -HardFault_Handler PROC - EXPORT HardFault_Handler - - ; get current context - MRS r0, psp ; get fault thread stack pointer - PUSH {lr} - BL rt_hw_hard_fault_exception - POP {pc} - ENDP - - ALIGN 4 - - END diff --git a/rt-thread/libcpu/arm/cortex-m23/cpuport.c b/rt-thread/libcpu/arm/cortex-m23/cpuport.c deleted file mode 100644 index a3b18f5..0000000 --- a/rt-thread/libcpu/arm/cortex-m23/cpuport.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-01-25 Bernard first version - * 2012-05-31 aozima Merge all of the C source code into cpuport.c - * 2012-08-17 aozima fixed bug: store r8 - r11. - * 2012-12-23 aozima stack addr align to 8byte. - * 2019-03-31 xuzhuoyi port to Cortex-M23. - */ - -#include - -struct exception_stack_frame -{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r12; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t psr; -}; - -struct stack_frame -{ - /* r4 ~ r7 low register */ - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - - /* r8 ~ r11 high register */ - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t r11; - - struct exception_stack_frame exception_stack_frame; -}; - -/* flag in interrupt handling */ -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, - void *parameter, - rt_uint8_t *stack_addr, - void *texit) -{ - struct stack_frame *stack_frame; - rt_uint8_t *stk; - unsigned long i; - - stk = stack_addr + sizeof(rt_uint32_t); - stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8); - stk -= sizeof(struct stack_frame); - - stack_frame = (struct stack_frame *)stk; - - /* init all register */ - for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++) - { - ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef; - } - - stack_frame->exception_stack_frame.r0 = (unsigned long)parameter; /* r0 : argument */ - stack_frame->exception_stack_frame.r1 = 0; /* r1 */ - stack_frame->exception_stack_frame.r2 = 0; /* r2 */ - stack_frame->exception_stack_frame.r3 = 0; /* r3 */ - stack_frame->exception_stack_frame.r12 = 0; /* r12 */ - stack_frame->exception_stack_frame.lr = (unsigned long)texit; /* lr */ - stack_frame->exception_stack_frame.pc = (unsigned long)tentry; /* entry point, pc */ - stack_frame->exception_stack_frame.psr = 0x01000000L; /* PSR */ - - /* return task's current stack address */ - return stk; -} - -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) -extern long list_thread(void); -#endif -extern rt_thread_t rt_current_thread; -/** - * fault exception handling - */ -void rt_hw_hard_fault_exception(struct exception_stack_frame *contex) -{ - rt_kprintf("psr: 0x%08x\n", contex->psr); - rt_kprintf(" pc: 0x%08x\n", contex->pc); - rt_kprintf(" lr: 0x%08x\n", contex->lr); - rt_kprintf("r12: 0x%08x\n", contex->r12); - rt_kprintf("r03: 0x%08x\n", contex->r3); - rt_kprintf("r02: 0x%08x\n", contex->r2); - rt_kprintf("r01: 0x%08x\n", contex->r1); - rt_kprintf("r00: 0x%08x\n", contex->r0); - - rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name); - -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - - while (1); -} - -#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */ -#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ -#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ -#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ -#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED00) /* Reset control Address Register */ -#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */ - -#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ -#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ -#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */ - -/** - * reset CPU - */ -RT_WEAK void rt_hw_cpu_reset(void) -{ - SCB_AIRCR = SCB_RESET_VALUE;//((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |SCB_AIRCR_SYSRESETREQ_Msk); -} diff --git a/rt-thread/libcpu/arm/cortex-m3/SConscript b/rt-thread/libcpu/arm/cortex-m3/SConscript deleted file mode 100644 index b259a94..0000000 --- a/rt-thread/libcpu/arm/cortex-m3/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/cortex-m3/context_gcc.S b/rt-thread/libcpu/arm/cortex-m3/context_gcc.S deleted file mode 100644 index 1f4e106..0000000 --- a/rt-thread/libcpu/arm/cortex-m3/context_gcc.S +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-10-11 Bernard First version - * 2010-12-29 onelife Modify for EFM32 - * 2011-06-17 onelife Merge all of the assembly source code into context_gcc.S - * 2011-07-12 onelife Add interrupt context check function - * 2013-06-18 aozima add restore MSP feature. - * 2013-07-09 aozima enhancement hard fault exception handler. - */ - - .cpu cortex-m3 - .fpu softvfp - .syntax unified - .thumb - .text - - .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ - .equ ICSR, 0xE000ED04 /* interrupt control state register */ - .equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */ - - .equ SHPR3, 0xE000ED20 /* system priority register (3) */ - .equ PENDSV_PRI_LOWEST, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */ - -/* - * rt_base_t rt_hw_interrupt_disable(); - */ - .global rt_hw_interrupt_disable - .type rt_hw_interrupt_disable, %function -rt_hw_interrupt_disable: - MRS R0, PRIMASK - CPSID I - BX LR - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ - .global rt_hw_interrupt_enable - .type rt_hw_interrupt_enable, %function -rt_hw_interrupt_enable: - MSR PRIMASK, R0 - BX LR - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * R0 --> from - * R1 --> to - */ - .global rt_hw_context_switch_interrupt - .type rt_hw_context_switch_interrupt, %function - .global rt_hw_context_switch - .type rt_hw_context_switch, %function -rt_hw_context_switch_interrupt: -rt_hw_context_switch: - /* set rt_thread_switch_interrupt_flag to 1 */ - LDR R2, =rt_thread_switch_interrupt_flag - LDR R3, [R2] - CMP R3, #1 - BEQ _reswitch - MOV R3, #1 - STR R3, [R2] - - LDR R2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - STR R0, [R2] - -_reswitch: - LDR R2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - STR R1, [R2] - - LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */ - LDR R1, =PENDSVSET_BIT - STR R1, [R0] - BX LR - -/* R0 --> switch from thread stack - * R1 --> switch to thread stack - * psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack - */ - .global PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - /* disable interrupt to protect context switch */ - MRS R2, PRIMASK - CPSID I - - /* get rt_thread_switch_interrupt_flag */ - LDR R0, =rt_thread_switch_interrupt_flag - LDR R1, [R0] - CBZ R1, pendsv_exit /* pendsv already handled */ - - /* clear rt_thread_switch_interrupt_flag to 0 */ - MOV R1, #0 - STR R1, [R0] - - LDR R0, =rt_interrupt_from_thread - LDR R1, [R0] - CBZ R1, switch_to_thread /* skip register save at the first time */ - - MRS R1, PSP /* get from thread stack pointer */ - STMFD R1!, {R4 - R11} /* push R4 - R11 register */ - LDR R0, [R0] - STR R1, [R0] /* update from thread stack pointer */ - -switch_to_thread: - LDR R1, =rt_interrupt_to_thread - LDR R1, [R1] - LDR R1, [R1] /* load thread stack pointer */ - - LDMFD R1!, {R4 - R11} /* pop R4 - R11 register */ - MSR PSP, R1 /* update stack pointer */ - -pendsv_exit: - /* restore interrupt */ - MSR PRIMASK, R2 - - ORR LR, LR, #0x04 - BX LR - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * R0 --> to - */ - .global rt_hw_context_switch_to - .type rt_hw_context_switch_to, %function -rt_hw_context_switch_to: - LDR R1, =rt_interrupt_to_thread - STR R0, [R1] - - /* set from thread to 0 */ - LDR R1, =rt_interrupt_from_thread - MOV R0, #0 - STR R0, [R1] - - /* set interrupt flag to 1 */ - LDR R1, =rt_thread_switch_interrupt_flag - MOV R0, #1 - STR R0, [R1] - - /* set the PendSV and SysTick exception priority */ - LDR R0, =SHPR3 - LDR R1, =PENDSV_PRI_LOWEST - LDR.W R2, [R0,#0] /* read */ - ORR R1, R1, R2 /* modify */ - STR R1, [R0] /* write-back */ - - LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */ - LDR R1, =PENDSVSET_BIT - STR R1, [R0] - - /* restore MSP */ - LDR r0, =SCB_VTOR - LDR r0, [r0] - LDR r0, [r0] - NOP - MSR msp, r0 - - /* enable interrupts at processor level */ - CPSIE F - CPSIE I - - /* ensure PendSV exception taken place before subsequent operation */ - DSB - ISB - - /* never reach here! */ - -/* compatible with old version */ - .global rt_hw_interrupt_thread_switch - .type rt_hw_interrupt_thread_switch, %function -rt_hw_interrupt_thread_switch: - BX LR - NOP - - .global HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - /* get current context */ - MRS r0, msp /* get fault context from handler. */ - TST lr, #0x04 /* if(!EXC_RETURN[2]) */ - BEQ _get_sp_done - MRS r0, psp /* get fault context from thread. */ -_get_sp_done: - - STMFD r0!, {r4 - r11} /* push r4 - r11 register */ - STMFD r0!, {lr} /* push exec_return register */ - - TST lr, #0x04 /* if(!EXC_RETURN[2]) */ - BEQ _update_msp - MSR psp, r0 /* update stack pointer to PSP. */ - B _update_done -_update_msp: - MSR msp, r0 /* update stack pointer to MSP. */ -_update_done: - - PUSH {LR} - BL rt_hw_hard_fault_exception - POP {LR} - - ORR LR, LR, #0x04 - BX LR - -/* - * rt_uint32_t rt_hw_interrupt_check(void); - * R0 --> state - */ - .global rt_hw_interrupt_check - .type rt_hw_interrupt_check, %function -rt_hw_interrupt_check: - MRS R0, IPSR - BX LR diff --git a/rt-thread/libcpu/arm/cortex-m3/context_iar.S b/rt-thread/libcpu/arm/cortex-m3/context_iar.S deleted file mode 100644 index 5173652..0000000 --- a/rt-thread/libcpu/arm/cortex-m3/context_iar.S +++ /dev/null @@ -1,206 +0,0 @@ -;/* -; * Copyright (c) 2006-2018, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2009-01-17 Bernard first version -; * 2009-09-27 Bernard add protect when contex switch occurs -; * 2013-06-18 aozima add restore MSP feature. -; * 2013-07-09 aozima enhancement hard fault exception handler. -; */ - -;/** -; * @addtogroup cortex-m3 -; */ -;/*@{*/ - -SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register -NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register -NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) -NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception - - SECTION .text:CODE(2) - THUMB - REQUIRE8 - PRESERVE8 - - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ - EXPORT rt_hw_interrupt_disable -rt_hw_interrupt_disable: - MRS r0, PRIMASK - CPSID I - BX LR - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ - EXPORT rt_hw_interrupt_enable -rt_hw_interrupt_enable: - MSR PRIMASK, r0 - BX LR - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ - EXPORT rt_hw_context_switch_interrupt - EXPORT rt_hw_context_switch -rt_hw_context_switch_interrupt: -rt_hw_context_switch: - ; set rt_thread_switch_interrupt_flag to 1 - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 - STR r3, [r2] - - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] - -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - BX LR - -; r0 --> switch from thread stack -; r1 --> switch to thread stack -; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack - EXPORT PendSV_Handler -PendSV_Handler: - - ; disable interrupt to protect context switch - MRS r2, PRIMASK - CPSID I - - ; get rt_thread_switch_interrupt_flag - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CBZ r1, pendsv_exit ; pendsv already handled - - ; clear rt_thread_switch_interrupt_flag to 0 - MOV r1, #0x00 - STR r1, [r0] - - LDR r0, =rt_interrupt_from_thread - LDR r1, [r0] - CBZ r1, switch_to_thread ; skip register save at the first time - - MRS r1, psp ; get from thread stack pointer - STMFD r1!, {r4 - r11} ; push r4 - r11 register - LDR r0, [r0] - STR r1, [r0] ; update from thread stack pointer - -switch_to_thread - LDR r1, =rt_interrupt_to_thread - LDR r1, [r1] - LDR r1, [r1] ; load thread stack pointer - - LDMFD r1!, {r4 - r11} ; pop r4 - r11 register - MSR psp, r1 ; update stack pointer - -pendsv_exit - ; restore interrupt - MSR PRIMASK, r2 - - ORR lr, lr, #0x04 - BX lr - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; */ - EXPORT rt_hw_context_switch_to -rt_hw_context_switch_to: - LDR r1, =rt_interrupt_to_thread - STR r0, [r1] - - ; set from thread to 0 - LDR r1, =rt_interrupt_from_thread - MOV r0, #0x0 - STR r0, [r1] - - ; set interrupt flag to 1 - LDR r1, =rt_thread_switch_interrupt_flag - MOV r0, #1 - STR r0, [r1] - - ; set the PendSV and SysTick exception priority - LDR r0, =NVIC_SYSPRI2 - LDR r1, =NVIC_PENDSV_PRI - LDR.W r2, [r0,#0x00] ; read - ORR r1,r1,r2 ; modify - STR r1, [r0] ; write-back - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - - ; restore MSP - LDR r0, =SCB_VTOR - LDR r0, [r0] - LDR r0, [r0] - NOP - MSR msp, r0 - - ; enable interrupts at processor level - CPSIE F - CPSIE I - - ; ensure PendSV exception taken place before subsequent operation - DSB - ISB - - ; never reach here! - -; compatible with old version - EXPORT rt_hw_interrupt_thread_switch -rt_hw_interrupt_thread_switch: - BX lr - - IMPORT rt_hw_hard_fault_exception - EXPORT HardFault_Handler -HardFault_Handler: - - ; get current context - MRS r0, msp ; get fault context from handler. - TST lr, #0x04 ; if(!EXC_RETURN[2]) - BEQ _get_sp_done - MRS r0, psp ; get fault context from thread. -_get_sp_done - - STMFD r0!, {r4 - r11} ; push r4 - r11 register - ;STMFD r0!, {lr} ; push exec_return register - SUB r0, r0, #0x04 - STR lr, [r0] - - TST lr, #0x04 ; if(!EXC_RETURN[2]) - BEQ _update_msp - MSR psp, r0 ; update stack pointer to PSP. - B _update_done -_update_msp - MSR msp, r0 ; update stack pointer to MSP. -_update_done - - PUSH {lr} - BL rt_hw_hard_fault_exception - POP {lr} - - ORR lr, lr, #0x04 - BX lr - - END diff --git a/rt-thread/libcpu/arm/cortex-m3/context_rvds.S b/rt-thread/libcpu/arm/cortex-m3/context_rvds.S deleted file mode 100644 index cdf300b..0000000 --- a/rt-thread/libcpu/arm/cortex-m3/context_rvds.S +++ /dev/null @@ -1,211 +0,0 @@ -;/* -; * Copyright (c) 2006-2022, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2009-01-17 Bernard first version -; * 2013-06-18 aozima add restore MSP feature. -; * 2013-07-09 aozima enhancement hard fault exception handler. -; */ - -;/** -; * @addtogroup CORTEX-M3 -; */ -;/*@{*/ - -SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register -NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register -NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) -NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception - - AREA |.text|, CODE, READONLY, ALIGN=2 - THUMB - REQUIRE8 - PRESERVE8 - - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ -rt_hw_interrupt_disable PROC - EXPORT rt_hw_interrupt_disable - MRS r0, PRIMASK - CPSID I - BX LR - ENDP - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ -rt_hw_interrupt_enable PROC - EXPORT rt_hw_interrupt_enable - MSR PRIMASK, r0 - BX LR - ENDP - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ -rt_hw_context_switch_interrupt - EXPORT rt_hw_context_switch_interrupt -rt_hw_context_switch PROC - EXPORT rt_hw_context_switch - - ; set rt_thread_switch_interrupt_flag to 1 - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 - STR r3, [r2] - - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] - -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - BX LR - ENDP - -; r0 --> switch from thread stack -; r1 --> switch to thread stack -; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack -PendSV_Handler PROC - EXPORT PendSV_Handler - - ; disable interrupt to protect context switch - MRS r2, PRIMASK - CPSID I - - ; get rt_thread_switch_interrupt_flag - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CBZ r1, pendsv_exit ; pendsv already handled - - ; clear rt_thread_switch_interrupt_flag to 0 - MOV r1, #0x00 - STR r1, [r0] - - LDR r0, =rt_interrupt_from_thread - LDR r1, [r0] - CBZ r1, switch_to_thread ; skip register save at the first time - - MRS r1, psp ; get from thread stack pointer - STMFD r1!, {r4 - r11} ; push r4 - r11 register - LDR r0, [r0] - STR r1, [r0] ; update from thread stack pointer - -switch_to_thread - LDR r1, =rt_interrupt_to_thread - LDR r1, [r1] - LDR r1, [r1] ; load thread stack pointer - - LDMFD r1!, {r4 - r11} ; pop r4 - r11 register - MSR psp, r1 ; update stack pointer - -pendsv_exit - ; restore interrupt - MSR PRIMASK, r2 - - ORR lr, lr, #0x04 - BX lr - ENDP - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; * this fucntion is used to perform the first thread switch -; */ -rt_hw_context_switch_to PROC - EXPORT rt_hw_context_switch_to - ; set to thread - LDR r1, =rt_interrupt_to_thread - STR r0, [r1] - - ; set from thread to 0 - LDR r1, =rt_interrupt_from_thread - MOV r0, #0x0 - STR r0, [r1] - - ; set interrupt flag to 1 - LDR r1, =rt_thread_switch_interrupt_flag - MOV r0, #1 - STR r0, [r1] - - ; set the PendSV and SysTick exception priority - LDR r0, =NVIC_SYSPRI2 - LDR r1, =NVIC_PENDSV_PRI - LDR.W r2, [r0,#0x00] ; read - ORR r1,r1,r2 ; modify - STR r1, [r0] ; write-back - - ; trigger the PendSV exception (causes context switch) - LDR r0, =NVIC_INT_CTRL - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - - ; restore MSP - LDR r0, =SCB_VTOR - LDR r0, [r0] - LDR r0, [r0] - MSR msp, r0 - - ; enable interrupts at processor level - CPSIE F - CPSIE I - - ; ensure PendSV exception taken place before subsequent operation - DSB - ISB - - ; never reach here! - ENDP - -; compatible with old version -rt_hw_interrupt_thread_switch PROC - EXPORT rt_hw_interrupt_thread_switch - BX lr - ENDP - - IMPORT rt_hw_hard_fault_exception - EXPORT HardFault_Handler -HardFault_Handler PROC - - ; get current context - TST lr, #0x04 ; if(!EXC_RETURN[2]) - ITE EQ - MRSEQ r0, msp ; [2]=0 ==> Z=1, get fault context from handler. - MRSNE r0, psp ; [2]=1 ==> Z=0, get fault context from thread. - - STMFD r0!, {r4 - r11} ; push r4 - r11 register - STMFD r0!, {lr} ; push exec_return register - - TST lr, #0x04 ; if(!EXC_RETURN[2]) - ITE EQ - MSREQ msp, r0 ; [2]=0 ==> Z=1, update stack pointer to MSP. - MSRNE psp, r0 ; [2]=1 ==> Z=0, update stack pointer to PSP. - - PUSH {lr} - BL rt_hw_hard_fault_exception - POP {lr} - - ORR lr, lr, #0x04 - BX lr - ENDP - - ALIGN 4 - - END diff --git a/rt-thread/libcpu/arm/cortex-m3/cpuport.c b/rt-thread/libcpu/arm/cortex-m3/cpuport.c deleted file mode 100644 index 0f09930..0000000 --- a/rt-thread/libcpu/arm/cortex-m3/cpuport.c +++ /dev/null @@ -1,424 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard first version - * 2011-02-14 onelife Modify for EFM32 - * 2011-06-17 onelife Merge all of the C source code into cpuport.c - * 2012-12-23 aozima stack addr align to 8byte. - * 2012-12-29 Bernard Add exception hook. - * 2013-07-09 aozima enhancement hard fault exception handler. - * 2019-07-03 yangjie add __rt_ffs() for armclang. - */ - -#include - -struct exception_stack_frame -{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r12; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t psr; -}; - -struct stack_frame -{ - /* r4 ~ r11 register */ - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t r11; - - struct exception_stack_frame exception_stack_frame; -}; - -/* flag in interrupt handling */ -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; -/* exception hook */ -static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL; - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, - void *parameter, - rt_uint8_t *stack_addr, - void *texit) -{ - struct stack_frame *stack_frame; - rt_uint8_t *stk; - unsigned long i; - - stk = stack_addr + sizeof(rt_uint32_t); - stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8); - stk -= sizeof(struct stack_frame); - - stack_frame = (struct stack_frame *)stk; - - /* init all register */ - for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++) - { - ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef; - } - - stack_frame->exception_stack_frame.r0 = (unsigned long)parameter; /* r0 : argument */ - stack_frame->exception_stack_frame.r1 = 0; /* r1 */ - stack_frame->exception_stack_frame.r2 = 0; /* r2 */ - stack_frame->exception_stack_frame.r3 = 0; /* r3 */ - stack_frame->exception_stack_frame.r12 = 0; /* r12 */ - stack_frame->exception_stack_frame.lr = (unsigned long)texit; /* lr */ - stack_frame->exception_stack_frame.pc = (unsigned long)tentry; /* entry point, pc */ - stack_frame->exception_stack_frame.psr = 0x01000000L; /* PSR */ - - /* return task's current stack address */ - return stk; -} - -/** - * This function set the hook, which is invoked on fault exception handling. - * - * @param exception_handle the exception handling hook function. - */ -void rt_hw_exception_install(rt_err_t (*exception_handle)(void* context)) -{ - rt_exception_hook = exception_handle; -} - -#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */ -#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ -#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ -#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ -#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */ -#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */ - -#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ -#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ -#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */ - -#ifdef RT_USING_FINSH -static void usage_fault_track(void) -{ - rt_kprintf("usage fault:\n"); - rt_kprintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR); - - if(SCB_CFSR_UFSR & (1<<0)) - { - /* [0]:UNDEFINSTR */ - rt_kprintf("UNDEFINSTR "); - } - - if(SCB_CFSR_UFSR & (1<<1)) - { - /* [1]:INVSTATE */ - rt_kprintf("INVSTATE "); - } - - if(SCB_CFSR_UFSR & (1<<2)) - { - /* [2]:INVPC */ - rt_kprintf("INVPC "); - } - - if(SCB_CFSR_UFSR & (1<<3)) - { - /* [3]:NOCP */ - rt_kprintf("NOCP "); - } - - if(SCB_CFSR_UFSR & (1<<8)) - { - /* [8]:UNALIGNED */ - rt_kprintf("UNALIGNED "); - } - - if(SCB_CFSR_UFSR & (1<<9)) - { - /* [9]:DIVBYZERO */ - rt_kprintf("DIVBYZERO "); - } - - rt_kprintf("\n"); -} - -static void bus_fault_track(void) -{ - rt_kprintf("bus fault:\n"); - rt_kprintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR); - - if(SCB_CFSR_BFSR & (1<<0)) - { - /* [0]:IBUSERR */ - rt_kprintf("IBUSERR "); - } - - if(SCB_CFSR_BFSR & (1<<1)) - { - /* [1]:PRECISERR */ - rt_kprintf("PRECISERR "); - } - - if(SCB_CFSR_BFSR & (1<<2)) - { - /* [2]:IMPRECISERR */ - rt_kprintf("IMPRECISERR "); - } - - if(SCB_CFSR_BFSR & (1<<3)) - { - /* [3]:UNSTKERR */ - rt_kprintf("UNSTKERR "); - } - - if(SCB_CFSR_BFSR & (1<<4)) - { - /* [4]:STKERR */ - rt_kprintf("STKERR "); - } - - if(SCB_CFSR_BFSR & (1<<7)) - { - rt_kprintf("SCB->BFAR:%08X\n", SCB_BFAR); - } - else - { - rt_kprintf("\n"); - } -} - -static void mem_manage_fault_track(void) -{ - rt_kprintf("mem manage fault:\n"); - rt_kprintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR); - - if(SCB_CFSR_MFSR & (1<<0)) - { - /* [0]:IACCVIOL */ - rt_kprintf("IACCVIOL "); - } - - if(SCB_CFSR_MFSR & (1<<1)) - { - /* [1]:DACCVIOL */ - rt_kprintf("DACCVIOL "); - } - - if(SCB_CFSR_MFSR & (1<<3)) - { - /* [3]:MUNSTKERR */ - rt_kprintf("MUNSTKERR "); - } - - if(SCB_CFSR_MFSR & (1<<4)) - { - /* [4]:MSTKERR */ - rt_kprintf("MSTKERR "); - } - - if(SCB_CFSR_MFSR & (1<<7)) - { - /* [7]:MMARVALID */ - rt_kprintf("SCB->MMAR:%08X\n", SCB_MMAR); - } - else - { - rt_kprintf("\n"); - } -} - -static void hard_fault_track(void) -{ - if(SCB_HFSR & (1UL<<1)) - { - /* [1]:VECTBL, Indicates hard fault is caused by failed vector fetch. */ - rt_kprintf("failed vector fetch\n"); - } - - if(SCB_HFSR & (1UL<<30)) - { - /* [30]:FORCED, Indicates hard fault is taken because of bus fault, - memory management fault, or usage fault. */ - if(SCB_CFSR_BFSR) - { - bus_fault_track(); - } - - if(SCB_CFSR_MFSR) - { - mem_manage_fault_track(); - } - - if(SCB_CFSR_UFSR) - { - usage_fault_track(); - } - } - - if(SCB_HFSR & (1UL<<31)) - { - /* [31]:DEBUGEVT, Indicates hard fault is triggered by debug event. */ - rt_kprintf("debug event\n"); - } -} -#endif /* RT_USING_FINSH */ - -struct exception_info -{ - rt_uint32_t exc_return; - struct stack_frame stack_frame; -}; - -/* - * fault exception handler - */ -void rt_hw_hard_fault_exception(struct exception_info * exception_info) -{ -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - extern long list_thread(void); -#endif - struct stack_frame* context = &exception_info->stack_frame; - - if (rt_exception_hook != RT_NULL) - { - rt_err_t result; - - result = rt_exception_hook(exception_info); - if (result == RT_EOK) - return; - } - - rt_kprintf("psr: 0x%08x\n", context->exception_stack_frame.psr); - - rt_kprintf("r00: 0x%08x\n", context->exception_stack_frame.r0); - rt_kprintf("r01: 0x%08x\n", context->exception_stack_frame.r1); - rt_kprintf("r02: 0x%08x\n", context->exception_stack_frame.r2); - rt_kprintf("r03: 0x%08x\n", context->exception_stack_frame.r3); - rt_kprintf("r04: 0x%08x\n", context->r4); - rt_kprintf("r05: 0x%08x\n", context->r5); - rt_kprintf("r06: 0x%08x\n", context->r6); - rt_kprintf("r07: 0x%08x\n", context->r7); - rt_kprintf("r08: 0x%08x\n", context->r8); - rt_kprintf("r09: 0x%08x\n", context->r9); - rt_kprintf("r10: 0x%08x\n", context->r10); - rt_kprintf("r11: 0x%08x\n", context->r11); - rt_kprintf("r12: 0x%08x\n", context->exception_stack_frame.r12); - rt_kprintf(" lr: 0x%08x\n", context->exception_stack_frame.lr); - rt_kprintf(" pc: 0x%08x\n", context->exception_stack_frame.pc); - - if(exception_info->exc_return & (1 << 2) ) - { - rt_kprintf("hard fault on thread: %s\r\n\r\n", rt_thread_self()->name); - -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - } - else - { - rt_kprintf("hard fault on handler\r\n\r\n"); - } - -#ifdef RT_USING_FINSH - hard_fault_track(); -#endif /* RT_USING_FINSH */ - - while (1); -} - -/** - * shutdown CPU - */ -RT_WEAK void rt_hw_cpu_shutdown(void) -{ - rt_kprintf("shutdown...\n"); - - RT_ASSERT(0); -} - -/** - * reset CPU - */ -RT_WEAK void rt_hw_cpu_reset(void) -{ - SCB_AIRCR = SCB_RESET_VALUE; -} - -#ifdef RT_USING_CPU_FFS -/** - * This function finds the first bit set (beginning with the least significant bit) - * in value and return the index of that bit. - * - * Bits are numbered starting at 1 (the least significant bit). A return value of - * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function - * shall return 0. - */ -#if defined(__CC_ARM) -__asm int __rt_ffs(int value) -{ - CMP r0, #0x00 - BEQ exit - - RBIT r0, r0 - CLZ r0, r0 - ADDS r0, r0, #0x01 - -exit - BX lr -} -#elif defined(__clang__) -int __rt_ffs(int value) -{ - __asm volatile( - "CMP %1, #0x00 \n" - "BEQ 1f \n" - - "RBIT %1, %1 \n" - "CLZ %0, %1 \n" - "ADDS %0, %0, #0x01 \n" - - "1: \n" - - : "=r"(value) - : "r"(value) - ); - return value; -} -#elif defined(__IAR_SYSTEMS_ICC__) -int __rt_ffs(int value) -{ - if (value == 0) return value; - - asm("RBIT %0, %1" : "=r"(value) : "r"(value)); - asm("CLZ %0, %1" : "=r"(value) : "r"(value)); - asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value)); - - return value; -} -#elif defined(__GNUC__) -int __rt_ffs(int value) -{ - return __builtin_ffs(value); -} -#endif - -#endif diff --git a/rt-thread/libcpu/arm/cortex-m33/SConscript b/rt-thread/libcpu/arm/cortex-m33/SConscript deleted file mode 100644 index b259a94..0000000 --- a/rt-thread/libcpu/arm/cortex-m33/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/cortex-m33/context_gcc.S b/rt-thread/libcpu/arm/cortex-m33/context_gcc.S deleted file mode 100644 index d1a4921..0000000 --- a/rt-thread/libcpu/arm/cortex-m33/context_gcc.S +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-10-11 Bernard first version - * 2012-01-01 aozima support context switch load/store FPU register. - * 2013-06-18 aozima add restore MSP feature. - * 2013-06-23 aozima support lazy stack optimized. - * 2018-07-24 aozima enhancement hard fault exception handler. - */ - -/** - * @addtogroup cortex-m4 - */ -/*@{*/ - -.cpu cortex-m4 -.syntax unified -.thumb -.text - -.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ -.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ -.equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */ -.equ NVIC_PENDSV_PRI, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */ -.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ - -/* - * rt_base_t rt_hw_interrupt_disable(); - */ -.global rt_hw_interrupt_disable -.type rt_hw_interrupt_disable, %function -rt_hw_interrupt_disable: - MRS r0, PRIMASK - CPSID I - BX LR - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ -.global rt_hw_interrupt_enable -.type rt_hw_interrupt_enable, %function -rt_hw_interrupt_enable: - MSR PRIMASK, r0 - BX LR - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to - */ -.global rt_hw_context_switch_interrupt -.type rt_hw_context_switch_interrupt, %function -.global rt_hw_context_switch -.type rt_hw_context_switch, %function - -rt_hw_context_switch_interrupt: -rt_hw_context_switch: - /* set rt_thread_switch_interrupt_flag to 1 */ - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 - STR r3, [r2] - - LDR r2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - STR r0, [r2] - -_reswitch: - LDR r2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - STR r1, [r2] - - LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - BX LR - -/* r0 --> switch from thread stack - * r1 --> switch to thread stack - * psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack - */ -.global PendSV_Handler -.type PendSV_Handler, %function -PendSV_Handler: - /* disable interrupt to protect context switch */ - MRS r2, PRIMASK - CPSID I - - /* get rt_thread_switch_interrupt_flag */ - LDR r0, =rt_thread_switch_interrupt_flag /* r0 = &rt_thread_switch_interrupt_flag */ - LDR r1, [r0] /* r1 = *r1 */ - CMP r1, #0x00 /* compare r1 == 0x00 */ - BNE schedule - MSR PRIMASK, r2 /* if r1 == 0x00, do msr PRIMASK, r2 */ - BX lr /* if r1 == 0x00, do bx lr */ - -schedule: - PUSH {r2} /* store interrupt state */ - - /* clear rt_thread_switch_interrupt_flag to 0 */ - MOV r1, #0x00 /* r1 = 0x00 */ - STR r1, [r0] /* *r0 = r1 */ - - /* skip register save at the first time */ - LDR r0, =rt_interrupt_from_thread /* r0 = &rt_interrupt_from_thread */ - LDR r1, [r0] /* r1 = *r0 */ - CBZ r1, switch_to_thread /* if r1 == 0, goto switch_to_thread */ - - /* Whether TrustZone thread stack exists */ - LDR r1, =rt_trustzone_current_context /* r1 = &rt_secure_current_context */ - LDR r1, [r1] /* r1 = *r1 */ - CBZ r1, contex_ns_store /* if r1 == 0, goto contex_ns_store */ - - /*call TrustZone fun, Save TrustZone stack */ - STMFD sp!, {r0-r1, lr} /* push register */ - MOV r0, r1 /* r0 = rt_secure_current_context */ - BL rt_trustzone_context_store /* call TrustZone store fun */ - LDMFD sp!, {r0-r1, lr} /* pop register */ - - /* check break from TrustZone */ - MOV r2, lr /* r2 = lr */ - TST r2, #0x40 /* if EXC_RETURN[6] is 1, TrustZone stack was used */ - BEQ contex_ns_store /* if r2 & 0x40 == 0, goto contex_ns_store */ - - /* push PSPLIM CONTROL PSP LR current_context to stack */ - MRS r3, psplim /* r3 = psplim */ - MRS r4, control /* r4 = control */ - MRS r5, psp /* r5 = psp */ - STMFD r5!, {r1-r4} /* push to thread stack */ - - /* update from thread stack pointer */ - LDR r0, [r0] /* r0 = rt_thread_switch_interrupt_flag */ - STR r5, [r0] /* *r0 = r5 */ - b switch_to_thread /* goto switch_to_thread */ - -contex_ns_store: - - MRS r1, psp /* get from thread stack pointer */ - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - TST lr, #0x10 /* if(!EXC_RETURN[4]) */ - IT EQ - VSTMDBEQ r1!, {d8 - d15} /* push FPU register s16~s31 */ -#endif - - STMFD r1!, {r4 - r11} /* push r4 - r11 register */ - - LDR r2, =rt_trustzone_current_context /* r2 = &rt_secure_current_context */ - LDR r2, [r2] /* r2 = *r2 */ - MOV r3, lr /* r3 = lr */ - MRS r4, psplim /* r4 = psplim */ - MRS r5, control /* r5 = control */ - STMFD r1!, {r2-r5} /* push to thread stack */ - - LDR r0, [r0] - STR r1, [r0] /* update from thread stack pointer */ - -switch_to_thread: - LDR r1, =rt_interrupt_to_thread - LDR r1, [r1] - LDR r1, [r1] /* load thread stack pointer */ - - /* update current TrustZone context */ - LDMFD r1!, {r2-r5} /* pop thread stack */ - MSR psplim, r4 /* psplim = r4 */ - MSR control, r5 /* control = r5 */ - MOV lr, r3 /* lr = r3 */ - LDR r6, =rt_trustzone_current_context /* r6 = &rt_secure_current_context */ - STR r2, [r6] /* *r6 = r2 */ - MOV r0, r2 /* r0 = r2 */ - - /* Whether TrustZone thread stack exists */ - CBZ r0, contex_ns_load /* if r0 == 0, goto contex_ns_load */ - PUSH {r1, r3} /* push lr, thread_stack */ - BL rt_trustzone_context_load /* call TrustZone load fun */ - POP {r1, r3} /* pop lr, thread_stack */ - MOV lr, r3 /* lr = r1 */ - TST r3, #0x40 /* if EXC_RETURN[6] is 1, TrustZone stack was used */ - BEQ contex_ns_load /* if r1 & 0x40 == 0, goto contex_ns_load */ - B pendsv_exit - -contex_ns_load: - LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */ - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - TST lr, #0x10 /* if(!EXC_RETURN[4]) */ - IT EQ - VLDMIAEQ r1!, {d8 - d15} /* pop FPU register s16~s31 */ -#endif - -pendsv_exit: - MSR psp, r1 /* update stack pointer */ - /* restore interrupt */ - POP {r2} - MSR PRIMASK, r2 - - BX lr - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to - */ -.global rt_hw_context_switch_to -.type rt_hw_context_switch_to, %function -rt_hw_context_switch_to: - LDR r1, =rt_interrupt_to_thread - STR r0, [r1] - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - /* CLEAR CONTROL.FPCA */ - MRS r2, CONTROL /* read */ - BIC r2, #0x04 /* modify */ - MSR CONTROL, r2 /* write-back */ -#endif - - /* set from thread to 0 */ - LDR r1, =rt_interrupt_from_thread - MOV r0, #0x0 - STR r0, [r1] - - /* set interrupt flag to 1 */ - LDR r1, =rt_thread_switch_interrupt_flag - MOV r0, #1 - STR r0, [r1] - - /* set the PendSV and SysTick exception priority */ - LDR r0, =NVIC_SYSPRI2 - LDR r1, =NVIC_PENDSV_PRI - LDR.W r2, [r0,#0x00] /* read */ - ORR r1,r1,r2 /* modify */ - STR r1, [r0] /* write-back */ - - LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - - /* restore MSP */ - LDR r0, =SCB_VTOR - LDR r0, [r0] - LDR r0, [r0] - NOP - MSR msp, r0 - - /* enable interrupts at processor level */ - CPSIE F - CPSIE I - - /* ensure PendSV exception taken place before subsequent operation */ - DSB - ISB - - /* never reach here! */ - -/* compatible with old version */ -.global rt_hw_interrupt_thread_switch -.type rt_hw_interrupt_thread_switch, %function -rt_hw_interrupt_thread_switch: - BX lr - NOP - -.global HardFault_Handler -.type HardFault_Handler, %function -HardFault_Handler: - /* get current context */ - MRS r0, msp /* get fault context from handler. */ - TST lr, #0x04 /* if(!EXC_RETURN[2]) */ - BEQ get_sp_done - MRS r0, psp /* get fault context from thread. */ -get_sp_done: - - STMFD r0!, {r4 - r11} /* push r4 - r11 register */ - - LDR r2, =rt_trustzone_current_context /* r2 = &rt_secure_current_context */ - LDR r2, [r2] /* r2 = *r2 */ - MOV r3, lr /* r3 = lr */ - MRS r4, psplim /* r4 = psplim */ - MRS r5, control /* r5 = control */ - STMFD r0!, {r2-r5} /* push to thread stack */ - - STMFD r0!, {lr} /* push exec_return register */ - - TST lr, #0x04 /* if(!EXC_RETURN[2]) */ - BEQ update_msp - MSR psp, r0 /* update stack pointer to PSP. */ - B update_done -update_msp: - MSR msp, r0 /* update stack pointer to MSP. */ -update_done: - - PUSH {LR} - BL rt_hw_hard_fault_exception - POP {LR} - - ORR lr, lr, #0x04 - BX lr diff --git a/rt-thread/libcpu/arm/cortex-m33/context_iar.S b/rt-thread/libcpu/arm/cortex-m33/context_iar.S deleted file mode 100644 index c9c2ed6..0000000 --- a/rt-thread/libcpu/arm/cortex-m33/context_iar.S +++ /dev/null @@ -1,304 +0,0 @@ -;/* -; * Copyright (c) 2006-2018, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2009-01-17 Bernard first version -; * 2009-09-27 Bernard add protect when contex switch occurs -; * 2012-01-01 aozima support context switch load/store FPU register. -; * 2013-06-18 aozima add restore MSP feature. -; * 2013-06-23 aozima support lazy stack optimized. -; * 2018-07-24 aozima enhancement hard fault exception handler. -; */ - -;/** -; * @addtogroup cortex-m33 -; */ -;/*@{*/ - -SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register -NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register -NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) -NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception - - SECTION .text:CODE(2) - THUMB - REQUIRE8 - PRESERVE8 - - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - IMPORT rt_trustzone_current_context - IMPORT rt_trustzone_context_load - IMPORT rt_trustzone_context_store - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ - EXPORT rt_hw_interrupt_disable -rt_hw_interrupt_disable: - MRS r0, PRIMASK - CPSID I - BX LR - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ - EXPORT rt_hw_interrupt_enable -rt_hw_interrupt_enable: - MSR PRIMASK, r0 - BX LR - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ - EXPORT rt_hw_context_switch_interrupt - EXPORT rt_hw_context_switch -rt_hw_context_switch_interrupt: -rt_hw_context_switch: - ; set rt_thread_switch_interrupt_flag to 1 - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 - STR r3, [r2] - - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] - -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - BX LR - -; r0 --> switch from thread stack -; r1 --> switch to thread stack -; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack - EXPORT PendSV_Handler -PendSV_Handler: - - ; disable interrupt to protect context switch - MRS r2, PRIMASK - CPSID I - - ; get rt_thread_switch_interrupt_flag - LDR r0, =rt_thread_switch_interrupt_flag ; r0 = &rt_thread_switch_interrupt_flag - LDR r1, [r0] ; r1 = *r1 - CMP r1, #0x00 ; compare r1 == 0x00 - BNE schedule - MSR PRIMASK, r2 ; if r1 == 0x00, do msr PRIMASK, r2 - BX lr ; if r1 == 0x00, do bx lr - -schedule - PUSH {r2} ; store interrupt state - - ; clear rt_thread_switch_interrupt_flag to 0 - MOV r1, #0x00 ; r1 = 0x00 - STR r1, [r0] ; *r0 = r1 - - ; skip register save at the first time - LDR r0, =rt_interrupt_from_thread ; r0 = &rt_interrupt_from_thread - LDR r1, [r0] ; r1 = *r0 - CBZ r1, switch_to_thread ; if r1 == 0, goto switch_to_thread - - ; Whether TrustZone thread stack exists - LDR r1, =rt_trustzone_current_context ; r1 = &rt_secure_current_context - LDR r1, [r1] ; r1 = *r1 - CBZ r1, contex_ns_store ; if r1 == 0, goto contex_ns_store - - ;call TrustZone fun, Save TrustZone stack - STMFD sp!, {r0-r1, lr} ; push register - MOV r0, r1 ; r0 = rt_secure_current_context - BL rt_trustzone_context_store ; call TrustZone store fun - LDMFD sp!, {r0-r1, lr} ; pop register - - ; check break from TrustZone - MOV r2, lr ; r2 = lr - TST r2, #0x40 ; if EXC_RETURN[6] is 1, TrustZone stack was used - BEQ contex_ns_store ; if r2 & 0x40 == 0, goto contex_ns_store - - ; push PSPLIM CONTROL PSP LR current_context to stack - MRS r3, psplim ; r3 = psplim - MRS r4, control ; r4 = control - MRS r5, psp ; r5 = psp - STMFD r5!, {r1-r4} ; push to thread stack - - ; update from thread stack pointer - LDR r0, [r0] ; r0 = rt_thread_switch_interrupt_flag - STR r5, [r0] ; *r0 = r5 - b switch_to_thread ; goto switch_to_thread - -contex_ns_store - - MRS r1, psp ; get from thread stack pointer - -#if defined ( __ARMVFP__ ) - TST lr, #0x10 ; if(!EXC_RETURN[4]) - BNE skip_push_fpu - VSTMDB r1!, {d8 - d15} ; push FPU register s16~s31 -skip_push_fpu -#endif - - STMFD r1!, {r4 - r11} ; push r4 - r11 register - - LDR r2, =rt_trustzone_current_context ; r2 = &rt_secure_current_context - LDR r2, [r2] ; r2 = *r2 - MOV r3, lr ; r3 = lr - MRS r4, psplim ; r4 = psplim - MRS r5, control ; r5 = control - STMFD r1!, {r2-r5} ; push to thread stack - - LDR r0, [r0] - STR r1, [r0] ; update from thread stack pointer - -switch_to_thread - - LDR r1, =rt_interrupt_to_thread - LDR r1, [r1] - LDR r1, [r1] ; load thread stack pointer - - ; update current TrustZone context - LDMFD r1!, {r2-r5} ; pop thread stack - MSR psplim, r4 ; psplim = r4 - MSR control, r5 ; control = r5 - MOV lr, r3 ; lr = r3 - LDR r6, =rt_trustzone_current_context ; r6 = &rt_secure_current_context - STR r2, [r6] ; *r6 = r2 - MOV r0, r2 ; r0 = r2 - - ; Whether TrustZone thread stack exists - CBZ r0, contex_ns_load ; if r0 == 0, goto contex_ns_load - PUSH {r1, r3} ; push lr, thread_stack - BL rt_trustzone_context_load ; call TrustZone load fun - POP {r1, r3} ; pop lr, thread_stack - MOV lr, r3 ; lr = r1 - TST r3, #0x40 ; if EXC_RETURN[6] is 1, TrustZone stack was used - BEQ contex_ns_load ; if r1 & 0x40 == 0, goto contex_ns_load - B pendsv_exit - -contex_ns_load - LDMFD r1!, {r4 - r11} ; pop r4 - r11 register - -#if defined ( __ARMVFP__ ) - TST lr, #0x10 ; if(!EXC_RETURN[4]) - BNE skip_pop_fpu - VLDMIA r1!, {d8 - d15} ; pop FPU register s16~s31 -skip_pop_fpu -#endif - -pendsv_exit - MSR psp, r1 ; update stack pointer - ; restore interrupt - POP {r2} - MSR PRIMASK, r2 - - BX lr - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; */ - EXPORT rt_hw_context_switch_to -rt_hw_context_switch_to: - LDR r1, =rt_interrupt_to_thread - STR r0, [r1] - -#if defined ( __ARMVFP__ ) - ; CLEAR CONTROL.FPCA - MRS r2, CONTROL ; read - BIC r2, r2, #0x04 ; modify - MSR CONTROL, r2 ; write-back -#endif - - ; set from thread to 0 - LDR r1, =rt_interrupt_from_thread - MOV r0, #0x0 - STR r0, [r1] - - ; set interrupt flag to 1 - LDR r1, =rt_thread_switch_interrupt_flag - MOV r0, #1 - STR r0, [r1] - - ; set the PendSV and SysTick exception priority - LDR r0, =NVIC_SYSPRI2 - LDR r1, =NVIC_PENDSV_PRI - LDR.W r2, [r0,#0x00] ; read - ORR r1,r1,r2 ; modify - STR r1, [r0] ; write-back - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - - ; restore MSP - LDR r0, =SCB_VTOR - LDR r0, [r0] - LDR r0, [r0] - NOP - MSR msp, r0 - - ; enable interrupts at processor level - CPSIE F - CPSIE I - - ; ensure PendSV exception taken place before subsequent operation - DSB - ISB - - ; never reach here! - -; compatible with old version - EXPORT rt_hw_interrupt_thread_switch -rt_hw_interrupt_thread_switch: - BX lr - - IMPORT rt_hw_hard_fault_exception - EXPORT HardFault_Handler -HardFault_Handler: - - ; get current context - MRS r0, msp ; get fault context from handler. - TST lr, #0x04 ; if(!EXC_RETURN[2]) - BEQ get_sp_done - MRS r0, psp ; get fault context from thread. -get_sp_done - - STMFD r0!, {r4 - r11} ; push r4 - r11 register - - LDR r2, =rt_trustzone_current_context ; r2 = &rt_secure_current_context - LDR r2, [r2] ; r2 = *r2 - MOV r3, lr ; r3 = lr - MRS r4, psplim ; r4 = psplim - MRS r5, control ; r5 = control - STMFD r0!, {r2-r5} ; push to thread stack - - STMFD r0!, {lr} ; push exec_return register - - TST lr, #0x04 ; if(!EXC_RETURN[2]) - BEQ update_msp - MSR psp, r0 ; update stack pointer to PSP. - B update_done -update_msp - MSR msp, r0 ; update stack pointer to MSP. -update_done - - PUSH {lr} - BL rt_hw_hard_fault_exception - POP {lr} - - ORR lr, lr, #0x04 - BX lr - - END diff --git a/rt-thread/libcpu/arm/cortex-m33/context_rvds.S b/rt-thread/libcpu/arm/cortex-m33/context_rvds.S deleted file mode 100644 index 5b527b5..0000000 --- a/rt-thread/libcpu/arm/cortex-m33/context_rvds.S +++ /dev/null @@ -1,310 +0,0 @@ -;/* -;* Copyright (c) 2006-2018, RT-Thread Development Team -;* -;* SPDX-License-Identifier: Apache-2.0 -;* -; * Change Logs: -; * Date Author Notes -; * 2009-01-17 Bernard first version. -; * 2012-01-01 aozima support context switch load/store FPU register. -; * 2013-06-18 aozima add restore MSP feature. -; * 2013-06-23 aozima support lazy stack optimized. -; * 2018-07-24 aozima enhancement hard fault exception handler. -; */ - -;/** -; * @addtogroup cortex-m33 -; */ -;/*@{*/ - -SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register -NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register -NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) -NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception - - AREA |.text|, CODE, READONLY, ALIGN=2 - THUMB - REQUIRE8 - PRESERVE8 - - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - IMPORT rt_trustzone_current_context - IMPORT rt_trustzone_context_load - IMPORT rt_trustzone_context_store - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ -rt_hw_interrupt_disable PROC - EXPORT rt_hw_interrupt_disable - MRS r0, PRIMASK - CPSID I - BX LR - ENDP - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ -rt_hw_interrupt_enable PROC - EXPORT rt_hw_interrupt_enable - MSR PRIMASK, r0 - BX LR - ENDP - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ -rt_hw_context_switch_interrupt - EXPORT rt_hw_context_switch_interrupt -rt_hw_context_switch PROC - EXPORT rt_hw_context_switch - - ; set rt_thread_switch_interrupt_flag to 1 - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 - STR r3, [r2] - - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] - -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - BX LR - ENDP - -; r0 --> switch from thread stack -; r1 --> switch to thread stack -; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack -PendSV_Handler PROC - EXPORT PendSV_Handler - - ; disable interrupt to protect context switch - MRS r2, PRIMASK ; R2 = PRIMASK - CPSID I ; disable all interrupt - - ; get rt_thread_switch_interrupt_flag - LDR r0, =rt_thread_switch_interrupt_flag ; r0 = &rt_thread_switch_interrupt_flag - LDR r1, [r0] ; r1 = *r1 - CMP r1, #0x00 ; compare r1 == 0x00 - BNE schedule - MSR PRIMASK, r2 ; if r1 == 0x00, do msr PRIMASK, r2 - BX lr ; if r1 == 0x00, do bx lr - -schedule - PUSH {r2} ; store interrupt state - - ; clear rt_thread_switch_interrupt_flag to 0 - MOV r1, #0x00 ; r1 = 0x00 - STR r1, [r0] ; *r0 = r1 - - ; skip register save at the first time - LDR r0, =rt_interrupt_from_thread ; r0 = &rt_interrupt_from_thread - LDR r1, [r0] ; r1 = *r0 - CBZ r1, switch_to_thread ; if r1 == 0, goto switch_to_thread - - ; Whether TrustZone thread stack exists - LDR r1, =rt_trustzone_current_context ; r1 = &rt_secure_current_context - LDR r1, [r1] ; r1 = *r1 - CBZ r1, contex_ns_store ; if r1 == 0, goto contex_ns_store - - ;call TrustZone fun, Save TrustZone stack - STMFD sp!, {r0-r1, lr} ; push register - MOV r0, r1 ; r0 = rt_secure_current_context - BL rt_trustzone_context_store ; call TrustZone store fun - LDMFD sp!, {r0-r1, lr} ; pop register - - ; check break from TrustZone - MOV r2, lr ; r2 = lr - TST r2, #0x40 ; if EXC_RETURN[6] is 1, TrustZone stack was used - BEQ contex_ns_store ; if r2 & 0x40 == 0, goto contex_ns_store - - ; push PSPLIM CONTROL PSP LR current_context to stack - MRS r3, psplim ; r3 = psplim - MRS r4, control ; r4 = control - MRS r5, psp ; r5 = psp - STMFD r5!, {r1-r4} ; push to thread stack - - ; update from thread stack pointer - LDR r0, [r0] ; r0 = rt_thread_switch_interrupt_flag - STR r5, [r0] ; *r0 = r5 - b switch_to_thread ; goto switch_to_thread - -contex_ns_store - - MRS r1, psp ; get from thread stack pointer - - IF {FPU} != "SoftVFP" - TST lr, #0x10 ; if(!EXC_RETURN[4]) - VSTMFDEQ r1!, {d8 - d15} ; push FPU register s16~s31 - ENDIF - - STMFD r1!, {r4 - r11} ; push r4 - r11 register - - LDR r2, =rt_trustzone_current_context ; r2 = &rt_secure_current_context - LDR r2, [r2] ; r2 = *r2 - MOV r3, lr ; r3 = lr - MRS r4, psplim ; r4 = psplim - MRS r5, control ; r5 = control - STMFD r1!, {r2-r5} ; push to thread stack - - LDR r0, [r0] - STR r1, [r0] ; update from thread stack pointer - -switch_to_thread - LDR r1, =rt_interrupt_to_thread - LDR r1, [r1] - LDR r1, [r1] ; load thread stack pointer - - ; update current TrustZone context - LDMFD r1!, {r2-r5} ; pop thread stack - MSR psplim, r4 ; psplim = r4 - MSR control, r5 ; control = r5 - MOV lr, r3 ; lr = r3 - LDR r6, =rt_trustzone_current_context ; r6 = &rt_secure_current_context - STR r2, [r6] ; *r6 = r2 - MOV r0, r2 ; r0 = r2 - - ; Whether TrustZone thread stack exists - CBZ r0, contex_ns_load ; if r0 == 0, goto contex_ns_load - PUSH {r1, r3} ; push lr, thread_stack - BL rt_trustzone_context_load ; call TrustZone load fun - POP {r1, r3} ; pop lr, thread_stack - MOV lr, r3 ; lr = r1 - TST r3, #0x40 ; if EXC_RETURN[6] is 1, TrustZone stack was used - BEQ contex_ns_load ; if r1 & 0x40 == 0, goto contex_ns_load - B pendsv_exit - -contex_ns_load - LDMFD r1!, {r4 - r11} ; pop r4 - r11 register - - IF {FPU} != "SoftVFP" - TST lr, #0x10 ; if(!EXC_RETURN[4]) - VLDMFDEQ r1!, {d8 - d15} ; pop FPU register s16~s31 - ENDIF - -pendsv_exit - MSR psp, r1 ; update stack pointer - ; restore interrupt - POP {r2} - MSR PRIMASK, r2 - - BX lr - ENDP - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; * this fucntion is used to perform the first thread switch -; */ -rt_hw_context_switch_to PROC - EXPORT rt_hw_context_switch_to - ; set to thread - LDR r1, =rt_interrupt_to_thread - STR r0, [r1] - - IF {FPU} != "SoftVFP" - ; CLEAR CONTROL.FPCA - MRS r2, CONTROL ; read - BIC r2, #0x04 ; modify - MSR CONTROL, r2 ; write-back - ENDIF - - ; set from thread to 0 - LDR r1, =rt_interrupt_from_thread - MOV r0, #0x0 - STR r0, [r1] - - ; set interrupt flag to 1 - LDR r1, =rt_thread_switch_interrupt_flag - MOV r0, #1 - STR r0, [r1] - - ; set the PendSV and SysTick exception priority - LDR r0, =NVIC_SYSPRI2 - LDR r1, =NVIC_PENDSV_PRI - LDR.W r2, [r0,#0x00] ; read - ORR r1,r1,r2 ; modify - STR r1, [r0] ; write-back - - ; trigger the PendSV exception (causes context switch) - LDR r0, =NVIC_INT_CTRL - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - - ; restore MSP - LDR r0, =SCB_VTOR - LDR r0, [r0] - LDR r0, [r0] - MSR msp, r0 - - ; enable interrupts at processor level - CPSIE F - CPSIE I - - ; ensure PendSV exception taken place before subsequent operation - DSB - ISB - - ; never reach here! - ENDP - -; compatible with old version -rt_hw_interrupt_thread_switch PROC - EXPORT rt_hw_interrupt_thread_switch - BX lr - ENDP - - IMPORT rt_hw_hard_fault_exception - EXPORT HardFault_Handler -HardFault_Handler PROC - - ; get current context - MRS r0, msp ;get fault context from handler - TST lr, #0x04 ;if(!EXC_RETURN[2]) - BEQ get_sp_done - MRS r0, psp ;get fault context from thread -get_sp_done - - STMFD r0!, {r4 - r11} ; push r4 - r11 register - - LDR r2, =rt_trustzone_current_context ; r2 = &rt_secure_current_context - LDR r2, [r2] ; r2 = *r2 - MOV r3, lr ; r3 = lr - MRS r4, psplim ; r4 = psplim - MRS r5, control ; r5 = control - STMFD r0!, {r2-r5} ; push to thread stack - - STMFD r0!, {lr} ; push exec_return register - - TST lr, #0x04 ; if(!EXC_RETURN[2]) - BEQ update_msp - MSR psp, r0 ; update stack pointer to PSP - B update_done -update_msp - MSR msp, r0 ; update stack pointer to MSP -update_done - - PUSH {lr} - BL rt_hw_hard_fault_exception - POP {lr} - - ORR lr, lr, #0x04 - BX lr - ENDP - - ALIGN 4 - - END diff --git a/rt-thread/libcpu/arm/cortex-m33/cpuport.c b/rt-thread/libcpu/arm/cortex-m33/cpuport.c deleted file mode 100644 index 44e7c28..0000000 --- a/rt-thread/libcpu/arm/cortex-m33/cpuport.c +++ /dev/null @@ -1,563 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-10-21 Bernard the first version. - * 2011-10-27 aozima update for cortex-M4 FPU. - * 2011-12-31 aozima fixed stack align issues. - * 2012-01-01 aozima support context switch load/store FPU register. - * 2012-12-11 lgnq fixed the coding style. - * 2012-12-23 aozima stack addr align to 8byte. - * 2012-12-29 Bernard Add exception hook. - * 2013-06-23 aozima support lazy stack optimized. - * 2018-07-24 aozima enhancement hard fault exception handler. - * 2019-07-03 yangjie add __rt_ffs() for armclang. - */ - -#include - -#if /* ARMCC */ ( (defined ( __CC_ARM ) && defined ( __TARGET_FPU_VFP )) \ - /* Clang */ || (defined ( __clang__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) \ - /* IAR */ || (defined ( __ICCARM__ ) && defined ( __ARMVFP__ )) \ - /* GNU */ || (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) ) -#define USE_FPU 1 -#else -#define USE_FPU 0 -#endif - -/* exception and interrupt handler table */ -rt_uint32_t rt_interrupt_from_thread; -rt_uint32_t rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -/* exception hook */ -static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL; - -struct exception_stack_frame -{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r12; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t psr; -}; - -struct stack_frame -{ - rt_uint32_t tz; - rt_uint32_t lr; - rt_uint32_t psplim; - rt_uint32_t control; - - /* r4 ~ r11 register */ - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t r11; - - struct exception_stack_frame exception_stack_frame; -}; - -struct exception_stack_frame_fpu -{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r12; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t psr; - -#if USE_FPU - /* FPU register */ - rt_uint32_t S0; - rt_uint32_t S1; - rt_uint32_t S2; - rt_uint32_t S3; - rt_uint32_t S4; - rt_uint32_t S5; - rt_uint32_t S6; - rt_uint32_t S7; - rt_uint32_t S8; - rt_uint32_t S9; - rt_uint32_t S10; - rt_uint32_t S11; - rt_uint32_t S12; - rt_uint32_t S13; - rt_uint32_t S14; - rt_uint32_t S15; - rt_uint32_t FPSCR; - rt_uint32_t NO_NAME; -#endif -}; - -struct stack_frame_fpu -{ - rt_uint32_t flag; - - /* r4 ~ r11 register */ - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t r11; - -#if USE_FPU - /* FPU register s16 ~ s31 */ - rt_uint32_t s16; - rt_uint32_t s17; - rt_uint32_t s18; - rt_uint32_t s19; - rt_uint32_t s20; - rt_uint32_t s21; - rt_uint32_t s22; - rt_uint32_t s23; - rt_uint32_t s24; - rt_uint32_t s25; - rt_uint32_t s26; - rt_uint32_t s27; - rt_uint32_t s28; - rt_uint32_t s29; - rt_uint32_t s30; - rt_uint32_t s31; -#endif - - struct exception_stack_frame_fpu exception_stack_frame; -}; - -rt_uint8_t *rt_hw_stack_init(void *tentry, - void *parameter, - rt_uint8_t *stack_addr, - void *texit) -{ - struct stack_frame *stack_frame; - rt_uint8_t *stk; - unsigned long i; - - stk = stack_addr + sizeof(rt_uint32_t); - stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8); - stk -= sizeof(struct stack_frame); - - stack_frame = (struct stack_frame *)stk; - - /* init all register */ - for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++) - { - ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef; - } - - stack_frame->exception_stack_frame.r0 = (unsigned long)parameter; /* r0 : argument */ - stack_frame->exception_stack_frame.r1 = 0; /* r1 */ - stack_frame->exception_stack_frame.r2 = 0; /* r2 */ - stack_frame->exception_stack_frame.r3 = 0; /* r3 */ - stack_frame->exception_stack_frame.r12 = 0; /* r12 */ - stack_frame->exception_stack_frame.lr = (unsigned long)texit; /* lr */ - stack_frame->exception_stack_frame.pc = (unsigned long)tentry; /* entry point, pc */ - stack_frame->exception_stack_frame.psr = 0x01000000L; /* PSR */ - - stack_frame->tz = 0x00; /* trustzone thread context */ - /* - * Exception return behavior - * +--------+---+---+------+-------+------+-------+---+----+ - * | PREFIX | - | S | DCRS | FType | Mode | SPSEL | - | ES | - * +--------+---+---+------+-------+------+-------+---+----+ - * PREFIX [31:24] - Indicates that this is an EXC_RETURN value. This field reads as 0b11111111. - * S [6] - Indicates whether registers have been pushed to a Secure or Non-secure stack. - * 0: Non-secure stack used. - * 1: Secure stack used. - * DCRS [5] - Indicates whether the default stacking rules apply, or whether the callee registers are already on the stack. - * 0: Stacking of the callee saved registers is skipped. - * 1: Default rules for stacking the callee registers are followed. - * FType [4] - In a PE with the Main and Floating-point Extensions: - * 0: The PE allocated space on the stack for FP context. - * 1: The PE did not allocate space on the stack for FP context. - * In a PE without the Floating-point Extension, this bit is Reserved, RES1. - * Mode [3] - Indicates the mode that was stacked from. - * 0: Handler mode. - * 1: Thread mode. - * SPSEL [2] - Indicates which stack contains the exception stack frame. - * 0: Main stack pointer. - * 1: Process stack pointer. - * ES [0] - Indicates the Security state the exception was taken to. - * 0: Non-secure. - * 1: Secure. - */ -#ifdef ARCH_ARM_CORTEX_SECURE - stack_frame->lr = 0xfffffffdL; -#else - stack_frame->lr = 0xffffffbcL; -#endif - stack_frame->psplim = 0x00; - /* - * CONTROL register bit assignments - * +---+------+------+-------+-------+ - * | - | SFPA | FPCA | SPSEL | nPRIV | - * +---+------+------+-------+-------+ - * SFPA [3] - Indicates that the floating-point registers contain active state that belongs to the Secure state: - * 0: The floating-point registers do not contain state that belongs to the Secure state. - * 1: The floating-point registers contain state that belongs to the Secure state. - * This bit is not banked between Security states and RAZ/WI from Non-secure state. - * FPCA [2] - Indicates whether floating-point context is active: - * 0: No floating-point context active. - * 1: Floating-point context active. - * This bit is used to determine whether to preserve floating-point state when processing an exception. - * This bit is not banked between Security states. - * SPSEL [1] - Defines the currently active stack pointer: - * 0: MSP is the current stack pointer. - * 1: PSP is the current stack pointer. - * In Handler mode, this bit reads as zero and ignores writes. The CortexM33 core updates this bit automatically onexception return. - * This bit is banked between Security states. - * nPRIV [0] - Defines the Thread mode privilege level: - * 0: Privileged. - * 1: Unprivileged. - * This bit is banked between Security states. - * - */ - stack_frame->control = 0x00000000L; - - /* return task's current stack address */ - return stk; -} - -/** - * This function set the hook, which is invoked on fault exception handling. - * - * @param exception_handle the exception handling hook function. - */ -void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context)) -{ - rt_exception_hook = exception_handle; -} - -#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */ -#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ -#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ -#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ -#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */ -#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */ - -#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ -#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ -#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */ - -#ifdef RT_USING_FINSH -static void usage_fault_track(void) -{ - rt_kprintf("usage fault:\n"); - rt_kprintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR); - - if(SCB_CFSR_UFSR & (1<<0)) - { - /* [0]:UNDEFINSTR */ - rt_kprintf("UNDEFINSTR "); - } - - if(SCB_CFSR_UFSR & (1<<1)) - { - /* [1]:INVSTATE */ - rt_kprintf("INVSTATE "); - } - - if(SCB_CFSR_UFSR & (1<<2)) - { - /* [2]:INVPC */ - rt_kprintf("INVPC "); - } - - if(SCB_CFSR_UFSR & (1<<3)) - { - /* [3]:NOCP */ - rt_kprintf("NOCP "); - } - - if(SCB_CFSR_UFSR & (1<<8)) - { - /* [8]:UNALIGNED */ - rt_kprintf("UNALIGNED "); - } - - if(SCB_CFSR_UFSR & (1<<9)) - { - /* [9]:DIVBYZERO */ - rt_kprintf("DIVBYZERO "); - } - - rt_kprintf("\n"); -} - -static void bus_fault_track(void) -{ - rt_kprintf("bus fault:\n"); - rt_kprintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR); - - if(SCB_CFSR_BFSR & (1<<0)) - { - /* [0]:IBUSERR */ - rt_kprintf("IBUSERR "); - } - - if(SCB_CFSR_BFSR & (1<<1)) - { - /* [1]:PRECISERR */ - rt_kprintf("PRECISERR "); - } - - if(SCB_CFSR_BFSR & (1<<2)) - { - /* [2]:IMPRECISERR */ - rt_kprintf("IMPRECISERR "); - } - - if(SCB_CFSR_BFSR & (1<<3)) - { - /* [3]:UNSTKERR */ - rt_kprintf("UNSTKERR "); - } - - if(SCB_CFSR_BFSR & (1<<4)) - { - /* [4]:STKERR */ - rt_kprintf("STKERR "); - } - - if(SCB_CFSR_BFSR & (1<<7)) - { - rt_kprintf("SCB->BFAR:%08X\n", SCB_BFAR); - } - else - { - rt_kprintf("\n"); - } -} - -static void mem_manage_fault_track(void) -{ - rt_kprintf("mem manage fault:\n"); - rt_kprintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR); - - if(SCB_CFSR_MFSR & (1<<0)) - { - /* [0]:IACCVIOL */ - rt_kprintf("IACCVIOL "); - } - - if(SCB_CFSR_MFSR & (1<<1)) - { - /* [1]:DACCVIOL */ - rt_kprintf("DACCVIOL "); - } - - if(SCB_CFSR_MFSR & (1<<3)) - { - /* [3]:MUNSTKERR */ - rt_kprintf("MUNSTKERR "); - } - - if(SCB_CFSR_MFSR & (1<<4)) - { - /* [4]:MSTKERR */ - rt_kprintf("MSTKERR "); - } - - if(SCB_CFSR_MFSR & (1<<7)) - { - /* [7]:MMARVALID */ - rt_kprintf("SCB->MMAR:%08X\n", SCB_MMAR); - } - else - { - rt_kprintf("\n"); - } -} - -static void hard_fault_track(void) -{ - if(SCB_HFSR & (1UL<<1)) - { - /* [1]:VECTBL, Indicates hard fault is caused by failed vector fetch. */ - rt_kprintf("failed vector fetch\n"); - } - - if(SCB_HFSR & (1UL<<30)) - { - /* [30]:FORCED, Indicates hard fault is taken because of bus fault, - memory management fault, or usage fault. */ - if(SCB_CFSR_BFSR) - { - bus_fault_track(); - } - - if(SCB_CFSR_MFSR) - { - mem_manage_fault_track(); - } - - if(SCB_CFSR_UFSR) - { - usage_fault_track(); - } - } - - if(SCB_HFSR & (1UL<<31)) - { - /* [31]:DEBUGEVT, Indicates hard fault is triggered by debug event. */ - rt_kprintf("debug event\n"); - } -} -#endif /* RT_USING_FINSH */ - -struct exception_info -{ - rt_uint32_t exc_return; - struct stack_frame stack_frame; -}; - -void rt_hw_hard_fault_exception(struct exception_info *exception_info) -{ -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - extern long list_thread(void); -#endif - struct exception_stack_frame *exception_stack = &exception_info->stack_frame.exception_stack_frame; - struct stack_frame *context = &exception_info->stack_frame; - - if (rt_exception_hook != RT_NULL) - { - rt_err_t result; - - result = rt_exception_hook(exception_stack); - if (result == RT_EOK) return; - } - - rt_kprintf("psr: 0x%08x\n", context->exception_stack_frame.psr); - - rt_kprintf("r00: 0x%08x\n", context->exception_stack_frame.r0); - rt_kprintf("r01: 0x%08x\n", context->exception_stack_frame.r1); - rt_kprintf("r02: 0x%08x\n", context->exception_stack_frame.r2); - rt_kprintf("r03: 0x%08x\n", context->exception_stack_frame.r3); - rt_kprintf("r04: 0x%08x\n", context->r4); - rt_kprintf("r05: 0x%08x\n", context->r5); - rt_kprintf("r06: 0x%08x\n", context->r6); - rt_kprintf("r07: 0x%08x\n", context->r7); - rt_kprintf("r08: 0x%08x\n", context->r8); - rt_kprintf("r09: 0x%08x\n", context->r9); - rt_kprintf("r10: 0x%08x\n", context->r10); - rt_kprintf("r11: 0x%08x\n", context->r11); - rt_kprintf("r12: 0x%08x\n", context->exception_stack_frame.r12); - rt_kprintf(" lr: 0x%08x\n", context->exception_stack_frame.lr); - rt_kprintf(" pc: 0x%08x\n", context->exception_stack_frame.pc); - - if (exception_info->exc_return & (1 << 2)) - { - rt_kprintf("hard fault on thread: %s\r\n\r\n", rt_thread_self()->name); - -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - } - else - { - rt_kprintf("hard fault on handler\r\n\r\n"); - } - - if ( (exception_info->exc_return & 0x10) == 0) - { - rt_kprintf("FPU active!\r\n"); - } - -#ifdef RT_USING_FINSH - hard_fault_track(); -#endif /* RT_USING_FINSH */ - - while (1); -} - -/** - * shutdown CPU - */ -RT_WEAK void rt_hw_cpu_shutdown(void) -{ - rt_kprintf("shutdown...\n"); - - RT_ASSERT(0); -} - -/** - * reset CPU - */ -RT_WEAK void rt_hw_cpu_reset(void) -{ - SCB_AIRCR = SCB_RESET_VALUE; -} - -#ifdef RT_USING_CPU_FFS -/** - * This function finds the first bit set (beginning with the least significant bit) - * in value and return the index of that bit. - * - * Bits are numbered starting at 1 (the least significant bit). A return value of - * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function - * shall return 0. - */ -#if defined(__CC_ARM) -__asm int __rt_ffs(int value) -{ - CMP r0, #0x00 - BEQ exit - - RBIT r0, r0 - CLZ r0, r0 - ADDS r0, r0, #0x01 - -exit - BX lr -} -#elif defined(__clang__) -int __rt_ffs(int value) -{ - if (value == 0) return value; - - __asm volatile( - "RBIT r0, r0 \n" - "CLZ r0, r0 \n" - "ADDS r0, r0, #0x01 \n" - - : "=r"(value) - : "r"(value) - ); - return value; -} -#elif defined(__IAR_SYSTEMS_ICC__) -int __rt_ffs(int value) -{ - if (value == 0) return value; - - asm("RBIT %0, %1" : "=r"(value) : "r"(value)); - asm("CLZ %0, %1" : "=r"(value) : "r"(value)); - asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value)); - - return value; -} -#elif defined(__GNUC__) -int __rt_ffs(int value) -{ - return __builtin_ffs(value); -} -#endif - -#endif diff --git a/rt-thread/libcpu/arm/cortex-m33/syscall_gcc.S b/rt-thread/libcpu/arm/cortex-m33/syscall_gcc.S deleted file mode 100644 index c648378..0000000 --- a/rt-thread/libcpu/arm/cortex-m33/syscall_gcc.S +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-10-25 tyx first version - */ - -.cpu cortex-m4 -.syntax unified -.thumb -.text - -/* - * int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2); - */ -.global tzcall -.type tzcall, %function -tzcall: - SVC 1 /* call SVC 1 */ - BX LR - -tzcall_entry: - PUSH {R1, R4, LR} - MOV R4, R1 /* copy thread SP to R4 */ - LDMFD R4!, {r0 - r3} /* pop user stack, get input arg0, arg1, arg2 */ - STMFD R4!, {r0 - r3} /* push stack, user stack recovery */ - BL rt_secure_svc_handle /* call fun */ - POP {R1, R4, LR} - STR R0, [R1] /* update return value */ - BX LR /* return to thread */ - -syscall_entry: - BX LR /* return to user app */ - -.global SVC_Handler -.type SVC_Handler, %function -SVC_Handler: - - /* get SP, save to R1 */ - MRS R1, MSP /* get fault context from handler. */ - TST LR, #0x04 /* if(!EXC_RETURN[2]) */ - BEQ get_sp_done - MRS R1, PSP /* get fault context from thread. */ -get_sp_done: - - /* get svc index */ - LDR R0, [R1, #24] - LDRB R0, [R0, #-2] - - /* if svc == 0, do system call */ - CMP R0, #0x0 - BEQ syscall_entry - - /* if svc == 1, do TrustZone call */ - CMP R0, #0x1 - BEQ tzcall_entry diff --git a/rt-thread/libcpu/arm/cortex-m33/syscall_iar.S b/rt-thread/libcpu/arm/cortex-m33/syscall_iar.S deleted file mode 100644 index 7a05861..0000000 --- a/rt-thread/libcpu/arm/cortex-m33/syscall_iar.S +++ /dev/null @@ -1,67 +0,0 @@ -;/* -; * Copyright (c) 2006-2022, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2019-10-25 tyx first version -; * 2021-03-26 lxf modify bad instruction -; */ - -;/* -; * @addtogroup cortex-m33 -; */ - - - SECTION .text:CODE(2) - THUMB - REQUIRE8 - PRESERVE8 - - IMPORT rt_secure_svc_handle - -;/* -; * int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2); -; */ - EXPORT tzcall -tzcall: - SVC 1 ;/* call SVC 1 */ - BX LR - -tzcall_entry: - PUSH {R1, R4, LR} - MOV R4, R1 ;/* copy thread SP to R4 */ - LDMFD R4!, {r0 - r3} ;/* pop user stack, get input arg0, arg1, arg2 */ - STMFD R4!, {r0 - r3} ;/* push stack, user stack recovery */ - BL rt_secure_svc_handle ;/* call fun */ - POP {R1, R4, LR} - STR R0, [R1] ;/* update return value */ - BX LR ;/* return to thread */ - -syscall_entry: - BX LR ;/* return to user app */ - - EXPORT SVC_Handler -SVC_Handler: - - ;/* get SP, save to R1 */ - MRS R1, MSP ;/* get fault context from handler. */ - TST LR, #0x04 ;/* if(!EXC_RETURN[2]) */ - BEQ get_sp_done - MRS R1, PSP ;/* get fault context from thread. */ -get_sp_done: - - ;/* get svc index */ - LDR R0, [R1, #24] - LDRB R0, [R0, #-2] - - ;/* if svc == 0, do system call */ - CMP R0, #0x0 - BEQ syscall_entry - - ;/* if svc == 1, do TrustZone call */ - CMP R0, #0x1 - BEQ tzcall_entry - - END diff --git a/rt-thread/libcpu/arm/cortex-m33/syscall_rvds.S b/rt-thread/libcpu/arm/cortex-m33/syscall_rvds.S deleted file mode 100644 index 9189deb..0000000 --- a/rt-thread/libcpu/arm/cortex-m33/syscall_rvds.S +++ /dev/null @@ -1,74 +0,0 @@ -;/* -; * Copyright (c) 2006-2022, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2019-10-25 tyx first version -; */ - - AREA |.text|, CODE, READONLY, ALIGN=2 - THUMB - REQUIRE8 - PRESERVE8 - - IMPORT rt_secure_svc_handle - -;/* -; * int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2); -; */ -tzcall PROC - EXPORT tzcall - SVC 1 ;call SVC 1 - BX LR - - ENDP - -tzcall_entry PROC - PUSH {R1, R4, LR} - MOV R4, R1 ; copy thread SP to R4 - LDMFD R4!, {r0 - r3} ; pop user stack, get input arg0, arg1, arg2 - STMFD R4!, {r0 - r3} ; push stack, user stack recovery - BL rt_secure_svc_handle ; call fun - POP {R1, R4, LR} - STR R0, [R1] ; update return value - BX LR ; return to thread - - ENDP - -syscall_entry PROC - BX LR ; return to user app - - ENDP - -;/* -; * void SVC_Handler(void); -; */ -SVC_Handler PROC - EXPORT SVC_Handler - - ; get SP, save to R1 - MRS R1, MSP ;get fault context from handler - TST LR, #0x04 ;if(!EXC_RETURN[2]) - BEQ get_sp_done - MRS R1, PSP ;get fault context from thread -get_sp_done - - ; get svc index - LDR R0, [R1, #24] - LDRB R0, [R0, #-2] - - ;if svc == 0, do system call - CMP R0, #0x0 - BEQ syscall_entry - - ;if svc == 1, do TrustZone call - CMP R0, #0x1 - BEQ tzcall_entry - - ENDP - - ALIGN - - END diff --git a/rt-thread/libcpu/arm/cortex-m33/trustzone.c b/rt-thread/libcpu/arm/cortex-m33/trustzone.c deleted file mode 100644 index 6c00a1f..0000000 --- a/rt-thread/libcpu/arm/cortex-m33/trustzone.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-10-28 tyx the first version. - */ - -#include - -#ifdef ARM_CM33_ENABLE_TRUSTZONE -extern void TZ_InitContextSystem_S(void); -extern rt_uint32_t TZ_AllocModuleContext_S (rt_uint32_t module); -extern rt_uint32_t TZ_FreeModuleContext_S(rt_uint32_t id); -extern rt_uint32_t TZ_LoadContext_S(rt_uint32_t id); -extern rt_uint32_t TZ_StoreContext_S(rt_uint32_t id); -#else -void TZ_InitContextSystem_S(void){} -rt_uint32_t TZ_AllocModuleContext_S (rt_uint32_t module){return 0;} -rt_uint32_t TZ_FreeModuleContext_S(rt_uint32_t id) {return 0;} -rt_uint32_t TZ_LoadContext_S(rt_uint32_t id){return 0;}; -rt_uint32_t TZ_StoreContext_S(rt_uint32_t id){return 0;}; -#endif -extern int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2); - -#define TZ_INIT_CONTEXT_ID (0x1001) -#define TZ_ALLOC_CONTEXT_ID (0x1002) -#define TZ_FREE_CONTEXT_ID (0x1003) - -rt_ubase_t rt_trustzone_current_context; - -void rt_trustzone_init(void) -{ - static rt_uint8_t _init; - - if (_init) - return; - tzcall(TZ_INIT_CONTEXT_ID, 0, 0, 0); - _init = 1; -} - -rt_err_t rt_trustzone_enter(rt_ubase_t module) -{ - rt_trustzone_init(); - if (tzcall(TZ_ALLOC_CONTEXT_ID, module, 0, 0)) - { - return RT_EOK; - } - return -RT_ERROR; -} - -rt_err_t rt_trustzone_exit(void) -{ - tzcall(TZ_FREE_CONTEXT_ID, 0, 0, 0); - return RT_EOK; -} - -void rt_trustzone_context_store(rt_ubase_t context) -{ - TZ_StoreContext_S(context); -} - -void rt_trustzone_context_load(rt_ubase_t context) -{ - TZ_LoadContext_S(context); -} - -int rt_secure_svc_handle(int svc_id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2) -{ - int res = 0; - - switch (svc_id) - { - case TZ_INIT_CONTEXT_ID: - TZ_InitContextSystem_S(); - break; - case TZ_ALLOC_CONTEXT_ID: - res = TZ_AllocModuleContext_S(arg0); - if (res <= 0) - { - rt_kprintf("Alloc Context Failed\n"); - } - else - { - rt_trustzone_current_context = res; - TZ_LoadContext_S(res); - } - break; - case TZ_FREE_CONTEXT_ID: - TZ_FreeModuleContext_S(rt_trustzone_current_context); - rt_trustzone_current_context = 0; - break; - } - return res; -} - diff --git a/rt-thread/libcpu/arm/cortex-m7/SConscript b/rt-thread/libcpu/arm/cortex-m7/SConscript deleted file mode 100644 index b259a94..0000000 --- a/rt-thread/libcpu/arm/cortex-m7/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/cortex-m7/context_gcc.S b/rt-thread/libcpu/arm/cortex-m7/context_gcc.S deleted file mode 100644 index 8475d33..0000000 --- a/rt-thread/libcpu/arm/cortex-m7/context_gcc.S +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-10-11 Bernard first version - * 2012-01-01 aozima support context switch load/store FPU register. - * 2013-06-18 aozima add restore MSP feature. - * 2013-06-23 aozima support lazy stack optimized. - * 2018-07-24 aozima enhancement hard fault exception handler. - */ - -/** - * @addtogroup cortex-m4 - */ -/*@{*/ - -.cpu cortex-m4 -.syntax unified -.thumb -.text - -.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ -.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ -.equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */ -.equ NVIC_PENDSV_PRI, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */ -.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ - -/* - * rt_base_t rt_hw_interrupt_disable(); - */ -.global rt_hw_interrupt_disable -.type rt_hw_interrupt_disable, %function -rt_hw_interrupt_disable: - MRS r0, PRIMASK - CPSID I - BX LR - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ -.global rt_hw_interrupt_enable -.type rt_hw_interrupt_enable, %function -rt_hw_interrupt_enable: - MSR PRIMASK, r0 - BX LR - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to - */ -.global rt_hw_context_switch_interrupt -.type rt_hw_context_switch_interrupt, %function -.global rt_hw_context_switch -.type rt_hw_context_switch, %function - -rt_hw_context_switch_interrupt: -rt_hw_context_switch: - /* set rt_thread_switch_interrupt_flag to 1 */ - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 - STR r3, [r2] - - LDR r2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - STR r0, [r2] - -_reswitch: - LDR r2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - STR r1, [r2] - - LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - BX LR - -/* r0 --> switch from thread stack - * r1 --> switch to thread stack - * psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack - */ -.global PendSV_Handler -.type PendSV_Handler, %function -PendSV_Handler: - /* disable interrupt to protect context switch */ - MRS r2, PRIMASK - CPSID I - - /* get rt_thread_switch_interrupt_flag */ - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CBZ r1, pendsv_exit /* pendsv already handled */ - - /* clear rt_thread_switch_interrupt_flag to 0 */ - MOV r1, #0x00 - STR r1, [r0] - - LDR r0, =rt_interrupt_from_thread - LDR r1, [r0] - CBZ r1, switch_to_thread /* skip register save at the first time */ - - MRS r1, psp /* get from thread stack pointer */ - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - TST lr, #0x10 /* if(!EXC_RETURN[4]) */ - IT EQ - VSTMDBEQ r1!, {d8 - d15} /* push FPU register s16~s31 */ -#endif - - STMFD r1!, {r4 - r11} /* push r4 - r11 register */ - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - MOV r4, #0x00 /* flag = 0 */ - - TST lr, #0x10 /* if(!EXC_RETURN[4]) */ - IT EQ - MOVEQ r4, #0x01 /* flag = 1 */ - - STMFD r1!, {r4} /* push flag */ -#endif - - LDR r0, [r0] - STR r1, [r0] /* update from thread stack pointer */ - -switch_to_thread: - LDR r1, =rt_interrupt_to_thread - LDR r1, [r1] - LDR r1, [r1] /* load thread stack pointer */ - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - LDMFD r1!, {r3} /* pop flag */ -#endif - - LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */ - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - CMP r3, #0 /* if(flag_r3 != 0) */ - IT NE - VLDMIANE r1!, {d8 - d15} /* pop FPU register s16~s31 */ -#endif - - MSR psp, r1 /* update stack pointer */ - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - ORR lr, lr, #0x10 /* lr |= (1 << 4), clean FPCA. */ - CMP r3, #0 /* if(flag_r3 != 0) */ - IT NE - BICNE lr, lr, #0x10 /* lr &= ~(1 << 4), set FPCA. */ -#endif - -pendsv_exit: - /* restore interrupt */ - MSR PRIMASK, r2 - - ORR lr, lr, #0x04 - BX lr - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to - */ -.global rt_hw_context_switch_to -.type rt_hw_context_switch_to, %function -rt_hw_context_switch_to: - LDR r1, =rt_interrupt_to_thread - STR r0, [r1] - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - /* CLEAR CONTROL.FPCA */ - MRS r2, CONTROL /* read */ - BIC r2, #0x04 /* modify */ - MSR CONTROL, r2 /* write-back */ -#endif - - /* set from thread to 0 */ - LDR r1, =rt_interrupt_from_thread - MOV r0, #0x0 - STR r0, [r1] - - /* set interrupt flag to 1 */ - LDR r1, =rt_thread_switch_interrupt_flag - MOV r0, #1 - STR r0, [r1] - - /* set the PendSV and SysTick exception priority */ - LDR r0, =NVIC_SYSPRI2 - LDR r1, =NVIC_PENDSV_PRI - LDR.W r2, [r0,#0x00] /* read */ - ORR r1,r1,r2 /* modify */ - STR r1, [r0] /* write-back */ - - LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - - /* restore MSP */ - LDR r0, =SCB_VTOR - LDR r0, [r0] - LDR r0, [r0] - NOP - MSR msp, r0 - - /* enable interrupts at processor level */ - CPSIE F - CPSIE I - - /* ensure PendSV exception taken place before subsequent operation */ - DSB - ISB - - /* never reach here! */ - -/* compatible with old version */ -.global rt_hw_interrupt_thread_switch -.type rt_hw_interrupt_thread_switch, %function -rt_hw_interrupt_thread_switch: - BX lr - NOP - -.global HardFault_Handler -.type HardFault_Handler, %function -HardFault_Handler: - /* get current context */ - MRS r0, msp /* get fault context from handler. */ - TST lr, #0x04 /* if(!EXC_RETURN[2]) */ - BEQ _get_sp_done - MRS r0, psp /* get fault context from thread. */ -_get_sp_done: - - STMFD r0!, {r4 - r11} /* push r4 - r11 register */ -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - STMFD r0!, {lr} /* push dummy for flag */ -#endif - STMFD r0!, {lr} /* push exec_return register */ - - TST lr, #0x04 /* if(!EXC_RETURN[2]) */ - BEQ _update_msp - MSR psp, r0 /* update stack pointer to PSP. */ - B _update_done -_update_msp: - MSR msp, r0 /* update stack pointer to MSP. */ -_update_done: - - PUSH {LR} - BL rt_hw_hard_fault_exception - POP {LR} - - ORR lr, lr, #0x04 - BX lr diff --git a/rt-thread/libcpu/arm/cortex-m7/context_iar.S b/rt-thread/libcpu/arm/cortex-m7/context_iar.S deleted file mode 100644 index 30be2b7..0000000 --- a/rt-thread/libcpu/arm/cortex-m7/context_iar.S +++ /dev/null @@ -1,257 +0,0 @@ -;/* -; * Copyright (c) 2006-2018, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2009-01-17 Bernard first version -; * 2009-09-27 Bernard add protect when contex switch occurs -; * 2012-01-01 aozima support context switch load/store FPU register. -; * 2013-06-18 aozima add restore MSP feature. -; * 2013-06-23 aozima support lazy stack optimized. -; * 2018-07-24 aozima enhancement hard fault exception handler. -; */ - -;/** -; * @addtogroup cortex-m4 -; */ -;/*@{*/ - -SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register -NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register -NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) -NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception - - SECTION .text:CODE(2) - THUMB - REQUIRE8 - PRESERVE8 - - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ - EXPORT rt_hw_interrupt_disable -rt_hw_interrupt_disable: - MRS r0, PRIMASK - CPSID I - BX LR - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ - EXPORT rt_hw_interrupt_enable -rt_hw_interrupt_enable: - MSR PRIMASK, r0 - BX LR - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ - EXPORT rt_hw_context_switch_interrupt - EXPORT rt_hw_context_switch -rt_hw_context_switch_interrupt: -rt_hw_context_switch: - ; set rt_thread_switch_interrupt_flag to 1 - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 - STR r3, [r2] - - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] - -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - BX LR - -; r0 --> switch from thread stack -; r1 --> switch to thread stack -; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack - EXPORT PendSV_Handler -PendSV_Handler: - - ; disable interrupt to protect context switch - MRS r2, PRIMASK - CPSID I - - ; get rt_thread_switch_interrupt_flag - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CBZ r1, pendsv_exit ; pendsv already handled - - ; clear rt_thread_switch_interrupt_flag to 0 - MOV r1, #0x00 - STR r1, [r0] - - LDR r0, =rt_interrupt_from_thread - LDR r1, [r0] - CBZ r1, switch_to_thread ; skip register save at the first time - - MRS r1, psp ; get from thread stack pointer - -#if defined ( __ARMVFP__ ) - TST lr, #0x10 ; if(!EXC_RETURN[4]) - BNE skip_push_fpu - VSTMDB r1!, {d8 - d15} ; push FPU register s16~s31 -skip_push_fpu -#endif - - STMFD r1!, {r4 - r11} ; push r4 - r11 register - -#if defined ( __ARMVFP__ ) - MOV r4, #0x00 ; flag = 0 - TST lr, #0x10 ; if(!EXC_RETURN[4]) - BNE push_flag - MOV r4, #0x01 ; flag = 1 -push_flag - ;STMFD r1!, {r4} ; push flag - SUB r1, r1, #0x04 - STR r4, [r1] -#endif - - LDR r0, [r0] - STR r1, [r0] ; update from thread stack pointer - -switch_to_thread - LDR r1, =rt_interrupt_to_thread - LDR r1, [r1] - LDR r1, [r1] ; load thread stack pointer - -#if defined ( __ARMVFP__ ) - LDMFD r1!, {r3} ; pop flag -#endif - - LDMFD r1!, {r4 - r11} ; pop r4 - r11 register - -#if defined ( __ARMVFP__ ) - CBZ r3, skip_pop_fpu - VLDMIA r1!, {d8 - d15} ; pop FPU register s16~s31 -skip_pop_fpu -#endif - - MSR psp, r1 ; update stack pointer - -#if defined ( __ARMVFP__ ) - ORR lr, lr, #0x10 ; lr |= (1 << 4), clean FPCA. - CBZ r3, return_without_fpu ; if(flag_r3 != 0) - BIC lr, lr, #0x10 ; lr &= ~(1 << 4), set FPCA. -return_without_fpu -#endif - -pendsv_exit - ; restore interrupt - MSR PRIMASK, r2 - - ORR lr, lr, #0x04 - BX lr - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; */ - EXPORT rt_hw_context_switch_to -rt_hw_context_switch_to: - LDR r1, =rt_interrupt_to_thread - STR r0, [r1] - -#if defined ( __ARMVFP__ ) - ; CLEAR CONTROL.FPCA - MRS r2, CONTROL ; read - BIC r2, r2, #0x04 ; modify - MSR CONTROL, r2 ; write-back -#endif - - ; set from thread to 0 - LDR r1, =rt_interrupt_from_thread - MOV r0, #0x0 - STR r0, [r1] - - ; set interrupt flag to 1 - LDR r1, =rt_thread_switch_interrupt_flag - MOV r0, #1 - STR r0, [r1] - - ; set the PendSV and SysTick exception priority - LDR r0, =NVIC_SYSPRI2 - LDR r1, =NVIC_PENDSV_PRI - LDR.W r2, [r0,#0x00] ; read - ORR r1,r1,r2 ; modify - STR r1, [r0] ; write-back - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - - ; restore MSP - LDR r0, =SCB_VTOR - LDR r0, [r0] - LDR r0, [r0] - NOP - MSR msp, r0 - - ; enable interrupts at processor level - CPSIE F - CPSIE I - - ; ensure PendSV exception taken place before subsequent operation - DSB - ISB - - ; never reach here! - -; compatible with old version - EXPORT rt_hw_interrupt_thread_switch -rt_hw_interrupt_thread_switch: - BX lr - - IMPORT rt_hw_hard_fault_exception - EXPORT HardFault_Handler -HardFault_Handler: - - ; get current context - MRS r0, msp ; get fault context from handler. - TST lr, #0x04 ; if(!EXC_RETURN[2]) - BEQ _get_sp_done - MRS r0, psp ; get fault context from thread. -_get_sp_done - - STMFD r0!, {r4 - r11} ; push r4 - r11 register - ;STMFD r0!, {lr} ; push exec_return register -#if defined ( __ARMVFP__ ) - SUB r0, r0, #0x04 ; push dummy for flag - STR lr, [r0] -#endif - SUB r0, r0, #0x04 - STR lr, [r0] - - TST lr, #0x04 ; if(!EXC_RETURN[2]) - BEQ _update_msp - MSR psp, r0 ; update stack pointer to PSP. - B _update_done -_update_msp - MSR msp, r0 ; update stack pointer to MSP. -_update_done - - PUSH {lr} - BL rt_hw_hard_fault_exception - POP {lr} - - ORR lr, lr, #0x04 - BX lr - - END diff --git a/rt-thread/libcpu/arm/cortex-m7/context_rvds.S b/rt-thread/libcpu/arm/cortex-m7/context_rvds.S deleted file mode 100644 index a507593..0000000 --- a/rt-thread/libcpu/arm/cortex-m7/context_rvds.S +++ /dev/null @@ -1,257 +0,0 @@ -;/* -; * Copyright (c) 2006-2018, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2009-01-17 Bernard first version. -; * 2012-01-01 aozima support context switch load/store FPU register. -; * 2013-06-18 aozima add restore MSP feature. -; * 2013-06-23 aozima support lazy stack optimized. -; * 2018-07-24 aozima enhancement hard fault exception handler. -; */ - -;/** -; * @addtogroup cortex-m4 -; */ -;/*@{*/ - -SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register -NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register -NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) -NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception - - AREA |.text|, CODE, READONLY, ALIGN=2 - THUMB - REQUIRE8 - PRESERVE8 - - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ -rt_hw_interrupt_disable PROC - EXPORT rt_hw_interrupt_disable - MRS r0, PRIMASK - CPSID I - BX LR - ENDP - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ -rt_hw_interrupt_enable PROC - EXPORT rt_hw_interrupt_enable - MSR PRIMASK, r0 - BX LR - ENDP - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ -rt_hw_context_switch_interrupt - EXPORT rt_hw_context_switch_interrupt -rt_hw_context_switch PROC - EXPORT rt_hw_context_switch - - ; set rt_thread_switch_interrupt_flag to 1 - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 - STR r3, [r2] - - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] - -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - - LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - BX LR - ENDP - -; r0 --> switch from thread stack -; r1 --> switch to thread stack -; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack -PendSV_Handler PROC - EXPORT PendSV_Handler - - ; disable interrupt to protect context switch - MRS r2, PRIMASK - CPSID I - - ; get rt_thread_switch_interrupt_flag - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CBZ r1, pendsv_exit ; pendsv already handled - - ; clear rt_thread_switch_interrupt_flag to 0 - MOV r1, #0x00 - STR r1, [r0] - - LDR r0, =rt_interrupt_from_thread - LDR r1, [r0] - CBZ r1, switch_to_thread ; skip register save at the first time - - MRS r1, psp ; get from thread stack pointer - - IF {FPU} != "SoftVFP" - TST lr, #0x10 ; if(!EXC_RETURN[4]) - VSTMFDEQ r1!, {d8 - d15} ; push FPU register s16~s31 - ENDIF - - STMFD r1!, {r4 - r11} ; push r4 - r11 register - - IF {FPU} != "SoftVFP" - MOV r4, #0x00 ; flag = 0 - - TST lr, #0x10 ; if(!EXC_RETURN[4]) - MOVEQ r4, #0x01 ; flag = 1 - - STMFD r1!, {r4} ; push flag - ENDIF - - LDR r0, [r0] - STR r1, [r0] ; update from thread stack pointer - -switch_to_thread - LDR r1, =rt_interrupt_to_thread - LDR r1, [r1] - LDR r1, [r1] ; load thread stack pointer - - IF {FPU} != "SoftVFP" - LDMFD r1!, {r3} ; pop flag - ENDIF - - LDMFD r1!, {r4 - r11} ; pop r4 - r11 register - - IF {FPU} != "SoftVFP" - CMP r3, #0 ; if(flag_r3 != 0) - VLDMFDNE r1!, {d8 - d15} ; pop FPU register s16~s31 - ENDIF - - MSR psp, r1 ; update stack pointer - - IF {FPU} != "SoftVFP" - ORR lr, lr, #0x10 ; lr |= (1 << 4), clean FPCA. - CMP r3, #0 ; if(flag_r3 != 0) - BICNE lr, lr, #0x10 ; lr &= ~(1 << 4), set FPCA. - ENDIF - -pendsv_exit - ; restore interrupt - MSR PRIMASK, r2 - - ORR lr, lr, #0x04 - BX lr - ENDP - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; * this fucntion is used to perform the first thread switch -; */ -rt_hw_context_switch_to PROC - EXPORT rt_hw_context_switch_to - ; set to thread - LDR r1, =rt_interrupt_to_thread - STR r0, [r1] - - IF {FPU} != "SoftVFP" - ; CLEAR CONTROL.FPCA - MRS r2, CONTROL ; read - BIC r2, #0x04 ; modify - MSR CONTROL, r2 ; write-back - ENDIF - - ; set from thread to 0 - LDR r1, =rt_interrupt_from_thread - MOV r0, #0x0 - STR r0, [r1] - - ; set interrupt flag to 1 - LDR r1, =rt_thread_switch_interrupt_flag - MOV r0, #1 - STR r0, [r1] - - ; set the PendSV and SysTick exception priority - LDR r0, =NVIC_SYSPRI2 - LDR r1, =NVIC_PENDSV_PRI - LDR.W r2, [r0,#0x00] ; read - ORR r1,r1,r2 ; modify - STR r1, [r0] ; write-back - - ; trigger the PendSV exception (causes context switch) - LDR r0, =NVIC_INT_CTRL - LDR r1, =NVIC_PENDSVSET - STR r1, [r0] - - ; restore MSP - LDR r0, =SCB_VTOR - LDR r0, [r0] - LDR r0, [r0] - MSR msp, r0 - - ; enable interrupts at processor level - CPSIE F - CPSIE I - - ; ensure PendSV exception taken place before subsequent operation - DSB - ISB - - ; never reach here! - ENDP - -; compatible with old version -rt_hw_interrupt_thread_switch PROC - EXPORT rt_hw_interrupt_thread_switch - BX lr - ENDP - - IMPORT rt_hw_hard_fault_exception - EXPORT HardFault_Handler - EXPORT MemManage_Handler -HardFault_Handler PROC -MemManage_Handler - - ; get current context - TST lr, #0x04 ; if(!EXC_RETURN[2]) - ITE EQ - MRSEQ r0, msp ; [2]=0 ==> Z=1, get fault context from handler. - MRSNE r0, psp ; [2]=1 ==> Z=0, get fault context from thread. - - STMFD r0!, {r4 - r11} ; push r4 - r11 register - IF {FPU} != "SoftVFP" - STMFD r0!, {lr} ; push dummy for flag - ENDIF - STMFD r0!, {lr} ; push exec_return register - - TST lr, #0x04 ; if(!EXC_RETURN[2]) - ITE EQ - MSREQ msp, r0 ; [2]=0 ==> Z=1, update stack pointer to MSP. - MSRNE psp, r0 ; [2]=1 ==> Z=0, update stack pointer to PSP. - - PUSH {lr} - BL rt_hw_hard_fault_exception - POP {lr} - - ORR lr, lr, #0x04 - BX lr - ENDP - - ALIGN 4 - - END diff --git a/rt-thread/libcpu/arm/cortex-m7/cpu_cache.c b/rt-thread/libcpu/arm/cortex-m7/cpu_cache.c deleted file mode 100644 index a6c0d62..0000000 --- a/rt-thread/libcpu/arm/cortex-m7/cpu_cache.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-04-02 tanek first implementation - * 2019-04-27 misonyo update to cortex-m7 series - */ - -#include -#include -#include - -/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */ -#define L1CACHE_LINESIZE_BYTE (32) - -void rt_hw_cpu_icache_enable(void) -{ - SCB_EnableICache(); -} - -void rt_hw_cpu_icache_disable(void) -{ - SCB_DisableICache(); -} - -rt_base_t rt_hw_cpu_icache_status(void) -{ - return 0; -} - -void rt_hw_cpu_icache_ops(int ops, void* addr, int size) -{ - rt_uint32_t address = (rt_uint32_t)addr & (rt_uint32_t) ~(L1CACHE_LINESIZE_BYTE - 1); - rt_int32_t size_byte = size + address - (rt_uint32_t)addr; - rt_uint32_t linesize = 32U; - if (ops & RT_HW_CACHE_INVALIDATE) - { - __DSB(); - while (size_byte > 0) - { - SCB->ICIMVAU = address; - address += linesize; - size_byte -= linesize; - } - __DSB(); - __ISB(); - } -} - -void rt_hw_cpu_dcache_enable(void) -{ - SCB_EnableDCache(); -} - -void rt_hw_cpu_dcache_disable(void) -{ - SCB_DisableDCache(); -} - -rt_base_t rt_hw_cpu_dcache_status(void) -{ - return 0; -} - -void rt_hw_cpu_dcache_ops(int ops, void* addr, int size) -{ - rt_uint32_t startAddr = (rt_uint32_t)addr & (rt_uint32_t)~(L1CACHE_LINESIZE_BYTE - 1); - rt_uint32_t size_byte = size + (rt_uint32_t)addr - startAddr; - rt_uint32_t clean_invalid = RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE; - - if ((ops & clean_invalid) == clean_invalid) - { - SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size_byte); - } - else if (ops & RT_HW_CACHE_FLUSH) - { - SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size_byte); - } - else if (ops & RT_HW_CACHE_INVALIDATE) - { - SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size_byte); - } - else - { - RT_ASSERT(0); - } -} diff --git a/rt-thread/libcpu/arm/cortex-m7/cpuport.c b/rt-thread/libcpu/arm/cortex-m7/cpuport.c deleted file mode 100644 index 274cc19..0000000 --- a/rt-thread/libcpu/arm/cortex-m7/cpuport.c +++ /dev/null @@ -1,508 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-10-21 Bernard the first version. - * 2011-10-27 aozima update for cortex-M4 FPU. - * 2011-12-31 aozima fixed stack align issues. - * 2012-01-01 aozima support context switch load/store FPU register. - * 2012-12-11 lgnq fixed the coding style. - * 2012-12-23 aozima stack addr align to 8byte. - * 2012-12-29 Bernard Add exception hook. - * 2013-06-23 aozima support lazy stack optimized. - * 2018-07-24 aozima enhancement hard fault exception handler. - * 2019-07-03 yangjie add __rt_ffs() for armclang. - */ - -#include - -#if /* ARMCC */ ( (defined ( __CC_ARM ) && defined ( __TARGET_FPU_VFP )) \ - /* Clang */ || (defined ( __clang__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) \ - /* IAR */ || (defined ( __ICCARM__ ) && defined ( __ARMVFP__ )) \ - /* GNU */ || (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) ) -#define USE_FPU 1 -#else -#define USE_FPU 0 -#endif - -/* exception and interrupt handler table */ -rt_uint32_t rt_interrupt_from_thread; -rt_uint32_t rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; -/* exception hook */ -static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL; - -struct exception_stack_frame -{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r12; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t psr; -}; - -struct stack_frame -{ -#if USE_FPU - rt_uint32_t flag; -#endif /* USE_FPU */ - - /* r4 ~ r11 register */ - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t r11; - - struct exception_stack_frame exception_stack_frame; -}; - -struct exception_stack_frame_fpu -{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r12; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t psr; - -#if USE_FPU - /* FPU register */ - rt_uint32_t S0; - rt_uint32_t S1; - rt_uint32_t S2; - rt_uint32_t S3; - rt_uint32_t S4; - rt_uint32_t S5; - rt_uint32_t S6; - rt_uint32_t S7; - rt_uint32_t S8; - rt_uint32_t S9; - rt_uint32_t S10; - rt_uint32_t S11; - rt_uint32_t S12; - rt_uint32_t S13; - rt_uint32_t S14; - rt_uint32_t S15; - rt_uint32_t FPSCR; - rt_uint32_t NO_NAME; -#endif -}; - -struct stack_frame_fpu -{ - rt_uint32_t flag; - - /* r4 ~ r11 register */ - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t r11; - -#if USE_FPU - /* FPU register s16 ~ s31 */ - rt_uint32_t s16; - rt_uint32_t s17; - rt_uint32_t s18; - rt_uint32_t s19; - rt_uint32_t s20; - rt_uint32_t s21; - rt_uint32_t s22; - rt_uint32_t s23; - rt_uint32_t s24; - rt_uint32_t s25; - rt_uint32_t s26; - rt_uint32_t s27; - rt_uint32_t s28; - rt_uint32_t s29; - rt_uint32_t s30; - rt_uint32_t s31; -#endif - - struct exception_stack_frame_fpu exception_stack_frame; -}; - -rt_uint8_t *rt_hw_stack_init(void *tentry, - void *parameter, - rt_uint8_t *stack_addr, - void *texit) -{ - struct stack_frame *stack_frame; - rt_uint8_t *stk; - unsigned long i; - - stk = stack_addr + sizeof(rt_uint32_t); - stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8); - stk -= sizeof(struct stack_frame); - - stack_frame = (struct stack_frame *)stk; - - /* init all register */ - for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++) - { - ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef; - } - - stack_frame->exception_stack_frame.r0 = (unsigned long)parameter; /* r0 : argument */ - stack_frame->exception_stack_frame.r1 = 0; /* r1 */ - stack_frame->exception_stack_frame.r2 = 0; /* r2 */ - stack_frame->exception_stack_frame.r3 = 0; /* r3 */ - stack_frame->exception_stack_frame.r12 = 0; /* r12 */ - stack_frame->exception_stack_frame.lr = (unsigned long)texit; /* lr */ - stack_frame->exception_stack_frame.pc = (unsigned long)tentry; /* entry point, pc */ - stack_frame->exception_stack_frame.psr = 0x01000000L; /* PSR */ - -#if USE_FPU - stack_frame->flag = 0; -#endif /* USE_FPU */ - - /* return task's current stack address */ - return stk; -} - -/** - * This function set the hook, which is invoked on fault exception handling. - * - * @param exception_handle the exception handling hook function. - */ -void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context)) -{ - rt_exception_hook = exception_handle; -} - -#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */ -#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ -#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ -#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ -#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */ -#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */ - -#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ -#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ -#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */ - -#ifdef RT_USING_FINSH -static void usage_fault_track(void) -{ - rt_kprintf("usage fault:\n"); - rt_kprintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR); - - if(SCB_CFSR_UFSR & (1<<0)) - { - /* [0]:UNDEFINSTR */ - rt_kprintf("UNDEFINSTR "); - } - - if(SCB_CFSR_UFSR & (1<<1)) - { - /* [1]:INVSTATE */ - rt_kprintf("INVSTATE "); - } - - if(SCB_CFSR_UFSR & (1<<2)) - { - /* [2]:INVPC */ - rt_kprintf("INVPC "); - } - - if(SCB_CFSR_UFSR & (1<<3)) - { - /* [3]:NOCP */ - rt_kprintf("NOCP "); - } - - if(SCB_CFSR_UFSR & (1<<8)) - { - /* [8]:UNALIGNED */ - rt_kprintf("UNALIGNED "); - } - - if(SCB_CFSR_UFSR & (1<<9)) - { - /* [9]:DIVBYZERO */ - rt_kprintf("DIVBYZERO "); - } - - rt_kprintf("\n"); -} - -static void bus_fault_track(void) -{ - rt_kprintf("bus fault:\n"); - rt_kprintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR); - - if(SCB_CFSR_BFSR & (1<<0)) - { - /* [0]:IBUSERR */ - rt_kprintf("IBUSERR "); - } - - if(SCB_CFSR_BFSR & (1<<1)) - { - /* [1]:PRECISERR */ - rt_kprintf("PRECISERR "); - } - - if(SCB_CFSR_BFSR & (1<<2)) - { - /* [2]:IMPRECISERR */ - rt_kprintf("IMPRECISERR "); - } - - if(SCB_CFSR_BFSR & (1<<3)) - { - /* [3]:UNSTKERR */ - rt_kprintf("UNSTKERR "); - } - - if(SCB_CFSR_BFSR & (1<<4)) - { - /* [4]:STKERR */ - rt_kprintf("STKERR "); - } - - if(SCB_CFSR_BFSR & (1<<7)) - { - rt_kprintf("SCB->BFAR:%08X\n", SCB_BFAR); - } - else - { - rt_kprintf("\n"); - } -} - -static void mem_manage_fault_track(void) -{ - rt_kprintf("mem manage fault:\n"); - rt_kprintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR); - - if(SCB_CFSR_MFSR & (1<<0)) - { - /* [0]:IACCVIOL */ - rt_kprintf("IACCVIOL "); - } - - if(SCB_CFSR_MFSR & (1<<1)) - { - /* [1]:DACCVIOL */ - rt_kprintf("DACCVIOL "); - } - - if(SCB_CFSR_MFSR & (1<<3)) - { - /* [3]:MUNSTKERR */ - rt_kprintf("MUNSTKERR "); - } - - if(SCB_CFSR_MFSR & (1<<4)) - { - /* [4]:MSTKERR */ - rt_kprintf("MSTKERR "); - } - - if(SCB_CFSR_MFSR & (1<<7)) - { - /* [7]:MMARVALID */ - rt_kprintf("SCB->MMAR:%08X\n", SCB_MMAR); - } - else - { - rt_kprintf("\n"); - } -} - -static void hard_fault_track(void) -{ - if(SCB_HFSR & (1UL<<1)) - { - /* [1]:VECTBL, Indicates hard fault is caused by failed vector fetch. */ - rt_kprintf("failed vector fetch\n"); - } - - if(SCB_HFSR & (1UL<<30)) - { - /* [30]:FORCED, Indicates hard fault is taken because of bus fault, - memory management fault, or usage fault. */ - if(SCB_CFSR_BFSR) - { - bus_fault_track(); - } - - if(SCB_CFSR_MFSR) - { - mem_manage_fault_track(); - } - - if(SCB_CFSR_UFSR) - { - usage_fault_track(); - } - } - - if(SCB_HFSR & (1UL<<31)) - { - /* [31]:DEBUGEVT, Indicates hard fault is triggered by debug event. */ - rt_kprintf("debug event\n"); - } -} -#endif /* RT_USING_FINSH */ - -struct exception_info -{ - rt_uint32_t exc_return; - struct stack_frame stack_frame; -}; - -void rt_hw_hard_fault_exception(struct exception_info *exception_info) -{ -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - extern long list_thread(void); -#endif - struct exception_stack_frame *exception_stack = &exception_info->stack_frame.exception_stack_frame; - struct stack_frame *context = &exception_info->stack_frame; - - if (rt_exception_hook != RT_NULL) - { - rt_err_t result; - - result = rt_exception_hook(exception_stack); - if (result == RT_EOK) return; - } - - rt_kprintf("psr: 0x%08x\n", context->exception_stack_frame.psr); - - rt_kprintf("r00: 0x%08x\n", context->exception_stack_frame.r0); - rt_kprintf("r01: 0x%08x\n", context->exception_stack_frame.r1); - rt_kprintf("r02: 0x%08x\n", context->exception_stack_frame.r2); - rt_kprintf("r03: 0x%08x\n", context->exception_stack_frame.r3); - rt_kprintf("r04: 0x%08x\n", context->r4); - rt_kprintf("r05: 0x%08x\n", context->r5); - rt_kprintf("r06: 0x%08x\n", context->r6); - rt_kprintf("r07: 0x%08x\n", context->r7); - rt_kprintf("r08: 0x%08x\n", context->r8); - rt_kprintf("r09: 0x%08x\n", context->r9); - rt_kprintf("r10: 0x%08x\n", context->r10); - rt_kprintf("r11: 0x%08x\n", context->r11); - rt_kprintf("r12: 0x%08x\n", context->exception_stack_frame.r12); - rt_kprintf(" lr: 0x%08x\n", context->exception_stack_frame.lr); - rt_kprintf(" pc: 0x%08x\n", context->exception_stack_frame.pc); - - if (exception_info->exc_return & (1 << 2)) - { - rt_kprintf("hard fault on thread: %s\r\n\r\n", rt_thread_self()->name); - -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - } - else - { - rt_kprintf("hard fault on handler\r\n\r\n"); - } - - if ( (exception_info->exc_return & 0x10) == 0) - { - rt_kprintf("FPU active!\r\n"); - } - -#ifdef RT_USING_FINSH - hard_fault_track(); -#endif /* RT_USING_FINSH */ - - while (1); -} - -/** - * shutdown CPU - */ -RT_WEAK void rt_hw_cpu_shutdown(void) -{ - rt_kprintf("shutdown...\n"); - - RT_ASSERT(0); -} - -/** - * reset CPU - */ -RT_WEAK void rt_hw_cpu_reset(void) -{ - SCB_AIRCR = SCB_RESET_VALUE; -} - -#ifdef RT_USING_CPU_FFS -/** - * This function finds the first bit set (beginning with the least significant bit) - * in value and return the index of that bit. - * - * Bits are numbered starting at 1 (the least significant bit). A return value of - * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function - * shall return 0. - */ -#if defined(__CC_ARM) -__asm int __rt_ffs(int value) -{ - CMP r0, #0x00 - BEQ exit - - RBIT r0, r0 - CLZ r0, r0 - ADDS r0, r0, #0x01 - -exit - BX lr -} -#elif defined(__clang__) -int __rt_ffs(int value) -{ - __asm volatile( - "CMP %1, #0x00 \n" - "BEQ 1f \n" - - "RBIT %1, %1 \n" - "CLZ %0, %1 \n" - "ADDS %0, %0, #0x01 \n" - - "1: \n" - - : "=r"(value) - : "r"(value) - ); - return value; -} -#elif defined(__IAR_SYSTEMS_ICC__) -int __rt_ffs(int value) -{ - if (value == 0) return value; - - asm("RBIT %0, %1" : "=r"(value) : "r"(value)); - asm("CLZ %0, %1" : "=r"(value) : "r"(value)); - asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value)); - - return value; -} -#elif defined(__GNUC__) -int __rt_ffs(int value) -{ - return __builtin_ffs(value); -} -#endif - -#endif diff --git a/rt-thread/libcpu/arm/cortex-r4/SConscript b/rt-thread/libcpu/arm/cortex-r4/SConscript deleted file mode 100644 index b259a94..0000000 --- a/rt-thread/libcpu/arm/cortex-r4/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/cortex-r4/armv7.h b/rt-thread/libcpu/arm/cortex-r4/armv7.h deleted file mode 100644 index d29b41a..0000000 --- a/rt-thread/libcpu/arm/cortex-r4/armv7.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ -#ifndef __ARMV7_H__ -#define __ARMV7_H__ - -#ifndef VFP_DATA_NR -#define VFP_DATA_NR 32 -#endif - -/* the exception stack without VFP registers */ -struct rt_hw_exp_stack -{ - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; -}; - -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define MONITORMODE 0x16 -#define ABORTMODE 0x17 -#define HYPMODE 0x1b -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -#define T_Bit (1<<5) -#define F_Bit (1<<6) -#define I_Bit (1<<7) -#define A_Bit (1<<8) -#define E_Bit (1<<9) -#define J_Bit (1<<24) - -#endif diff --git a/rt-thread/libcpu/arm/cortex-r4/context_ccs.asm b/rt-thread/libcpu/arm/cortex-r4/context_ccs.asm deleted file mode 100644 index 6a734cb..0000000 --- a/rt-thread/libcpu/arm/cortex-r4/context_ccs.asm +++ /dev/null @@ -1,260 +0,0 @@ -;/* -; * Copyright (c) 2006-2022, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2009-01-20 Bernard first version -; * 2011-07-22 Bernard added thumb mode porting -; * 2013-05-24 Grissiom port to CCS -; * 2013-05-26 Grissiom optimize for ARMv7 -; */ - - .text - .arm - .ref rt_thread_switch_interrupt_flag - .ref rt_interrupt_from_thread - .ref rt_interrupt_to_thread - .ref rt_interrupt_enter - .ref rt_interrupt_leave - .ref rt_hw_trap_irq - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ - .def rt_hw_interrupt_disable - .asmfunc -rt_hw_interrupt_disable - MRS r0, cpsr - CPSID IF - BX lr - .endasmfunc - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ - .def rt_hw_interrupt_enable - .asmfunc -rt_hw_interrupt_enable - MSR cpsr_c, r0 - BX lr - .endasmfunc - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ - .def rt_hw_context_switch - .asmfunc -rt_hw_context_switch - STMDB sp!, {lr} ; push pc (lr should be pushed in place of PC) - STMDB sp!, {r0-r12, lr} ; push lr & register file - - MRS r4, cpsr - TST lr, #0x01 - ORRNE r4, r4, #0x20 ; it's thumb code - - STMDB sp!, {r4} ; push cpsr - - .if (__TI_VFP_SUPPORT__) - VMRS r4, fpexc - TST r4, #0x40000000 - BEQ __no_vfp_frame1 - VSTMDB sp!, {d0-d15} - VMRS r5, fpscr - ; TODO: add support for Common VFPv3. - ; Save registers like FPINST, FPINST2 - STMDB sp!, {r5} -__no_vfp_frame1 - STMDB sp!, {r4} - .endif - - STR sp, [r0] ; store sp in preempted tasks TCB - LDR sp, [r1] ; get new task stack pointer - - .if (__TI_VFP_SUPPORT__) - LDMIA sp!, {r0} ; get fpexc - VMSR fpexc, r0 ; restore fpexc - TST r0, #0x40000000 - BEQ __no_vfp_frame2 - LDMIA sp!, {r1} ; get fpscr - VMSR fpscr, r1 - VLDMIA sp!, {d0-d15} -__no_vfp_frame2 - .endif - - LDMIA sp!, {r4} ; pop new task cpsr to spsr - MSR spsr_cxsf, r4 - - LDMIA sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr - .endasmfunc - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; */ - .def rt_hw_context_switch_to - .asmfunc -rt_hw_context_switch_to - LDR sp, [r0] ; get new task stack pointer - - .if (__TI_VFP_SUPPORT__) - LDMIA sp!, {r0} ; get fpexc - VMSR fpexc, r0 - TST r0, #0x40000000 - BEQ __no_vfp_frame_to - LDMIA sp!, {r1} ; get fpscr - VMSR fpscr, r1 - VLDMIA sp!, {d0-d15} -__no_vfp_frame_to - .endif - - LDMIA sp!, {r4} ; pop new task cpsr to spsr - MSR spsr_cxsf, r4 - - LDMIA sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr - .endasmfunc - -;/* -; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); -; */ - - .def rt_hw_context_switch_interrupt - .asmfunc -rt_hw_context_switch_interrupt - LDR r2, pintflag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1 - STR r3, [r2] - LDR r2, pfromthread ; set rt_interrupt_from_thread - STR r0, [r2] -_reswitch - LDR r2, ptothread ; set rt_interrupt_to_thread - STR r1, [r2] - BX lr - .endasmfunc - - .def IRQ_Handler -IRQ_Handler - STMDB sp!, {r0-r12,lr} - - .if (__TI_VFP_SUPPORT__) - VMRS r0, fpexc - TST r0, #0x40000000 - BEQ __no_vfp_frame_str_irq - VSTMDB sp!, {d0-d15} - VMRS r1, fpscr - ; TODO: add support for Common VFPv3. - ; Save registers like FPINST, FPINST2 - STMDB sp!, {r1} -__no_vfp_frame_str_irq - STMDB sp!, {r0} - .endif - - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; if rt_thread_switch_interrupt_flag set, jump to - ; rt_hw_context_switch_interrupt_do and don't return - LDR r0, pintflag - LDR r1, [r0] - CMP r1, #1 - BEQ rt_hw_context_switch_interrupt_do - - .if (__TI_VFP_SUPPORT__) - LDMIA sp!, {r0} ; get fpexc - VMSR fpexc, r0 - TST r0, #0x40000000 - BEQ __no_vfp_frame_ldr_irq - LDMIA sp!, {r1} ; get fpscr - VMSR fpscr, r1 - VLDMIA sp!, {d0-d15} -__no_vfp_frame_ldr_irq - .endif - - LDMIA sp!, {r0-r12,lr} - SUBS pc, lr, #4 - -; /* -; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) -; */ - .def rt_hw_context_switch_interrupt_do -rt_hw_context_switch_interrupt_do - MOV r1, #0 ; clear flag - STR r1, [r0] - - .if (__TI_VFP_SUPPORT__) - LDMIA sp!, {r0} ; get fpexc - VMSR fpexc, r0 - TST r0, #0x40000000 - BEQ __no_vfp_frame_do1 - LDMIA sp!, {r1} ; get fpscr - VMSR fpscr, r1 - VLDMIA sp!, {d0-d15} -__no_vfp_frame_do1 - .endif - - LDMIA sp!, {r0-r12,lr} ; reload saved registers - STMDB sp, {r0-r3} ; save r0-r3. We will restore r0-r3 in the SVC - ; mode so there is no need to update SP. - SUB r1, sp, #16 ; save the right SP value in r1, so we could restore r0-r3. - SUB r2, lr, #4 ; save old task's pc to r2 - - MRS r3, spsr ; get cpsr of interrupt thread - - ; switch to SVC mode and no interrupt - CPSID IF, #0x13 - - STMDB sp!, {r2} ; push old task's pc - STMDB sp!, {r4-r12,lr} ; push old task's lr,r12-r4 - LDMIA r1!, {r4-r7} ; restore r0-r3 of the interrupted thread - STMDB sp!, {r4-r7} ; push old task's r3-r0. We don't need to push/pop them to - ; r0-r3 because we just want to transfer the data and don't - ; use them here. - STMDB sp!, {r3} ; push old task's cpsr - - .if (__TI_VFP_SUPPORT__) - VMRS r0, fpexc - TST r0, #0x40000000 - BEQ __no_vfp_frame_do2 - VSTMDB sp!, {d0-d15} - VMRS r1, fpscr - ; TODO: add support for Common VFPv3. - ; Save registers like FPINST, FPINST2 - STMDB sp!, {r1} -__no_vfp_frame_do2 - STMDB sp!, {r0} - .endif - - LDR r4, pfromthread - LDR r5, [r4] - STR sp, [r5] ; store sp in preempted tasks's TCB - - LDR r6, ptothread - LDR r6, [r6] - LDR sp, [r6] ; get new task's stack pointer - - .if (__TI_VFP_SUPPORT__) - LDMIA sp!, {r0} ; get fpexc - VMSR fpexc, r0 - TST r0, #0x40000000 - BEQ __no_vfp_frame_do3 - LDMIA sp!, {r1} ; get fpscr - VMSR fpscr, r1 - VLDMIA sp!, {d0-d15} -__no_vfp_frame_do3 - .endif - - LDMIA sp!, {r4} ; pop new task's cpsr to spsr - MSR spsr_cxsf, r4 - - LDMIA sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr - -pintflag .word rt_thread_switch_interrupt_flag -pfromthread .word rt_interrupt_from_thread -ptothread .word rt_interrupt_to_thread diff --git a/rt-thread/libcpu/arm/cortex-r4/context_gcc.S b/rt-thread/libcpu/arm/cortex-r4/context_gcc.S deleted file mode 100644 index a148fe9..0000000 --- a/rt-thread/libcpu/arm/cortex-r4/context_gcc.S +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-01-20 Bernard first version - * 2011-07-22 Bernard added thumb mode porting - * 2013-05-24 Grissiom port to CCS - * 2013-05-26 Grissiom optimize for ARMv7 - * 2013-10-20 Grissiom port to GCC - */ - -#include - - .text - .arm - .globl rt_thread_switch_interrupt_flag - .globl rt_interrupt_from_thread - .globl rt_interrupt_to_thread - .globl rt_interrupt_enter - .globl rt_interrupt_leave - .globl rt_hw_trap_irq - -/* - * rt_base_t rt_hw_interrupt_disable() - */ - .globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - MRS r0, cpsr - CPSID IF - BX lr - -/* - * void rt_hw_interrupt_enable(rt_base_t level) - */ - .globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - MSR cpsr_c, r0 - BX lr - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) - * r0 --> from - * r1 --> to - */ - .globl rt_hw_context_switch -rt_hw_context_switch: - STMDB sp!, {lr} @ push pc (lr should be pushed in place of PC) - STMDB sp!, {r0-r12, lr} @ push lr & register file - - MRS r4, cpsr - TST lr, #0x01 - ORRNE r4, r4, #0x20 @ it's thumb code - - STMDB sp!, {r4} @ push cpsr - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) - VMRS r4, fpexc - TST r4, #0x40000000 - BEQ __no_vfp_frame1 - VSTMDB sp!, {d0-d15} - VMRS r5, fpscr - @ TODO: add support for Common VFPv3. - @ Save registers like FPINST, FPINST2 - STMDB sp!, {r5} -__no_vfp_frame1: - STMDB sp!, {r4} -#endif - - STR sp, [r0] @ store sp in preempted tasks TCB - LDR sp, [r1] @ get new task stack pointer - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) - LDMIA sp!, {r0} @ get fpexc - VMSR fpexc, r0 @ restore fpexc - TST r0, #0x40000000 - BEQ __no_vfp_frame2 - LDMIA sp!, {r1} @ get fpscr - VMSR fpscr, r1 - VLDMIA sp!, {d0-d15} -__no_vfp_frame2: - #endif - - LDMIA sp!, {r4} @ pop new task cpsr to spsr - MSR spsr_cxsf, r4 - - LDMIA sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr - -/* - * void rt_hw_context_switch_to(rt_uint32 to) - * r0 --> to - */ - .globl rt_hw_context_switch_to -rt_hw_context_switch_to: - LDR sp, [r0] @ get new task stack pointer - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) - LDMIA sp!, {r0} @ get fpexc - VMSR fpexc, r0 - TST r0, #0x40000000 - BEQ __no_vfp_frame_to - LDMIA sp!, {r1} @ get fpscr - VMSR fpscr, r1 - VLDMIA sp!, {d0-d15} -__no_vfp_frame_to: -#endif - - LDMIA sp!, {r4} @ pop new task cpsr to spsr - MSR spsr_cxsf, r4 - - LDMIA sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)@ - */ - - .globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 @ set rt_thread_switch_interrupt_flag to 1 - STR r3, [r2] - LDR r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread - - STR r0, [r2] -_reswitch: - LDR r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread - STR r1, [r2] - BX lr - - .globl IRQ_Handler -IRQ_Handler: - STMDB sp!, {r0-r12,lr} - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) - VMRS r0, fpexc - TST r0, #0x40000000 - BEQ __no_vfp_frame_str_irq - VSTMDB sp!, {d0-d15} - VMRS r1, fpscr - @ TODO: add support for Common VFPv3. - @ Save registers like FPINST, FPINST2 - STMDB sp!, {r1} -__no_vfp_frame_str_irq: - STMDB sp!, {r0} -#endif - - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - @ if rt_thread_switch_interrupt_flag set, jump to - @ rt_hw_context_switch_interrupt_do and don't return - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #1 - BEQ rt_hw_context_switch_interrupt_do - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) - LDMIA sp!, {r0} @ get fpexc - VMSR fpexc, r0 - TST r0, #0x40000000 - BEQ __no_vfp_frame_ldr_irq - LDMIA sp!, {r1} @ get fpscr - VMSR fpscr, r1 - VLDMIA sp!, {d0-d15} -__no_vfp_frame_ldr_irq: -#endif - - LDMIA sp!, {r0-r12,lr} - SUBS pc, lr, #4 - -/* - * void rt_hw_context_switch_interrupt_do(rt_base_t flag) - */ - .globl rt_hw_context_switch_interrupt_do -rt_hw_context_switch_interrupt_do: - MOV r1, #0 @ clear flag - STR r1, [r0] - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) - LDMIA sp!, {r0} @ get fpexc - VMSR fpexc, r0 - TST r0, #0x40000000 - BEQ __no_vfp_frame_do1 - LDMIA sp!, {r1} @ get fpscr - VMSR fpscr, r1 - VLDMIA sp!, {d0-d15} -__no_vfp_frame_do1: -#endif - - LDMIA sp!, {r0-r12,lr} @ reload saved registers - STMDB sp, {r0-r3} @ save r0-r3. We will restore r0-r3 in the SVC - @ mode so there is no need to update SP. - SUB r1, sp, #16 @ save the right SP value in r1, so we could restore r0-r3. - SUB r2, lr, #4 @ save old task's pc to r2 - - MRS r3, spsr @ get cpsr of interrupt thread - - @ switch to SVC mode and no interrupt - CPSID IF, #0x13 - - STMDB sp!, {r2} @ push old task's pc - STMDB sp!, {r4-r12,lr} @ push old task's lr,r12-r4 - LDMIA r1!, {r4-r7} @ restore r0-r3 of the interrupted thread - STMDB sp!, {r4-r7} @ push old task's r3-r0. We don't need to push/pop them to - @ r0-r3 because we just want to transfer the data and don't - @ use them here. - STMDB sp!, {r3} @ push old task's cpsr - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) - VMRS r0, fpexc - TST r0, #0x40000000 - BEQ __no_vfp_frame_do2 - VSTMDB sp!, {d0-d15} - VMRS r1, fpscr - @ TODO: add support for Common VFPv3. - @ Save registers like FPINST, FPINST2 - STMDB sp!, {r1} -__no_vfp_frame_do2: - STMDB sp!, {r0} -#endif - - LDR r4, =rt_interrupt_from_thread - LDR r5, [r4] - STR sp, [r5] @ store sp in preempted tasks's TCB - - LDR r6, =rt_interrupt_to_thread - LDR r6, [r6] - LDR sp, [r6] @ get new task's stack pointer - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) - LDMIA sp!, {r0} @ get fpexc - VMSR fpexc, r0 - TST r0, #0x40000000 - BEQ __no_vfp_frame_do3 - LDMIA sp!, {r1} @ get fpscr - VMSR fpscr, r1 - VLDMIA sp!, {d0-d15} -__no_vfp_frame_do3: -#endif - - LDMIA sp!, {r4} @ pop new task's cpsr to spsr - MSR spsr_cxsf, r4 - - LDMIA sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr - diff --git a/rt-thread/libcpu/arm/cortex-r4/cpu.c b/rt-thread/libcpu/arm/cortex-r4/cpu.c deleted file mode 100644 index b63a077..0000000 --- a/rt-thread/libcpu/arm/cortex-r4/cpu.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2008-12-11 XuXinming first version - * 2013-05-24 Grissiom port to RM48x50 - */ - -#include - -/** - * @addtogroup RM48x50 - */ -/*@{*/ - -/** - * this function will reset CPU - * - */ -RT_WEAK void rt_hw_cpu_reset() -{ -} - -/** - * this function will shutdown CPU - * - */ -RT_WEAK void rt_hw_cpu_shutdown() -{ - rt_kprintf("shutdown...\n"); - - while (1); -} - -#ifdef __TI_COMPILER_VERSION__ -#ifdef RT_USING_CPU_FFS -int __rt_ffs(int value) -{ - if (value == 0) - return value; - - __asm(" rsb r1, r0, #0"); - __asm(" and r1, r1, r0"); - __asm(" clz r1, r1"); - __asm(" rsb r0, r1, #32"); -} -#endif - -void rt_hw_cpu_icache_enable() -{ - __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data"); - __asm(" ORR r1, r1, #0x1 <<12 ; instruction cache enable"); - __asm(" MCR p15, #0, r0, c7, c5, #0 ; Invalidate entire instruction cache, r0 is ignored"); - __asm(" MCR p15, #0, r1, c1, c0, #0 ; enabled instruction cache"); - __asm(" ISB"); -} - -void rt_hw_cpu_icache_disable() -{ - __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data"); - __asm(" BIC r1, r1, #0x1 <<12 ; instruction cache enable"); - __asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled instruction cache"); - __asm(" ISB"); -} - -void rt_hw_cpu_dcache_enable() -{ - __asm(" MRC p15, #0, R1, c1, c0, #0 ; Read SCTLR configuration data"); - __asm(" ORR R1, R1, #0x1 <<2"); - __asm(" DSB"); - __asm(" MCR p15, #0, r0, c15, c5, #0 ; Invalidate entire data cache"); - __asm(" MCR p15, #0, R1, c1, c0, #0 ; enabled data cache"); -} - -void rt_hw_cpu_dcache_disable() -{ - /* FIXME: Clean entire data cache. This routine depends on the data cache - * size. It can be omitted if it is known that the data cache has no dirty - * data. */ - __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data"); - __asm(" BIC r1, r1, #0x1 <<2"); - __asm(" DSB"); - __asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled data cache"); -} - -#elif __GNUC__ -#ifdef RT_USING_CPU_FFS -int __rt_ffs(int value) -{ - return __builtin_ffs(value); -} -#endif -#endif -/*@}*/ diff --git a/rt-thread/libcpu/arm/cortex-r4/interrupt.c b/rt-thread/libcpu/arm/cortex-r4/interrupt.c deleted file mode 100644 index 14a9023..0000000 --- a/rt-thread/libcpu/arm/cortex-r4/interrupt.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2008-12-11 XuXinming first version - * 2013-03-29 aozima Modify the interrupt interface implementations. - */ - -#include -#include - -#include -#include - -#include "armv7.h" - -#define MAX_HANDLERS 96 - -/* exception and interrupt handler table */ -struct rt_irq_desc irq_desc[MAX_HANDLERS]; - -extern volatile rt_uint8_t rt_interrupt_nest; - -/* exception and interrupt handler table */ -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -/** - * @addtogroup RM48x50 - */ - -/*@{*/ - -static void rt_hw_int_not_handle(int vector, void *param) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -#define vimRAM (0xFFF82000U) - -void rt_hw_interrupt_init(void) -{ - register int i; - - rt_uint32_t *vect_addr; - - /* the initialization is done in sys_startup.c */ - - /* init exceptions table */ - rt_memset(irq_desc, 0x00, sizeof(irq_desc)); - for(i=0; i < MAX_HANDLERS; i++) - { - irq_desc[i].handler = rt_hw_int_not_handle; - - vect_addr = (rt_uint32_t *)(vimRAM + i*4); - *vect_addr = (rt_uint32_t)&irq_desc[i]; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -void rt_hw_interrupt_mask(int vector) -{ - vimDisableInterrupt(vector); -} - -void rt_hw_interrupt_umask(int vector) -{ - vimEnableInterrupt(vector, SYS_IRQ); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param handler the interrupt service routine to be installed - * @param param the parameter for interrupt service routine - * @name unused. - * - * @return the old handler - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if(vector >= 0 && vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = handler; - irq_desc[vector].param = param; - } - } - - return old_handler; -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/cortex-r4/stack.c b/rt-thread/libcpu/arm/cortex-r4/stack.c deleted file mode 100644 index 539b47d..0000000 --- a/rt-thread/libcpu/arm/cortex-r4/stack.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2008-12-11 XuXinming first version - * 2013-05-24 Grissiom port to RM48x50 - */ -#include - -#include "armv7.h" -/** - * @addtogroup RM48x50 - */ -/*@{*/ - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - - stack_addr += sizeof(rt_uint32_t); - stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); - stk = (rt_uint32_t *)stack_addr; - *(--stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0xdeadbeef; /* r12 */ - *(--stk) = 0xdeadbeef; /* r11 */ - *(--stk) = 0xdeadbeef; /* r10 */ - *(--stk) = 0xdeadbeef; /* r9 */ - *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = 0xdeadbeef; /* r4 */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = 0xdeadbeef; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ - -#if defined(__TI_VFP_SUPPORT__) || (defined (__VFP_FP__) && !defined(__SOFTFP__)) -#ifndef RT_VFP_LAZY_STACKING - { - int i; - - for (i = 0; i < VFP_DATA_NR; i++) - { - *(--stk) = 0; - } - /* FPSCR TODO: do we need to set the values other than 0? */ - *(--stk) = 0; - /* FPEXC. Enable the FVP if no lazy stacking. */ - *(--stk) = 0x40000000; - } -#else - /* FPEXC. Disable the FVP by default. */ - *(--stk) = 0x00000000; -#endif -#endif - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/cortex-r4/start_ccs.asm b/rt-thread/libcpu/arm/cortex-r4/start_ccs.asm deleted file mode 100644 index 4436646..0000000 --- a/rt-thread/libcpu/arm/cortex-r4/start_ccs.asm +++ /dev/null @@ -1,552 +0,0 @@ -;------------------------------------------------------------------------------- -; sys_core.asm -; -; (c) Texas Instruments 2009-2013, All rights reserved. -; - - .text - .arm - - .ref _c_int00 - - .def _reset - .asmfunc -_reset -;------------------------------------------------------------------------------- -; Initialize CPU Registers -; After reset, the CPU is in the Supervisor mode (M = 10011) - mov r0, lr - mov r1, #0x0000 - mov r2, #0x0000 - mov r3, #0x0000 - mov r4, #0x0000 - mov r5, #0x0000 - mov r6, #0x0000 - mov r7, #0x0000 - mov r8, #0x0000 - mov r9, #0x0000 - mov r10, #0x0000 - mov r11, #0x0000 - mov r12, #0x0000 - mov r13, #0x0000 - mrs r1, cpsr - msr spsr_cxsf, r1 - ; Switch to FIQ mode (M = 10001) - cps #17 - mov lr, r0 - mov r8, #0x0000 - mov r9, #0x0000 - mov r10, #0x0000 - mov r11, #0x0000 - mov r12, #0x0000 - mrs r1, cpsr - msr spsr_cxsf, r1 - ; Switch to IRQ mode (M = 10010) - cps #18 - mov lr, r0 - mrs r1,cpsr - msr spsr_cxsf, r1 - ; Switch to Abort mode (M = 10111) - cps #23 - mov lr, r0 - mrs r1,cpsr - msr spsr_cxsf, r1 - ; Switch to Undefined Instruction Mode (M = 11011) - cps #27 - mov lr, r0 - mrs r1,cpsr - msr spsr_cxsf, r1 - ; Switch to System Mode ( Shares User Mode registers ) (M = 11111) - cps #31 - mov lr, r0 - mrs r1,cpsr - msr spsr_cxsf, r1 - ; Switch back to Supervisor Mode (M = 10011) - cps #19 - - ; Turn on FPV coprocessor - mrc p15, #0x00, r2, c1, c0, #0x02 - orr r2, r2, #0xF00000 - mcr p15, #0x00, r2, c1, c0, #0x02 - - .if (RT_VFP_LAZY_STACKING) = 0 - fmrx r2, fpexc - orr r2, r2, #0x40000000 - fmxr fpexc, r2 - - fmdrr d0, r1, r1 - fmdrr d1, r1, r1 - fmdrr d2, r1, r1 - fmdrr d3, r1, r1 - fmdrr d4, r1, r1 - fmdrr d5, r1, r1 - fmdrr d6, r1, r1 - fmdrr d7, r1, r1 - fmdrr d8, r1, r1 - fmdrr d9, r1, r1 - fmdrr d10, r1, r1 - fmdrr d11, r1, r1 - fmdrr d12, r1, r1 - fmdrr d13, r1, r1 - fmdrr d14, r1, r1 - fmdrr d15, r1, r1 - .endif - -;------------------------------------------------------------------------------- -; Initialize Stack Pointers - cps #17 - ldr sp, fiqSp - cps #18 - ldr sp, irqSp - cps #23 - ldr sp, abortSp - cps #27 - ldr sp, undefSp - cps #31 - ldr sp, userSp - cps #19 - ldr sp, svcSp - - bl next1 -next1 - bl next2 -next2 - bl next3 -next3 - bl next4 -next4 - ldr lr, int00ad - bx lr - -int00ad .word _c_int00 -userSp .word 0x08000000+0x00001000 -svcSp .word 0x08000000+0x00001000+0x00000100 -fiqSp .word 0x08000000+0x00001000+0x00000100+0x00000100 -irqSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100 -abortSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100 -undefSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100+0x00000100 - - .endasmfunc - -;------------------------------------------------------------------------------- -; Enable RAM ECC Support - - .def _coreEnableRamEcc_ - .asmfunc - -_coreEnableRamEcc_ - - stmfd sp!, {r0} - mrc p15, #0x00, r0, c1, c0, #0x01 - orr r0, r0, #0x0C000000 - mcr p15, #0x00, r0, c1, c0, #0x01 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Disable RAM ECC Support - - .def _coreDisableRamEcc_ - .asmfunc - -_coreDisableRamEcc_ - - stmfd sp!, {r0} - mrc p15, #0x00, r0, c1, c0, #0x01 - bic r0, r0, #0x0C000000 - mcr p15, #0x00, r0, c1, c0, #0x01 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Enable Flash ECC Support - - .def _coreEnableFlashEcc_ - .asmfunc - -_coreEnableFlashEcc_ - - stmfd sp!, {r0} - mrc p15, #0x00, r0, c1, c0, #0x01 - orr r0, r0, #0x02000000 - dmb - mcr p15, #0x00, r0, c1, c0, #0x01 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Disable Flash ECC Support - - .def _coreDisableFlashEcc_ - .asmfunc - -_coreDisableFlashEcc_ - - stmfd sp!, {r0} - mrc p15, #0x00, r0, c1, c0, #0x01 - bic r0, r0, #0x02000000 - mcr p15, #0x00, r0, c1, c0, #0x01 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - -;------------------------------------------------------------------------------- -; Get data fault status register - - .def _coreGetDataFault_ - .asmfunc - -_coreGetDataFault_ - - mrc p15, #0, r0, c5, c0, #0 - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Clear data fault status register - - .def _coreClearDataFault_ - .asmfunc - -_coreClearDataFault_ - - stmfd sp!, {r0} - mov r0, #0 - mcr p15, #0, r0, c5, c0, #0 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Get instruction fault status register - - .def _coreGetInstructionFault_ - .asmfunc - -_coreGetInstructionFault_ - - mrc p15, #0, r0, c5, c0, #1 - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Clear instruction fault status register - - .def _coreClearInstructionFault_ - .asmfunc - -_coreClearInstructionFault_ - - stmfd sp!, {r0} - mov r0, #0 - mcr p15, #0, r0, c5, c0, #1 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Get data fault address register - - .def _coreGetDataFaultAddress_ - .asmfunc - -_coreGetDataFaultAddress_ - - mrc p15, #0, r0, c6, c0, #0 - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Clear data fault address register - - .def _coreClearDataFaultAddress_ - .asmfunc - -_coreClearDataFaultAddress_ - - stmfd sp!, {r0} - mov r0, #0 - mcr p15, #0, r0, c6, c0, #0 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Get instruction fault address register - - .def _coreGetInstructionFaultAddress_ - .asmfunc - -_coreGetInstructionFaultAddress_ - - mrc p15, #0, r0, c6, c0, #2 - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Clear instruction fault address register - - .def _coreClearInstructionFaultAddress_ - .asmfunc - -_coreClearInstructionFaultAddress_ - - stmfd sp!, {r0} - mov r0, #0 - mcr p15, #0, r0, c6, c0, #2 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Get auxiliary data fault status register - - .def _coreGetAuxiliaryDataFault_ - .asmfunc - -_coreGetAuxiliaryDataFault_ - - mrc p15, #0, r0, c5, c1, #0 - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Clear auxiliary data fault status register - - .def _coreClearAuxiliaryDataFault_ - .asmfunc - -_coreClearAuxiliaryDataFault_ - - stmfd sp!, {r0} - mov r0, #0 - mcr p15, #0, r0, c5, c1, #0 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Get auxiliary instruction fault status register - - .def _coreGetAuxiliaryInstructionFault_ - .asmfunc - -_coreGetAuxiliaryInstructionFault_ - - mrc p15, #0, r0, c5, c1, #1 - bx lr - - .endasmfunc - -;------------------------------------------------------------------------------- -; Clear auxiliary instruction fault status register - - .def _coreClearAuxiliaryInstructionFault_ - .asmfunc - -_coreClearAuxiliaryInstructionFault_ - - stmfd sp!, {r0} - mov r0, #0 - mrc p15, #0, r0, c5, c1, #1 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - -;------------------------------------------------------------------------------- -; Clear ESM CCM errorss - - .def _esmCcmErrorsClear_ - .asmfunc - -_esmCcmErrorsClear_ - - stmfd sp!, {r0-r2} - ldr r0, ESMSR1_REG ; load the ESMSR1 status register address - ldr r2, ESMSR1_ERR_CLR - str r2, [r0] ; clear the ESMSR1 register - - ldr r0, ESMSR2_REG ; load the ESMSR2 status register address - ldr r2, ESMSR2_ERR_CLR - str r2, [r0] ; clear the ESMSR2 register - - ldr r0, ESMSSR2_REG ; load the ESMSSR2 status register address - ldr r2, ESMSSR2_ERR_CLR - str r2, [r0] ; clear the ESMSSR2 register - - ldr r0, ESMKEY_REG ; load the ESMKEY register address - mov r2, #0x5 ; load R2 with 0x5 - str r2, [r0] ; clear the ESMKEY register - - ldr r0, VIM_INTREQ ; load the INTREQ register address - ldr r2, VIM_INT_CLR - str r2, [r0] ; clear the INTREQ register - ldr r0, CCMR4_STAT_REG ; load the CCMR4 status register address - ldr r2, CCMR4_ERR_CLR - str r2, [r0] ; clear the CCMR4 status register - ldmfd sp!, {r0-r2} - bx lr - -ESMSR1_REG .word 0xFFFFF518 -ESMSR2_REG .word 0xFFFFF51C -ESMSR3_REG .word 0xFFFFF520 -ESMKEY_REG .word 0xFFFFF538 -ESMSSR2_REG .word 0xFFFFF53C -CCMR4_STAT_REG .word 0xFFFFF600 -ERR_CLR_WRD .word 0xFFFFFFFF -CCMR4_ERR_CLR .word 0x00010000 -ESMSR1_ERR_CLR .word 0x80000000 -ESMSR2_ERR_CLR .word 0x00000004 -ESMSSR2_ERR_CLR .word 0x00000004 -VIM_INT_CLR .word 0x00000001 -VIM_INTREQ .word 0xFFFFFE20 - - .endasmfunc - -;------------------------------------------------------------------------------- -; Work Around for Errata CORTEX-R4#57: -; -; Errata Description: -; Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags -; Workaround: -; Disable out-of-order single-precision floating point -; multiply-accumulate instruction completion - - .def _errata_CORTEXR4_57_ - .asmfunc - -_errata_CORTEXR4_57_ - - push {r0} - mrc p15, #0, r0, c15, c0, #0 ; Read Secondary Auxiliary Control Register - orr r0, r0, #0x10000 ; Set BIT 16 (Set DOOFMACS) - mcr p15, #0, r0, c15, c0, #0 ; Write Secondary Auxiliary Control Register - pop {r0} - bx lr - .endasmfunc - -;------------------------------------------------------------------------------- -; Work Around for Errata CORTEX-R4#66: -; -; Errata Description: -; Register Corruption During A Load-Multiple Instruction At -; an Exception Vector -; Workaround: -; Disable out-of-order completion for divide instructions in -; Auxiliary Control register - - .def _errata_CORTEXR4_66_ - .asmfunc - -_errata_CORTEXR4_66_ - - push {r0} - mrc p15, #0, r0, c1, c0, #1 ; Read Auxiliary Control register - orr r0, r0, #0x80 ; Set BIT 7 (Disable out-of-order completion - ; for divide instructions.) - mcr p15, #0, r0, c1, c0, #1 ; Write Auxiliary Control register - pop {r0} - bx lr - .endasmfunc - - .def turnon_VFP - .asmfunc -turnon_VFP - ; Enable FPV - STMDB sp!, {r0} - fmrx r0, fpexc - orr r0, r0, #0x40000000 - fmxr fpexc, r0 - LDMIA sp!, {r0} - subs pc, lr, #4 - .endasmfunc - -_push_svc_reg .macro - sub sp, sp, #17 * 4 ;/* Sizeof(struct rt_hw_exp_stack) */ - stmia sp, {r0 - r12} ;/* Calling r0-r12 */ - mov r0, sp - mrs r6, spsr ;/* Save CPSR */ - str lr, [r0, #15*4] ;/* Push PC */ - str r6, [r0, #16*4] ;/* Push CPSR */ - cps #0x13 - str sp, [r0, #13*4] ;/* Save calling SP */ - str lr, [r0, #14*4] ;/* Save calling PC */ - .endm - - .ref rt_hw_trap_svc - .def vector_svc - .asmfunc -vector_svc: - _push_svc_reg - bl rt_hw_trap_svc - sub pc, pc, #-4 - .endasmfunc - - .ref rt_hw_trap_pabt - .def vector_pabort - .asmfunc -vector_pabort: - _push_svc_reg - bl rt_hw_trap_pabt - sub pc, pc, #-4 - .endasmfunc - - .ref rt_hw_trap_dabt - .def vector_dabort - .asmfunc -vector_dabort: - _push_svc_reg - bl rt_hw_trap_dabt - sub pc, pc, #-4 - .endasmfunc - - .ref rt_hw_trap_resv - .def vector_resv - .asmfunc -vector_resv: - _push_svc_reg - bl rt_hw_trap_resv - sub pc, pc, #-4 - .endasmfunc - -;------------------------------------------------------------------------------- -; C++ construct table pointers - - .def __TI_PINIT_Base, __TI_PINIT_Limit - .weak SHT$$INIT_ARRAY$$Base, SHT$$INIT_ARRAY$$Limit - -__TI_PINIT_Base .long SHT$$INIT_ARRAY$$Base -__TI_PINIT_Limit .long SHT$$INIT_ARRAY$$Limit - -;------------------------------------------------------------------------------- diff --git a/rt-thread/libcpu/arm/cortex-r4/start_gcc.S b/rt-thread/libcpu/arm/cortex-r4/start_gcc.S deleted file mode 100644 index 10a74b2..0000000 --- a/rt-thread/libcpu/arm/cortex-r4/start_gcc.S +++ /dev/null @@ -1,504 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ -@------------------------------------------------------------------------------- -@ sys_core.asm -@ -@ (c) Texas Instruments 2009-2013, All rights reserved. -@ - -#include - -.equ Mode_USR, 0x10 -.equ Mode_FIQ, 0x11 -.equ Mode_IRQ, 0x12 -.equ Mode_SVC, 0x13 -.equ Mode_ABT, 0x17 -.equ Mode_UND, 0x1B -.equ Mode_SYS, 0x1F - -.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled -.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled - -.equ UND_Stack_Size, 0x00000000 -.equ SVC_Stack_Size, 0x00000000 -.equ ABT_Stack_Size, 0x00000000 -.equ FIQ_Stack_Size, 0x00001000 -.equ IRQ_Stack_Size, 0x00001000 - -.section .bss.noinit -/* stack */ -.globl stack_start -.globl stack_top - -.align 3 -stack_start: -.rept (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) -.byte 0 -.endr -stack_top: - -.section .text, "ax" - .text - .arm - - .globl _c_int00 - -.globl _reset -_reset: -@------------------------------------------------------------------------------- -@ Initialize CPU Registers -@ After reset, the CPU is in the Supervisor mode (M = 10011) - mov r0, #0x0000 - mov r1, #0x0000 - mov r2, #0x0000 - mov r3, #0x0000 - mov r4, #0x0000 - mov r5, #0x0000 - mov r6, #0x0000 - mov r7, #0x0000 - mov r8, #0x0000 - mov r9, #0x0000 - mov r10, #0x0000 - mov r11, #0x0000 - mov r12, #0x0000 - mov r13, #0x0000 - mrs r1, cpsr - msr spsr_cxsf, r1 - - cpsid if, #19 - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) - @ Turn on FPV coprocessor - mrc p15, #0x00, r2, c1, c0, #0x02 - orr r2, r2, #0xF00000 - mcr p15, #0x00, r2, c1, c0, #0x02 - - fmrx r2, fpexc - orr r2, r2, #0x40000000 - fmxr fpexc, r2 -#endif - -@------------------------------------------------------------------------------- -@ Initialize Stack Pointers - ldr r0, =stack_top - - @ Set the startup stack for svc - mov sp, r0 - - @ Enter Undefined Instruction Mode and set its Stack Pointer - msr cpsr_c, #Mode_UND|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #UND_Stack_Size - - @ Enter Abort Mode and set its Stack Pointer - msr cpsr_c, #Mode_ABT|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #ABT_Stack_Size - - @ Enter FIQ Mode and set its Stack Pointer - msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #FIQ_Stack_Size - - @ Enter IRQ Mode and set its Stack Pointer - msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #IRQ_Stack_Size - - @ Switch back to SVC - msr cpsr_c, #Mode_SVC|I_Bit|F_Bit - - bl next1 -next1: - bl next2 -next2: - bl next3 -next3: - bl next4 -next4: - ldr lr, =_c_int00 - bx lr - -.globl data_init -data_init: - /* copy .data to SRAM */ - ldr r1, =_sidata /* .data start in image */ - ldr r2, =_edata /* .data end in image */ - ldr r3, =_sdata /* sram data start */ -data_loop: - ldr r0, [r1, #0] - str r0, [r3] - - add r1, r1, #4 - add r3, r3, #4 - - cmp r3, r2 /* check if data to clear */ - blo data_loop /* loop until done */ - - /* clear .bss */ - mov r0,#0 /* get a zero */ - ldr r1,=__bss_start /* bss start */ - ldr r2,=__bss_end /* bss end */ - -bss_loop: - cmp r1,r2 /* check if data to clear */ - strlo r0,[r1],#4 /* clear 4 bytes */ - blo bss_loop /* loop until done */ - - /* call C++ constructors of global objects */ - ldr r0, =__ctors_start__ - ldr r1, =__ctors_end__ - -ctor_loop: - cmp r0, r1 - beq ctor_end - ldr r2, [r0], #4 - stmfd sp!, {r0-r3, ip, lr} - mov lr, pc - bx r2 - ldmfd sp!, {r0-r3, ip, lr} - b ctor_loop -ctor_end: - bx lr - -@------------------------------------------------------------------------------- -@ Enable RAM ECC Support - - .globl _coreEnableRamEcc_ -_coreEnableRamEcc_: - - stmfd sp!, {r0} - mrc p15, #0x00, r0, c1, c0, #0x01 - orr r0, r0, #0x0C000000 - mcr p15, #0x00, r0, c1, c0, #0x01 - ldmfd sp!, {r0} - bx lr - -@------------------------------------------------------------------------------- -@ Disable RAM ECC Support - - .globl _coreDisableRamEcc_ -_coreDisableRamEcc_: - - stmfd sp!, {r0} - mrc p15, #0x00, r0, c1, c0, #0x01 - bic r0, r0, #0x0C000000 - mcr p15, #0x00, r0, c1, c0, #0x01 - ldmfd sp!, {r0} - bx lr - - -@------------------------------------------------------------------------------- -@ Enable Flash ECC Support - - .globl _coreEnableFlashEcc_ -_coreEnableFlashEcc_: - - stmfd sp!, {r0} - mrc p15, #0x00, r0, c1, c0, #0x01 - orr r0, r0, #0x02000000 - dmb - mcr p15, #0x00, r0, c1, c0, #0x01 - ldmfd sp!, {r0} - bx lr - -@------------------------------------------------------------------------------- -@ Disable Flash ECC Support - - .globl _coreDisableFlashEcc_ -_coreDisableFlashEcc_: - - stmfd sp!, {r0} - mrc p15, #0x00, r0, c1, c0, #0x01 - bic r0, r0, #0x02000000 - mcr p15, #0x00, r0, c1, c0, #0x01 - ldmfd sp!, {r0} - bx lr - - -@------------------------------------------------------------------------------- -@ Get data fault status register - - .globl _coreGetDataFault_ -_coreGetDataFault_: - - mrc p15, #0, r0, c5, c0, #0 - bx lr - - - -@------------------------------------------------------------------------------- -@ Clear data fault status register - - .globl _coreClearDataFault_ -_coreClearDataFault_: - - stmfd sp!, {r0} - mov r0, #0 - mcr p15, #0, r0, c5, c0, #0 - ldmfd sp!, {r0} - bx lr - - - -@------------------------------------------------------------------------------- -@ Get instruction fault status register - - .globl _coreGetInstructionFault_ -_coreGetInstructionFault_: - - mrc p15, #0, r0, c5, c0, #1 - bx lr - - - -@------------------------------------------------------------------------------- -@ Clear instruction fault status register - - .globl _coreClearInstructionFault_ -_coreClearInstructionFault_: - - stmfd sp!, {r0} - mov r0, #0 - mcr p15, #0, r0, c5, c0, #1 - ldmfd sp!, {r0} - bx lr - - - -@------------------------------------------------------------------------------- -@ Get data fault address register - - .globl _coreGetDataFaultAddress_ -_coreGetDataFaultAddress_: - - mrc p15, #0, r0, c6, c0, #0 - bx lr - - - -@------------------------------------------------------------------------------- -@ Clear data fault address register - - .globl _coreClearDataFaultAddress_ -_coreClearDataFaultAddress_: - - stmfd sp!, {r0} - mov r0, #0 - mcr p15, #0, r0, c6, c0, #0 - ldmfd sp!, {r0} - bx lr - - - -@------------------------------------------------------------------------------- -@ Get instruction fault address register - - .globl _coreGetInstructionFaultAddress_ -_coreGetInstructionFaultAddress_: - - mrc p15, #0, r0, c6, c0, #2 - bx lr - - - -@------------------------------------------------------------------------------- -@ Clear instruction fault address register - - .globl _coreClearInstructionFaultAddress_ -_coreClearInstructionFaultAddress_: - - stmfd sp!, {r0} - mov r0, #0 - mcr p15, #0, r0, c6, c0, #2 - ldmfd sp!, {r0} - bx lr - - - -@------------------------------------------------------------------------------- -@ Get auxiliary data fault status register - - .globl _coreGetAuxiliaryDataFault_ -_coreGetAuxiliaryDataFault_: - - mrc p15, #0, r0, c5, c1, #0 - bx lr - - - -@------------------------------------------------------------------------------- -@ Clear auxiliary data fault status register - - .globl _coreClearAuxiliaryDataFault_ -_coreClearAuxiliaryDataFault_: - - stmfd sp!, {r0} - mov r0, #0 - mcr p15, #0, r0, c5, c1, #0 - ldmfd sp!, {r0} - bx lr - - - -@------------------------------------------------------------------------------- -@ Get auxiliary instruction fault status register - - .globl _coreGetAuxiliaryInstructionFault_ -_coreGetAuxiliaryInstructionFault_: - - mrc p15, #0, r0, c5, c1, #1 - bx lr - - -@------------------------------------------------------------------------------- -@ Clear auxiliary instruction fault status register - - .globl _coreClearAuxiliaryInstructionFault_ -_coreClearAuxiliaryInstructionFault_: - - stmfd sp!, {r0} - mov r0, #0 - mrc p15, #0, r0, c5, c1, #1 - ldmfd sp!, {r0} - bx lr - - -@------------------------------------------------------------------------------- -@ Clear ESM CCM errorss - - .globl _esmCcmErrorsClear_ -_esmCcmErrorsClear_: - - stmfd sp!, {r0-r2} - ldr r0, ESMSR1_REG @ load the ESMSR1 status register address - ldr r2, ESMSR1_ERR_CLR - str r2, [r0] @ clear the ESMSR1 register - - ldr r0, ESMSR2_REG @ load the ESMSR2 status register address - ldr r2, ESMSR2_ERR_CLR - str r2, [r0] @ clear the ESMSR2 register - - ldr r0, ESMSSR2_REG @ load the ESMSSR2 status register address - ldr r2, ESMSSR2_ERR_CLR - str r2, [r0] @ clear the ESMSSR2 register - - ldr r0, ESMKEY_REG @ load the ESMKEY register address - mov r2, #0x5 @ load R2 with 0x5 - str r2, [r0] @ clear the ESMKEY register - - ldr r0, VIM_INTREQ @ load the INTREQ register address - ldr r2, VIM_INT_CLR - str r2, [r0] @ clear the INTREQ register - ldr r0, CCMR4_STAT_REG @ load the CCMR4 status register address - ldr r2, CCMR4_ERR_CLR - str r2, [r0] @ clear the CCMR4 status register - ldmfd sp!, {r0-r2} - bx lr - -ESMSR1_REG: .word 0xFFFFF518 -ESMSR2_REG: .word 0xFFFFF51C -ESMSR3_REG: .word 0xFFFFF520 -ESMKEY_REG: .word 0xFFFFF538 -ESMSSR2_REG: .word 0xFFFFF53C -CCMR4_STAT_REG: .word 0xFFFFF600 -ERR_CLR_WRD: .word 0xFFFFFFFF -CCMR4_ERR_CLR: .word 0x00010000 -ESMSR1_ERR_CLR: .word 0x80000000 -ESMSR2_ERR_CLR: .word 0x00000004 -ESMSSR2_ERR_CLR: .word 0x00000004 -VIM_INT_CLR: .word 0x00000001 -VIM_INTREQ: .word 0xFFFFFE20 - - -@------------------------------------------------------------------------------- -@ Work Around for Errata CORTEX-R4#57: -@ -@ Errata Description: -@ Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags -@ Workaround: -@ Disable out-of-order single-precision floating point -@ multiply-accumulate instruction completion - - .globl _errata_CORTEXR4_57_ -_errata_CORTEXR4_57_: - - push {r0} - mrc p15, #0, r0, c15, c0, #0 @ Read Secondary Auxiliary Control Register - orr r0, r0, #0x10000 @ Set BIT 16 (Set DOOFMACS) - mcr p15, #0, r0, c15, c0, #0 @ Write Secondary Auxiliary Control Register - pop {r0} - bx lr - -@------------------------------------------------------------------------------- -@ Work Around for Errata CORTEX-R4#66: -@ -@ Errata Description: -@ Register Corruption During A Load-Multiple Instruction At -@ an Exception Vector -@ Workaround: -@ Disable out-of-order completion for divide instructions in -@ Auxiliary Control register - - .globl _errata_CORTEXR4_66_ -_errata_CORTEXR4_66_: - - push {r0} - mrc p15, #0, r0, c1, c0, #1 @ Read Auxiliary Control register - orr r0, r0, #0x80 @ Set BIT 7 (Disable out-of-order completion - @ for divide instructions.) - mcr p15, #0, r0, c1, c0, #1 @ Write Auxiliary Control register - pop {r0} - bx lr - - .globl turnon_VFP -turnon_VFP: - @ Enable FPV - STMDB sp!, {r0} - fmrx r0, fpexc - orr r0, r0, #0x40000000 - fmxr fpexc, r0 - LDMIA sp!, {r0} - subs pc, lr, #4 - - .macro push_svc_reg - sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ - stmia sp, {r0 - r12} @/* Calling r0-r12 */ - mov r0, sp - mrs r6, spsr @/* Save CPSR */ - str lr, [r0, #15*4] @/* Push PC */ - str r6, [r0, #16*4] @/* Push CPSR */ - cps #Mode_SVC - str sp, [r0, #13*4] @/* Save calling SP */ - str lr, [r0, #14*4] @/* Save calling PC */ - .endm - - .globl vector_svc -vector_svc: - push_svc_reg - bl rt_hw_trap_svc - b . - - .globl vector_pabort -vector_pabort: - push_svc_reg - bl rt_hw_trap_pabt - b . - - .globl vector_dabort -vector_dabort: - push_svc_reg - bl rt_hw_trap_dabt - b . - - .globl vector_resv -vector_resv: - push_svc_reg - bl rt_hw_trap_resv - b . diff --git a/rt-thread/libcpu/arm/cortex-r4/trap.c b/rt-thread/libcpu/arm/cortex-r4/trap.c deleted file mode 100644 index 3ff3d29..0000000 --- a/rt-thread/libcpu/arm/cortex-r4/trap.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2008-12-11 XuXinming first version - * 2013-05-24 Grissiom port to RM48x50 - */ - -#include -#include - -#include - -#include "armv7.h" - -/** - * @addtogroup RM48x50 - */ -/*@{*/ - -/** - * this function will show registers of CPU - * - * @param regs the registers point - */ -void rt_hw_show_register (struct rt_hw_exp_stack *regs) -{ - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); -} - -/** - * When comes across an instruction which it cannot handle, - * it takes the undefined instruction trap. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_udef(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("undefined instruction\n"); - rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); - rt_hw_cpu_shutdown(); -} - -/** - * The software interrupt instruction (SWI) is used for entering - * Supervisor mode, usually to request a particular supervisor - * function. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_svc(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("software interrupt\n"); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during an instruction prefetch. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("prefetch abort\n"); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during a data access. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("Data Abort "); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * Normally, system will never reach here - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("Reserved trap\n"); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -extern rt_isr_handler_t isr_table[]; -void rt_hw_trap_irq(void) -{ - int irqno; - struct rt_irq_desc* irq; - extern struct rt_irq_desc irq_desc[]; - - irq = (struct rt_irq_desc*) vimREG->IRQVECREG; - irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); - - /* invoke isr */ - irq->handler(irqno, irq->param); -} - -void rt_hw_trap_fiq(void) -{ - rt_kprintf("fast interrupt request\n"); -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/cortex-r4/vector_ccs.asm b/rt-thread/libcpu/arm/cortex-r4/vector_ccs.asm deleted file mode 100644 index df2bcec..0000000 --- a/rt-thread/libcpu/arm/cortex-r4/vector_ccs.asm +++ /dev/null @@ -1,34 +0,0 @@ -;------------------------------------------------------------------------------- -; sys_intvecs.asm -; -; (c) Texas Instruments 2009-2013, All rights reserved. -; - - .sect ".intvecs" - .arm - -;------------------------------------------------------------------------------- -; import reference for interrupt routines - - .ref _reset - .ref turnon_VFP - .ref vector_svc - .ref vector_pabort - .ref vector_dabort - .ref vector_resv - .ref IRQ_Handler - -;------------------------------------------------------------------------------- -; interrupt vectors - .def resetEntry -resetEntry - b _reset - b turnon_VFP - b vector_svc - b vector_pabort - b vector_dabort - b vector_resv - b IRQ_Handler - ldr pc,[pc,#-0x1b0] - -;------------------------------------------------------------------------------- diff --git a/rt-thread/libcpu/arm/cortex-r4/vector_gcc.S b/rt-thread/libcpu/arm/cortex-r4/vector_gcc.S deleted file mode 100644 index 6cb2e9f..0000000 --- a/rt-thread/libcpu/arm/cortex-r4/vector_gcc.S +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ -@------------------------------------------------------------------------------- -@ sys_intvecs.asm -@ -@ (c) Texas Instruments 2009-2013, All rights reserved. -@ - -.section .vectors, "ax" -.code 32 - -@------------------------------------------------------------------------------- -@ import reference for interrupt routines - - .globl _reset - .globl turnon_VFP - .globl vector_svc - .globl vector_pabort - .globl vector_dabort - .globl vector_resv - .globl IRQ_Handler - - -.globl system_vectors -system_vectors: - b _reset - b turnon_VFP - b vector_svc - b vector_pabort - b vector_dabort - b vector_resv - b IRQ_Handler - ldr pc,[pc,#-0x1b0] diff --git a/rt-thread/libcpu/arm/dm36x/SConscript b/rt-thread/libcpu/arm/dm36x/SConscript deleted file mode 100644 index b259a94..0000000 --- a/rt-thread/libcpu/arm/dm36x/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/dm36x/context_gcc.S b/rt-thread/libcpu/arm/dm36x/context_gcc.S deleted file mode 100644 index 7eed72a..0000000 --- a/rt-thread/libcpu/arm/dm36x/context_gcc.S +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety - */ - -/*! - * \addtogroup DM36X - */ -/*@{*/ - -#define NOINT 0xc0 - - -/* - * rt_base_t rt_hw_interrupt_disable(); - */ -.globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mrs r0, cpsr - orr r1, r0, #NOINT - msr cpsr_c, r1 - bx lr - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ -.globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - msr cpsr, r0 - bx lr - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to - */ -.globl rt_hw_context_switch -rt_hw_context_switch: - stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) - stmfd sp!, {r0-r12, lr} @ push lr & register file - - mrs r4, cpsr - tst lr, #0x01 - orrne r4, r4, #0x20 @ it's thumb code - - stmfd sp!, {r4} @ push cpsr - - str sp, [r0] @ store sp in preempted tasks TCB - ldr sp, [r1] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task cpsr to spsr - msr spsr_cxsf, r4 -_do_switch: - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to - */ -.globl rt_hw_context_switch_to -rt_hw_context_switch_to: - ldr sp, [r0] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - - bic r4, r4, #0x20 @ must be ARM mode - msr cpsr_cxsf, r4 - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - */ -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -.globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - ldr r2, =rt_thread_switch_interrupt_flag - ldr r3, [r2] - cmp r3, #1 - beq _reswitch - mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 - str r3, [r2] - ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread - str r0, [r2] -_reswitch: - ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread - str r1, [r2] - bx lr diff --git a/rt-thread/libcpu/arm/dm36x/context_rvds.S b/rt-thread/libcpu/arm/dm36x/context_rvds.S deleted file mode 100644 index 4054b97..0000000 --- a/rt-thread/libcpu/arm/dm36x/context_rvds.S +++ /dev/null @@ -1,103 +0,0 @@ -;/* -; * Copyright (c) 2006-2022, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2011-08-14 weety copy from mini2440 -; */ - -NOINT EQU 0xc0 ; disable interrupt in psr - - AREA |.text|, CODE, READONLY, ALIGN=2 - ARM - REQUIRE8 - PRESERVE8 - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ -rt_hw_interrupt_disable PROC - EXPORT rt_hw_interrupt_disable - MRS r0, cpsr - ORR r1, r0, #NOINT - MSR cpsr_c, r1 - BX lr - ENDP - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ -rt_hw_interrupt_enable PROC - EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0 - BX lr - ENDP - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ -rt_hw_context_switch PROC - EXPORT rt_hw_context_switch - STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC) - STMFD sp!, {r0-r12, lr} ; push lr & register file - - MRS r4, cpsr - STMFD sp!, {r4} ; push cpsr - MRS r4, spsr - STMFD sp!, {r4} ; push spsr - - STR sp, [r0] ; store sp in preempted tasks TCB - LDR sp, [r1] ; get new task stack pointer - - LDMFD sp!, {r4} ; pop new task spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task cpsr - MSR spsr_cxsf, r4 - - LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc - ENDP - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; */ -rt_hw_context_switch_to PROC - EXPORT rt_hw_context_switch_to - LDR sp, [r0] ; get new task stack pointer - - LDMFD sp!, {r4} ; pop new task spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task cpsr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP - -;/* -; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); -; */ - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -rt_hw_context_switch_interrupt PROC - EXPORT rt_hw_context_switch_interrupt - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1 - STR r3, [r2] - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - BX lr - ENDP - - END diff --git a/rt-thread/libcpu/arm/dm36x/cpuport.c b/rt-thread/libcpu/arm/dm36x/cpuport.c deleted file mode 100644 index a23dc32..0000000 --- a/rt-thread/libcpu/arm/dm36x/cpuport.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version - */ - -#include -#include - -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) - -extern void machine_reset(void); -extern void machine_shutdown(void); - -#ifdef __GNUC__ -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); -} -#endif - -#ifdef __CC_ARM -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - __asm - { - mrc p15, 0, i, c1, c0, 0 - } - - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } -} -#endif - -/** - * enable I-Cache - * - */ -void rt_hw_cpu_icache_enable() -{ - cache_enable(ICACHE_MASK); -} - -/** - * disable I-Cache - * - */ -void rt_hw_cpu_icache_disable() -{ - cache_disable(ICACHE_MASK); -} - -/** - * return the status of I-Cache - * - */ -rt_base_t rt_hw_cpu_icache_status() -{ - return (cp15_rd() & ICACHE_MASK); -} - -/** - * enable D-Cache - * - */ -void rt_hw_cpu_dcache_enable() -{ - cache_enable(DCACHE_MASK); -} - -/** - * disable D-Cache - * - */ -void rt_hw_cpu_dcache_disable() -{ - cache_disable(DCACHE_MASK); -} - -/** - * return the status of D-Cache - * - */ -rt_base_t rt_hw_cpu_dcache_status() -{ - return (cp15_rd() & DCACHE_MASK); -} - -/** - * reset cpu by dog's time-out - * - */ -RT_WEAK void rt_hw_cpu_reset() -{ - - rt_kprintf("Restarting system...\n"); - machine_reset(); - - while(1); /* loop forever and wait for reset to happen */ - - /* NEVER REACHED */ -} - -/** - * shutdown CPU - * - */ -RT_WEAK void rt_hw_cpu_shutdown() -{ - rt_base_t level; - rt_kprintf("shutdown...\n"); - - level = rt_hw_interrupt_disable(); - machine_shutdown(); - while (level) - { - RT_ASSERT(0); - } -} - -#ifdef RT_USING_CPU_FFS -/** - * This function finds the first bit set (beginning with the least significant bit) - * in value and return the index of that bit. - * - * Bits are numbered starting at 1 (the least significant bit). A return value of - * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function - * shall return 0. - */ -#if defined(__CC_ARM) -int __rt_ffs(int value) -{ - register rt_uint32_t x; - - if (value == 0) - return value; - - __asm - { - rsb x, value, #0 - and x, x, value - clz x, x - rsb x, x, #32 - } - - return x; -} -#elif defined(__IAR_SYSTEMS_ICC__) -int __rt_ffs(int value) -{ - if (value == 0) - return value; - - __ASM("RSB r4, r0, #0"); - __ASM("AND r4, r4, r0"); - __ASM("CLZ r4, r4"); - __ASM("RSB r0, r4, #32"); -} -#elif defined(__GNUC__) -int __rt_ffs(int value) -{ - if (value == 0) - return value; - - value &= (-value); - asm ("clz %0, %1": "=r"(value) :"r"(value)); - - return (32 - value); -} -#endif - -#endif - - -/*@}*/ diff --git a/rt-thread/libcpu/arm/dm36x/mmu.c b/rt-thread/libcpu/arm/dm36x/mmu.c deleted file mode 100644 index bec2e6a..0000000 --- a/rt-thread/libcpu/arm/dm36x/mmu.c +++ /dev/null @@ -1,546 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ - -#include "mmu.h" - -#ifdef __CC_ARM -void mmu_setttbase(rt_uint32_t i) -{ - register rt_uint32_t value; - - /* Invalidates all TLBs.Domain access is selected as - * client by configuring domain access register, - * in that case access controlled by permission value - * set by page table entry - */ - value = 0; - __asm volatile - { - mcr p15, 0, value, c8, c7, 0 - } - - value = 0x55555555; - __asm volatile - { - mcr p15, 0, value, c3, c0, 0 - mcr p15, 0, i, c2, c0, 0 - } -} - -void mmu_set_domain(rt_uint32_t i) -{ - __asm volatile - { - mcr p15,0, i, c3, c0, 0 - } -} - -void mmu_enable() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_enable_icache() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_enable_dcache() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable_icache() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable_dcache() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_enable_alignfault() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable_alignfault() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_clean_invalidated_cache_index(int index) -{ - __asm volatile - { - mcr p15, 0, index, c7, c14, 2 - } -} - -void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~(CACHE_LINE_SIZE - 1); - - while(ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c14, 1 - } - ptr += CACHE_LINE_SIZE; - } -} - -void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~(CACHE_LINE_SIZE - 1); - - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c10, 1 - } - ptr += CACHE_LINE_SIZE; - } -} - -void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~(CACHE_LINE_SIZE - 1); - - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c6, 1 - } - ptr += CACHE_LINE_SIZE; - } -} - -void mmu_invalidate_tlb() -{ - register rt_uint32_t value; - - value = 0; - __asm volatile - { - mcr p15, 0, value, c8, c7, 0 - } -} - -void mmu_invalidate_icache() -{ - register rt_uint32_t value; - - value = 0; - - __asm volatile - { - mcr p15, 0, value, c7, c5, 0 - } -} - - -void mmu_invalidate_dcache_all() -{ - register rt_uint32_t value; - - value = 0; - - __asm volatile - { - mcr p15, 0, value, c7, c6, 0 - } -} -#elif defined(__GNUC__) -void mmu_setttbase(register rt_uint32_t i) -{ - register rt_uint32_t value; - - /* Invalidates all TLBs.Domain access is selected as - * client by configuring domain access register, - * in that case access controlled by permission value - * set by page table entry - */ - value = 0; - asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); - - value = 0x55555555; - asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); - asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); -} - -void mmu_set_domain(register rt_uint32_t i) -{ - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); -} - -void mmu_enable() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= 0x1; - i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ - /* S R bit=1 0 for system protection */ - i |= (1 << 8); - i &= ~(1 << 9); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~0x1; - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_enable_icache() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= (1 << 12); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_enable_dcache() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= (1 << 2); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable_icache() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~(1 << 12); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable_dcache() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~(1 << 2); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_enable_alignfault() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= (1 << 1); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable_alignfault() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~(1 << 1); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_clean_invalidated_cache_index(int index) -{ - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); -} - -void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~(CACHE_LINE_SIZE - 1); - - while(ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } -} - - -void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~(CACHE_LINE_SIZE - 1); - - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } -} - -void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) -{ - unsigned int ptr; - - ptr = buffer & ~(CACHE_LINE_SIZE - 1); - - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } -} - -void mmu_invalidate_tlb() -{ - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); -} - -void mmu_invalidate_icache() -{ - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); -} - -void mmu_invalidate_dcache_all() -{ - asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0)); -} -#endif - -/* level1 page table */ -static volatile unsigned int _pgd_table[4*1024] ALIGN(16*1024); -/* - * level2 page table - * RT_MMU_PTE_SIZE must be 1024*n - */ -static volatile unsigned int _pte_table[RT_MMU_PTE_SIZE] ALIGN(1*1024); - -void mmu_create_pgd(struct mem_desc *mdesc) -{ - volatile rt_uint32_t *pTT; - volatile int i, nSec; - pTT = (rt_uint32_t *)_pgd_table + (mdesc->vaddr_start >> 20); - nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20); - for(i = 0; i <= nSec; i++) - { - *pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20); - pTT++; - } -} - -void mmu_create_pte(struct mem_desc *mdesc) -{ - volatile rt_uint32_t *pTT; - volatile rt_uint32_t *p_pteentry; - int i; - rt_uint32_t vaddr; - rt_uint32_t total_page = 0; - rt_uint32_t pte_offset = 0; - rt_uint32_t sect_attr = 0; - - total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1; - pte_offset = mdesc->sect_attr & 0xfffffc00; - sect_attr = mdesc->sect_attr & 0x3ff; - vaddr = mdesc->vaddr_start; - - for(i = 0; i < total_page; i++) - { - pTT = (rt_uint32_t *)_pgd_table + (vaddr >> 20); - if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */ - { - *pTT = pte_offset | sect_attr; - p_pteentry = (rt_uint32_t *)pte_offset + - ((vaddr & 0x000ff000) >> 12); - pte_offset += 1024; - } - else /* using old Level 1 page table item */ - { - p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + - ((vaddr & 0x000ff000) >> 12); - } - - - *p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12); - vaddr += 0x1000; - } -} - -static void build_pte_mem_desc(struct mem_desc *mdesc, rt_uint32_t size) -{ - rt_uint32_t pte_offset = 0; - rt_uint32_t nsec = 0; - /* set page table */ - for (; size > 0; size--) - { - if (mdesc->mapped_mode == PAGE_MAPPED) - { - nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20; - mdesc->sect_attr |= (((rt_uint32_t)_pte_table)& 0xfffffc00) + pte_offset; - pte_offset += nsec << 10; - } - if (pte_offset >= RT_MMU_PTE_SIZE) - { - rt_kprintf("PTE table size too little\n"); - RT_ASSERT(0); - } - - mdesc++; - } -} - -void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size) -{ - /* disable I/D cache */ - mmu_disable_dcache(); - mmu_disable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); - - /* clear pgd and pte table */ - rt_memset((void *)_pgd_table, 0, 16*1024); - rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE); - build_pte_mem_desc(mdesc, size); - /* set page table */ - for (; size > 0; size--) - { - if (mdesc->mapped_mode == SECT_MAPPED) - { - mmu_create_pgd(mdesc); - } - else - { - mmu_create_pte(mdesc); - } - - mdesc++; - } - - /* set MMU table address */ - mmu_setttbase((rt_uint32_t)_pgd_table); - - /* enables MMU */ - mmu_enable(); - - /* enable Instruction Cache */ - mmu_enable_icache(); - - /* enable Data Cache */ - mmu_enable_dcache(); - - mmu_invalidate_icache(); - mmu_invalidate_dcache_all(); -} - diff --git a/rt-thread/libcpu/arm/dm36x/mmu.h b/rt-thread/libcpu/arm/dm36x/mmu.h deleted file mode 100644 index 60a4e3c..0000000 --- a/rt-thread/libcpu/arm/dm36x/mmu.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ - -#ifndef __MMU_H__ -#define __MMU_H__ - -#include - -#define CACHE_LINE_SIZE 32 - -/* - * Hardware page table definitions. - * - * + Level 1 descriptor (PGD) - * - common - */ -#define PGD_TYPE_MASK (3 << 0) -#define PGD_TYPE_FAULT (0 << 0) -#define PGD_TYPE_TABLE (1 << 0) -#define PGD_TYPE_SECT (2 << 0) -#define PGD_BIT4 (1 << 4) -#define PGD_DOMAIN(x) ((x) << 5) -#define PGD_PROTECTION (1 << 9) /* ARMv5 */ -/* - * - section - */ -#define PGD_SECT_BUFFERABLE (1 << 2) -#define PGD_SECT_CACHEABLE (1 << 3) -#define PGD_SECT_XN (1 << 4) /* ARMv6 */ -#define PGD_SECT_AP0 (1 << 10) -#define PGD_SECT_AP1 (1 << 11) -#define PGD_SECT_TEX(x) ((x) << 12) /* ARMv5 */ -#define PGD_SECT_APX (1 << 15) /* ARMv6 */ -#define PGD_SECT_S (1 << 16) /* ARMv6 */ -#define PGD_SECT_nG (1 << 17) /* ARMv6 */ -#define PGD_SECT_SUPER (1 << 18) /* ARMv6 */ - -#define PGD_SECT_UNCACHED (0) -#define PGD_SECT_BUFFERED (PGD_SECT_BUFFERABLE) -#define PGD_SECT_WT (PGD_SECT_CACHEABLE) -#define PGD_SECT_WB (PGD_SECT_CACHEABLE | PGD_SECT_BUFFERABLE) -#define PGD_SECT_MINICACHE (PGD_SECT_TEX(1) | PGD_SECT_CACHEABLE) -#define PGD_SECT_WBWA (PGD_SECT_TEX(1) | PGD_SECT_CACHEABLE | PGD_SECT_BUFFERABLE) -#define PGD_SECT_NONSHARED_DEV (PGD_SECT_TEX(2)) - - -/* - * + Level 2 descriptor (PTE) - * - common - */ -#define PTE_TYPE_MASK (3 << 0) -#define PTE_TYPE_FAULT (0 << 0) -#define PTE_TYPE_LARGE (1 << 0) -#define PTE_TYPE_SMALL (2 << 0) -#define PTE_TYPE_EXT (3 << 0) /* ARMv5 */ -#define PTE_BUFFERABLE (1 << 2) -#define PTE_CACHEABLE (1 << 3) - -/* - * - extended small page/tiny page - */ -#define PTE_EXT_XN (1 << 0) /* ARMv6 */ -#define PTE_EXT_AP_MASK (3 << 4) -#define PTE_EXT_AP0 (1 << 4) -#define PTE_EXT_AP1 (2 << 4) -#define PTE_EXT_AP_UNO_SRO (0 << 4) -#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) -#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) -#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) -#define PTE_EXT_TEX(x) ((x) << 6) /* ARMv5 */ -#define PTE_EXT_APX (1 << 9) /* ARMv6 */ -#define PTE_EXT_SHARED (1 << 10) /* ARMv6 */ -#define PTE_EXT_NG (1 << 11) /* ARMv6 */ - -/* - * - small page - */ -#define PTE_SMALL_AP_MASK (0xff << 4) -#define PTE_SMALL_AP_UNO_SRO (0x00 << 4) -#define PTE_SMALL_AP_UNO_SRW (0x55 << 4) -#define PTE_SMALL_AP_URO_SRW (0xaa << 4) -#define PTE_SMALL_AP_URW_SRW (0xff << 4) - -/* - * sector table properities - */ -#define SECT_CB (PGD_SECT_CACHEABLE|PGD_SECT_BUFFERABLE) //cache_on, write_back -#define SECT_CNB (PGD_SECT_CACHEABLE) //cache_on, write_through -#define SECT_NCB (PGD_SECT_BUFFERABLE) //cache_off,WR_BUF on -#define SECT_NCNB (0 << 2) //cache_off,WR_BUF off - -#define SECT_AP_RW (PGD_SECT_AP0|PGD_SECT_AP1) //supervisor=RW, user=RW -#define SECT_AP_RO ((0 << 10)|(0 << 11)) //supervisor=RO, user=NO Access(SR=10) - -#define SECT_RW_CB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write, cache, write back */ -#define SECT_RW_CNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write, cache, write through */ -#define SECT_RW_NCNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write without cache and write buffer */ -#define SECT_RW_FAULT (SECT_AP_RW|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write without cache and write buffer */ - -#define SECT_RO_CB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_BIT4) /* Read Only, cache, write back */ -#define SECT_RO_CNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_BIT4) /* Read Only, cache, write through */ -#define SECT_RO_NCNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_BIT4) /* Read Only without cache and write buffer */ -#define SECT_RO_FAULT (SECT_AP_RO|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_BIT4) /* Read Only without cache and write buffer */ - -#define SECT_TO_PAGE (PGD_DOMAIN(0)|PGD_TYPE_TABLE|PGD_BIT4) /* Level 2 descriptor (PTE) entry properity */ - -/* - * page table properities - */ -#define PAGE_CB (PTE_BUFFERABLE|PTE_CACHEABLE) //cache_on, write_back -#define PAGE_CNB (PTE_CACHEABLE) //cache_on, write_through -#define PAGE_NCB (PTE_BUFFERABLE) //cache_off,WR_BUF on -#define PAGE_NCNB (0 << 2) //cache_off,WR_BUF off - -#define PAGE_AP_RW PTE_SMALL_AP_URW_SRW //supervisor=RW, user=RW -#define PAGE_AP_RO PTE_SMALL_AP_UNO_SRO //supervisor=RO, user=NO Access(SR=10) - -#define PAGE_RW_CB (PAGE_AP_RW|PAGE_CB|PTE_TYPE_SMALL) /* Read/Write, cache, write back */ -#define PAGE_RW_CNB (PAGE_AP_RW|PAGE_CNB|PTE_TYPE_SMALL) /* Read/Write, cache, write through */ -#define PAGE_RW_NCNB (PAGE_AP_RW|PTE_TYPE_SMALL) /* Read/Write without cache and write buffer */ -#define PAGE_RW_FAULT (PAGE_AP_RW|PTE_TYPE_SMALL) /* Read/Write without cache and write buffer */ - - -#define PAGE_RO_CB (PAGE_AP_RO|PAGE_CB|PTE_TYPE_SMALL) /* Read Only, cache, write back */ -#define PAGE_RO_CNB (PAGE_AP_RO|PAGE_CNB|PTE_TYPE_SMALL) /* Read Only, cache, write through */ -#define PAGE_RO_NCNB (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */ -#define PAGE_RO_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */ - -struct mem_desc { - rt_uint32_t vaddr_start; - rt_uint32_t vaddr_end; - rt_uint32_t paddr_start; - rt_uint32_t sect_attr; /* when page mapped */ - rt_uint32_t page_attr; /* only sector mapped valid */ - rt_uint32_t mapped_mode; - #define SECT_MAPPED 0 - #define PAGE_MAPPED 1 -}; - - -void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size); - -#endif - diff --git a/rt-thread/libcpu/arm/dm36x/stack.c b/rt-thread/libcpu/arm/dm36x/stack.c deleted file mode 100644 index e725d06..0000000 --- a/rt-thread/libcpu/arm/dm36x/stack.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety - */ -#include - -/*****************************/ -/* CPU Mode */ -/*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - - stack_addr += sizeof(rt_uint32_t); - stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); - stk = (rt_uint32_t *)stack_addr; - *(--stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0xdeadbeef; /* r12 */ - *(--stk) = 0xdeadbeef; /* r11 */ - *(--stk) = 0xdeadbeef; /* r10 */ - *(--stk) = 0xdeadbeef; /* r9 */ - *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = 0xdeadbeef; /* r4 */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = 0xdeadbeef; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - diff --git a/rt-thread/libcpu/arm/lpc214x/SConscript b/rt-thread/libcpu/arm/lpc214x/SConscript deleted file mode 100644 index b259a94..0000000 --- a/rt-thread/libcpu/arm/lpc214x/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/lpc214x/context_gcc.S b/rt-thread/libcpu/arm/lpc214x/context_gcc.S deleted file mode 100644 index 16d4720..0000000 --- a/rt-thread/libcpu/arm/lpc214x/context_gcc.S +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ -.global rt_hw_interrupt_disable -.global rt_hw_interrupt_enable -.global rt_hw_context_switch -.global rt_hw_context_switch_to -.global rt_hw_context_switch_interrupt - -.equ NOINT, 0xc0 - -/* - * rt_base_t rt_hw_interrupt_disable(); - 关闭中断，关闭å‰è¿”回CPSR寄存器值 - */ -rt_hw_interrupt_disable: - //EXPORT rt_hw_interrupt_disable - MRS r0, cpsr - ORR r1, r0, #NOINT - MSR cpsr_c, r1 - BX lr - //ENDP - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - æ¢å¤ä¸­æ–­çŠ¶æ€ - */ -rt_hw_interrupt_enable: - //EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0 - BX lr - //ENDP - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to - è¿›è¡Œçº¿ç¨‹çš„ä¸Šä¸‹æ–‡åˆ‡æ¢ - */ -rt_hw_context_switch: - //EXPORT rt_hw_context_switch - STMFD sp!, {lr} /* push pc (lr should be pushed in place of PC) */ - /* 把LR寄存器压入栈（这个函数返回åŽçš„下一个执行处） */ - STMFD sp!, {r0-r12, lr} /* push lr & register file */ - /* 把R0 – R12以åŠLR压入栈 */ - - MRS r4, cpsr /* 读å–CPSR寄存器到R4寄存器 */ - STMFD sp!, {r4} /* push cpsr */ - /* 把R4寄存器压栈（å³ä¸Šä¸€æŒ‡ä»¤å–出的CPSR寄存器） */ - MRS r4, spsr /* 读å–SPSR寄存器到R4寄存器 */ - STMFD sp!, {r4} /* push spsr */ - /* 把R4寄存器压栈（å³SPSR寄存器） */ - - STR sp, [r0] /* store sp in preempted tasks TCB */ - /* 把栈指针更新到TCBçš„sp，是由R0传入此函数 */ - /* 到这里æ¢å‡ºçº¿ç¨‹çš„上下文都ä¿å­˜åœ¨æ ˆä¸­ */ - LDR sp, [r1] /* get new task stack pointer */ - /* 载入切æ¢åˆ°çº¿ç¨‹çš„TCBçš„sp */ - /* 从切æ¢åˆ°çº¿ç¨‹çš„栈中æ¢å¤ä¸Šä¸‹æ–‡ï¼Œæ¬¡åºå’Œä¿å­˜çš„时候刚好相å */ - - LDMFD sp!, {r4} /* pop new task spsr */ - /* 出栈到R4寄存器（ä¿å­˜äº†SPSR寄存器） */ - MSR spsr_cxsf, r4 /* æ¢å¤SPSR寄存器 */ - LDMFD sp!, {r4} /* pop new task cpsr */ - /* 出栈到R4寄存器（ä¿å­˜äº†CPSR寄存器） */ - MSR cpsr_cxsf, r4 /* æ¢å¤CPSR寄存器 */ - - LDMFD sp!, {r0-r12, lr, pc} /* pop new task r0-r12, lr & pc */ - /* 对R0 – R12åŠLRã€PC进行æ¢å¤ */ - //ENDP - -rt_hw_context_switch_to: - //EXPORT rt_hw_context_switch_to - LDR sp, [r0] /* get new task stack pointer */ - /* 获得切æ¢åˆ°çº¿ç¨‹çš„SP指针 */ - - LDMFD sp!, {r4} /* pop new task spsr */ - /* 出栈R4寄存器（ä¿å­˜äº†SPSR寄存器值） */ - MSR spsr_cxsf, r4 /* æ¢å¤SPSR寄存器 */ - LDMFD sp!, {r4} /* pop new task cpsr */ - /* 出栈R4寄存器（ä¿å­˜äº†CPSR寄存器值） */ - MSR cpsr_cxsf, r4 /* æ¢å¤CPSR寄存器 */ - - LDMFD sp!, {r0-r12, lr, pc} /* pop new task r0-r12, lr & pc */ - /* æ¢å¤R0 – R12，LRåŠPC寄存器 */ - //ENDP - -rt_hw_context_switch_interrupt: - //EXPORT rt_hw_context_switch_interrupt - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] /* 载入中断中切æ¢æ ‡è‡´åœ°å€ */ - CMP r3, #1 /* 等于 1 ？*/ - BEQ _reswitch /* 如果等于1，跳转到_reswitch*/ - MOV r3, #1 /* set rt_thread_switch_interrupt_flag to 1*/ - /* 设置中断中切æ¢æ ‡å¿—ä½1 */ - STR r3, [r2] /* */ - LDR r2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread*/ - STR r0, [r2] /* ä¿å­˜åˆ‡æ¢å‡ºçº¿ç¨‹æ ˆæŒ‡é’ˆ*/ -_reswitch: - LDR r2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread*/ - STR r1, [r2] /* ä¿å­˜åˆ‡æ¢åˆ°çº¿ç¨‹æ ˆæŒ‡é’ˆ*/ - BX lr - //ENDP - - //END diff --git a/rt-thread/libcpu/arm/lpc214x/context_rvds.S b/rt-thread/libcpu/arm/lpc214x/context_rvds.S deleted file mode 100644 index c5cb59d..0000000 --- a/rt-thread/libcpu/arm/lpc214x/context_rvds.S +++ /dev/null @@ -1,160 +0,0 @@ -;/* -; * Copyright (c) 2006-2022, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2009-01-20 Bernard first version -; * 2011-07-22 Bernard added thumb mode porting -; */ - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled - -NOINT EQU 0xc0 ; disable interrupt in psr - - AREA |.text|, CODE, READONLY, ALIGN=2 - ARM - REQUIRE8 - PRESERVE8 - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ -rt_hw_interrupt_disable PROC - EXPORT rt_hw_interrupt_disable - MRS r0, cpsr - ORR r1, r0, #NOINT - MSR cpsr_c, r1 - BX lr - ENDP - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ -rt_hw_interrupt_enable PROC - EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0 - BX lr - ENDP - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ -rt_hw_context_switch PROC - EXPORT rt_hw_context_switch - STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC) - STMFD sp!, {r0-r12, lr} ; push lr & register file - - MRS r4, cpsr - TST lr, #0x01 - BEQ _ARM_MODE - ORR r4, r4, #0x20 ; it's thumb code -_ARM_MODE - STMFD sp!, {r4} ; push cpsr - - STR sp, [r0] ; store sp in preempted tasks TCB - LDR sp, [r1] ; get new task stack pointer - - LDMFD sp!, {r4} ; pop new task cpsr to spsr - MSR spsr_cxsf, r4 - BIC r4, r4, #0x20 ; must be ARM mode - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr - ENDP - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; */ -rt_hw_context_switch_to PROC - EXPORT rt_hw_context_switch_to - LDR sp, [r0] ; get new task stack pointer - - LDMFD sp!, {r4} ; pop new task cpsr to spsr - MSR spsr_cxsf, r4 - BIC r4, r4, #0x20 ; must be ARM mode - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr - ENDP - -;/* -; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); -; */ - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -rt_hw_context_switch_interrupt PROC - EXPORT rt_hw_context_switch_interrupt - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1 - STR r3, [r2] - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - BX lr - ENDP - -; /* -; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) -; */ -rt_hw_context_switch_interrupt_do PROC - EXPORT rt_hw_context_switch_interrupt_do - MOV r1, #0 ; clear flag - STR r1, [r0] - - LDMFD sp!, {r0-r12,lr}; reload saved registers - STMFD sp!, {r0-r3} ; save r0-r3 - MOV r1, sp - ADD sp, sp, #16 ; restore sp - SUB r2, lr, #4 ; save old task's pc to r2 - - MRS r3, spsr ; get cpsr of interrupt thread - - ; switch to SVC mode and no interrupt - MSR cpsr_c, #I_Bit:OR:F_Bit:OR:Mode_SVC - - STMFD sp!, {r2} ; push old task's pc - STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 - MOV r4, r1 ; Special optimised code below - MOV r5, r3 - LDMFD r4!, {r0-r3} - STMFD sp!, {r0-r3} ; push old task's r3-r0 - STMFD sp!, {r5} ; push old task's cpsr - - LDR r4, =rt_interrupt_from_thread - LDR r5, [r4] - STR sp, [r5] ; store sp in preempted tasks's TCB - - LDR r6, =rt_interrupt_to_thread - LDR r6, [r6] - LDR sp, [r6] ; get new task's stack pointer - - LDMFD sp!, {r4} ; pop new task's cpsr to spsr - MSR spsr_cxsf, r4 - BIC r4, r4, #0x20 ; must be ARM mode - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr - ENDP - - END diff --git a/rt-thread/libcpu/arm/lpc214x/cpuport.c b/rt-thread/libcpu/arm/lpc214x/cpuport.c deleted file mode 100644 index a1f594d..0000000 --- a/rt-thread/libcpu/arm/lpc214x/cpuport.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-06-15 aozima the first version for lpc214x - * 2013-03-29 aozima Modify the interrupt interface implementations. - */ - -#include -#include -#include "lpc214x.h" - -#define MAX_HANDLERS 32 -#define SVCMODE 0x13 - -extern rt_uint32_t rt_interrupt_nest; - -/* exception and interrupt handler table */ -struct rt_irq_desc irq_desc[MAX_HANDLERS]; - -/** - * @addtogroup LPC214x - */ -/*@{*/ - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - unsigned long *stk; - - stk = (unsigned long *)stack_addr; - *(stk) = (unsigned long)tentry; /* entry point */ - *(--stk) = (unsigned long)texit; /* lr */ - *(--stk) = 0; /* r12 */ - *(--stk) = 0; /* r11 */ - *(--stk) = 0; /* r10 */ - *(--stk) = 0; /* r9 */ - *(--stk) = 0; /* r8 */ - *(--stk) = 0; /* r7 */ - *(--stk) = 0; /* r6 */ - *(--stk) = 0; /* r5 */ - *(--stk) = 0; /* r4 */ - *(--stk) = 0; /* r3 */ - *(--stk) = 0; /* r2 */ - *(--stk) = 0; /* r1 */ - *(--stk) = (unsigned long)parameter; /* r0 : argument */ - - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/* exception and interrupt handler table */ -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -void rt_hw_interrupt_handler(int vector, void *param) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - rt_base_t index; - rt_uint32_t *vect_addr, *vect_ctl; - - /* initialize VIC*/ - VICIntEnClr = 0xffffffff; - VICVectAddr = 0; - /* set all to IRQ */ - VICIntSelect = 0; - - rt_memset(irq_desc, 0x00, sizeof(irq_desc)); - for (index = 0; index < MAX_HANDLERS; index ++) - { - irq_desc[index].handler = rt_hw_interrupt_handler; - - vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (index << 2)); - vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (index << 2)); - - *vect_addr = (rt_uint32_t)&irq_desc[index]; - *vect_ctl = 0xF; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - VICIntEnClr = (1 << vector); -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - VICIntEnable = (1 << vector); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param handler the interrupt service routine to be installed - * @param param the interrupt service function parameter - * @param name the interrupt name - * @return old handler - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if(vector >= 0 && vector < MAX_HANDLERS) - { - rt_uint32_t* vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (vector << 2)); - - /* assign IRQ slot and enable this slot */ - *vect_ctl = 0x20 | (vector & 0x1F); - - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = handler; - irq_desc[vector].param = param; - } - } - - return old_handler; -} - -/** - * this function will reset CPU - * - */ -RT_WEAK void rt_hw_cpu_reset(void) -{ -} - -/** - * this function will shutdown CPU - * - */ -RT_WEAK void rt_hw_cpu_shutdown() -{ - rt_kprintf("shutdown...\n"); - - while (1); -} - -void rt_hw_trap_irq(void) -{ - int irqno; - struct rt_irq_desc* irq; - extern struct rt_irq_desc irq_desc[]; - - irq = (struct rt_irq_desc*) VICVectAddr; - irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); - - /* invoke isr */ - irq->handler(irqno, irq->param); - - /* acknowledge Interrupt */ - // VICVectAddr = 0; -} - -void rt_hw_trap_fiq(void) -{ - rt_kprintf("fast interrupt request\n"); -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/lpc214x/lpc214x.h b/rt-thread/libcpu/arm/lpc214x/lpc214x.h deleted file mode 100644 index 21691f8..0000000 --- a/rt-thread/libcpu/arm/lpc214x/lpc214x.h +++ /dev/null @@ -1,393 +0,0 @@ -/***********************************************************************/ -/* This file is part of the uVision/ARM development tools */ -/* Copyright KEIL ELEKTRONIK GmbH 2002-2005 */ -/***********************************************************************/ -/* */ -/* LPC214X.H: Header file for Philips LPC2141/42/44/46/48 */ -/* */ -/***********************************************************************/ - -#ifndef __LPC214x_H -#define __LPC214x_H - -/* Vectored Interrupt Controller (VIC) */ -#define VICIRQStatus (*((volatile unsigned long *) 0xFFFFF000)) -#define VICFIQStatus (*((volatile unsigned long *) 0xFFFFF004)) -#define VICRawIntr (*((volatile unsigned long *) 0xFFFFF008)) -#define VICIntSelect (*((volatile unsigned long *) 0xFFFFF00C)) -#define VICIntEnable (*((volatile unsigned long *) 0xFFFFF010)) -#define VICIntEnClr (*((volatile unsigned long *) 0xFFFFF014)) -#define VICSoftInt (*((volatile unsigned long *) 0xFFFFF018)) -#define VICSoftIntClr (*((volatile unsigned long *) 0xFFFFF01C)) -#define VICProtection (*((volatile unsigned long *) 0xFFFFF020)) -#define VICVectAddr (*((volatile unsigned long *) 0xFFFFF030)) -#define VICDefVectAddr (*((volatile unsigned long *) 0xFFFFF034)) -#define VICVectAddr0 (*((volatile unsigned long *) 0xFFFFF100)) -#define VICVectAddr1 (*((volatile unsigned long *) 0xFFFFF104)) -#define VICVectAddr2 (*((volatile unsigned long *) 0xFFFFF108)) -#define VICVectAddr3 (*((volatile unsigned long *) 0xFFFFF10C)) -#define VICVectAddr4 (*((volatile unsigned long *) 0xFFFFF110)) -#define VICVectAddr5 (*((volatile unsigned long *) 0xFFFFF114)) -#define VICVectAddr6 (*((volatile unsigned long *) 0xFFFFF118)) -#define VICVectAddr7 (*((volatile unsigned long *) 0xFFFFF11C)) -#define VICVectAddr8 (*((volatile unsigned long *) 0xFFFFF120)) -#define VICVectAddr9 (*((volatile unsigned long *) 0xFFFFF124)) -#define VICVectAddr10 (*((volatile unsigned long *) 0xFFFFF128)) -#define VICVectAddr11 (*((volatile unsigned long *) 0xFFFFF12C)) -#define VICVectAddr12 (*((volatile unsigned long *) 0xFFFFF130)) -#define VICVectAddr13 (*((volatile unsigned long *) 0xFFFFF134)) -#define VICVectAddr14 (*((volatile unsigned long *) 0xFFFFF138)) -#define VICVectAddr15 (*((volatile unsigned long *) 0xFFFFF13C)) -#define VICVectCntl0 (*((volatile unsigned long *) 0xFFFFF200)) -#define VICVectCntl1 (*((volatile unsigned long *) 0xFFFFF204)) -#define VICVectCntl2 (*((volatile unsigned long *) 0xFFFFF208)) -#define VICVectCntl3 (*((volatile unsigned long *) 0xFFFFF20C)) -#define VICVectCntl4 (*((volatile unsigned long *) 0xFFFFF210)) -#define VICVectCntl5 (*((volatile unsigned long *) 0xFFFFF214)) -#define VICVectCntl6 (*((volatile unsigned long *) 0xFFFFF218)) -#define VICVectCntl7 (*((volatile unsigned long *) 0xFFFFF21C)) -#define VICVectCntl8 (*((volatile unsigned long *) 0xFFFFF220)) -#define VICVectCntl9 (*((volatile unsigned long *) 0xFFFFF224)) -#define VICVectCntl10 (*((volatile unsigned long *) 0xFFFFF228)) -#define VICVectCntl11 (*((volatile unsigned long *) 0xFFFFF22C)) -#define VICVectCntl12 (*((volatile unsigned long *) 0xFFFFF230)) -#define VICVectCntl13 (*((volatile unsigned long *) 0xFFFFF234)) -#define VICVectCntl14 (*((volatile unsigned long *) 0xFFFFF238)) -#define VICVectCntl15 (*((volatile unsigned long *) 0xFFFFF23C)) - -/* Pin Connect Block */ -#define PINSEL0 (*((volatile unsigned long *) 0xE002C000)) -#define PINSEL1 (*((volatile unsigned long *) 0xE002C004)) -#define PINSEL2 (*((volatile unsigned long *) 0xE002C014)) - -/* General Purpose Input/Output (GPIO) */ -#define IOPIN0 (*((volatile unsigned long *) 0xE0028000)) -#define IOSET0 (*((volatile unsigned long *) 0xE0028004)) -#define IODIR0 (*((volatile unsigned long *) 0xE0028008)) -#define IOCLR0 (*((volatile unsigned long *) 0xE002800C)) -#define IOPIN1 (*((volatile unsigned long *) 0xE0028010)) -#define IOSET1 (*((volatile unsigned long *) 0xE0028014)) -#define IODIR1 (*((volatile unsigned long *) 0xE0028018)) -#define IOCLR1 (*((volatile unsigned long *) 0xE002801C)) -#define IO0PIN (*((volatile unsigned long *) 0xE0028000)) -#define IO0SET (*((volatile unsigned long *) 0xE0028004)) -#define IO0DIR (*((volatile unsigned long *) 0xE0028008)) -#define IO0CLR (*((volatile unsigned long *) 0xE002800C)) -#define IO1PIN (*((volatile unsigned long *) 0xE0028010)) -#define IO1SET (*((volatile unsigned long *) 0xE0028014)) -#define IO1DIR (*((volatile unsigned long *) 0xE0028018)) -#define IO1CLR (*((volatile unsigned long *) 0xE002801C)) -#define FIO0DIR (*((volatile unsigned long *) 0x3FFFC000)) -#define FIO0MASK (*((volatile unsigned long *) 0x3FFFC010)) -#define FIO0PIN (*((volatile unsigned long *) 0x3FFFC014)) -#define FIO0SET (*((volatile unsigned long *) 0x3FFFC018)) -#define FIO0CLR (*((volatile unsigned long *) 0x3FFFC01C)) -#define FIO1DIR (*((volatile unsigned long *) 0x3FFFC020)) -#define FIO1MASK (*((volatile unsigned long *) 0x3FFFC030)) -#define FIO1PIN (*((volatile unsigned long *) 0x3FFFC034)) -#define FIO1SET (*((volatile unsigned long *) 0x3FFFC038)) -#define FIO1CLR (*((volatile unsigned long *) 0x3FFFC03C)) - -/* Memory Accelerator Module (MAM) */ -#define MAMCR (*((volatile unsigned char *) 0xE01FC000)) -#define MAMTIM (*((volatile unsigned char *) 0xE01FC004)) -#define MEMMAP (*((volatile unsigned char *) 0xE01FC040)) - -/* Phase Locked Loop 0 (PLL0) */ -#define PLL0CON (*((volatile unsigned char *) 0xE01FC080)) -#define PLL0CFG (*((volatile unsigned char *) 0xE01FC084)) -#define PLL0STAT (*((volatile unsigned short*) 0xE01FC088)) -#define PLL0FEED (*((volatile unsigned char *) 0xE01FC08C)) - -/* Phase Locked Loop 1 (PLL1) */ -#define PLL1CON (*((volatile unsigned char *) 0xE01FC0A0)) -#define PLL1CFG (*((volatile unsigned char *) 0xE01FC0A4)) -#define PLL1STAT (*((volatile unsigned short*) 0xE01FC0A8)) -#define PLL1FEED (*((volatile unsigned char *) 0xE01FC0AC)) - -/* VPB Divider */ -#define VPBDIV (*((volatile unsigned char *) 0xE01FC100)) - -/* Power Control */ -#define PCON (*((volatile unsigned char *) 0xE01FC0C0)) -#define PCONP (*((volatile unsigned long *) 0xE01FC0C4)) - -/* External Interrupts */ -#define EXTINT (*((volatile unsigned char *) 0xE01FC140)) -#define INTWAKE (*((volatile unsigned short*) 0xE01FC144)) -#define EXTMODE (*((volatile unsigned char *) 0xE01FC148)) -#define EXTPOLAR (*((volatile unsigned char *) 0xE01FC14C)) - -/* Reset */ -#define RSID (*((volatile unsigned char *) 0xE01FC180)) - -/* Code Security / Debugging */ -#define CSPR (*((volatile unsigned char *) 0xE01FC184)) - -/* System Control Miscellaneous */ -#define SCS (*((volatile unsigned long *) 0xE01FC1A0)) - -/* Timer 0 */ -#define T0IR (*((volatile unsigned long *) 0xE0004000)) -#define T0TCR (*((volatile unsigned long *) 0xE0004004)) -#define T0TC (*((volatile unsigned long *) 0xE0004008)) -#define T0PR (*((volatile unsigned long *) 0xE000400C)) -#define T0PC (*((volatile unsigned long *) 0xE0004010)) -#define T0MCR (*((volatile unsigned long *) 0xE0004014)) -#define T0MR0 (*((volatile unsigned long *) 0xE0004018)) -#define T0MR1 (*((volatile unsigned long *) 0xE000401C)) -#define T0MR2 (*((volatile unsigned long *) 0xE0004020)) -#define T0MR3 (*((volatile unsigned long *) 0xE0004024)) -#define T0CCR (*((volatile unsigned long *) 0xE0004028)) -#define T0CR0 (*((volatile unsigned long *) 0xE000402C)) -#define T0CR1 (*((volatile unsigned long *) 0xE0004030)) -#define T0CR2 (*((volatile unsigned long *) 0xE0004034)) -#define T0CR3 (*((volatile unsigned long *) 0xE0004038)) -#define T0EMR (*((volatile unsigned long *) 0xE000403C)) -#define T0CTCR (*((volatile unsigned long *) 0xE0004070)) - -/* Timer 1 */ -#define T1IR (*((volatile unsigned long *) 0xE0008000)) -#define T1TCR (*((volatile unsigned long *) 0xE0008004)) -#define T1TC (*((volatile unsigned long *) 0xE0008008)) -#define T1PR (*((volatile unsigned long *) 0xE000800C)) -#define T1PC (*((volatile unsigned long *) 0xE0008010)) -#define T1MCR (*((volatile unsigned long *) 0xE0008014)) -#define T1MR0 (*((volatile unsigned long *) 0xE0008018)) -#define T1MR1 (*((volatile unsigned long *) 0xE000801C)) -#define T1MR2 (*((volatile unsigned long *) 0xE0008020)) -#define T1MR3 (*((volatile unsigned long *) 0xE0008024)) -#define T1CCR (*((volatile unsigned long *) 0xE0008028)) -#define T1CR0 (*((volatile unsigned long *) 0xE000802C)) -#define T1CR1 (*((volatile unsigned long *) 0xE0008030)) -#define T1CR2 (*((volatile unsigned long *) 0xE0008034)) -#define T1CR3 (*((volatile unsigned long *) 0xE0008038)) -#define T1EMR (*((volatile unsigned long *) 0xE000803C)) -#define T1CTCR (*((volatile unsigned long *) 0xE0008070)) - -/* Pulse Width Modulator (PWM) */ -#define PWMIR (*((volatile unsigned long *) 0xE0014000)) -#define PWMTCR (*((volatile unsigned long *) 0xE0014004)) -#define PWMTC (*((volatile unsigned long *) 0xE0014008)) -#define PWMPR (*((volatile unsigned long *) 0xE001400C)) -#define PWMPC (*((volatile unsigned long *) 0xE0014010)) -#define PWMMCR (*((volatile unsigned long *) 0xE0014014)) -#define PWMMR0 (*((volatile unsigned long *) 0xE0014018)) -#define PWMMR1 (*((volatile unsigned long *) 0xE001401C)) -#define PWMMR2 (*((volatile unsigned long *) 0xE0014020)) -#define PWMMR3 (*((volatile unsigned long *) 0xE0014024)) -#define PWMMR4 (*((volatile unsigned long *) 0xE0014040)) -#define PWMMR5 (*((volatile unsigned long *) 0xE0014044)) -#define PWMMR6 (*((volatile unsigned long *) 0xE0014048)) -#define PWMPCR (*((volatile unsigned long *) 0xE001404C)) -#define PWMLER (*((volatile unsigned long *) 0xE0014050)) - -/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ -#define U0RBR (*((volatile unsigned char *) 0xE000C000)) -#define U0THR (*((volatile unsigned char *) 0xE000C000)) -#define U0IER (*((volatile unsigned long *) 0xE000C004)) -#define U0IIR (*((volatile unsigned long *) 0xE000C008)) -#define U0FCR (*((volatile unsigned char *) 0xE000C008)) -#define U0LCR (*((volatile unsigned char *) 0xE000C00C)) -#define U0MCR (*((volatile unsigned char *) 0xE000C010)) -#define U0LSR (*((volatile unsigned char *) 0xE000C014)) -#define U0MSR (*((volatile unsigned char *) 0xE000C018)) -#define U0SCR (*((volatile unsigned char *) 0xE000C01C)) -#define U0DLL (*((volatile unsigned char *) 0xE000C000)) -#define U0DLM (*((volatile unsigned char *) 0xE000C004)) -#define U0ACR (*((volatile unsigned long *) 0xE000C020)) -#define U0FDR (*((volatile unsigned long *) 0xE000C028)) -#define U0TER (*((volatile unsigned char *) 0xE000C030)) - -/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ -#define U1RBR (*((volatile unsigned char *) 0xE0010000)) -#define U1THR (*((volatile unsigned char *) 0xE0010000)) -#define U1IER (*((volatile unsigned long *) 0xE0010004)) -#define U1IIR (*((volatile unsigned long *) 0xE0010008)) -#define U1FCR (*((volatile unsigned char *) 0xE0010008)) -#define U1LCR (*((volatile unsigned char *) 0xE001000C)) -#define U1MCR (*((volatile unsigned char *) 0xE0010010)) -#define U1LSR (*((volatile unsigned char *) 0xE0010014)) -#define U1MSR (*((volatile unsigned char *) 0xE0010018)) -#define U1SCR (*((volatile unsigned char *) 0xE001001C)) -#define U1DLL (*((volatile unsigned char *) 0xE0010000)) -#define U1DLM (*((volatile unsigned char *) 0xE0010004)) -#define U1ACR (*((volatile unsigned long *) 0xE0010020)) -#define U1FDR (*((volatile unsigned long *) 0xE0010028)) -#define U1TER (*((volatile unsigned char *) 0xE0010030)) - -/* I2C Interface 0 */ -#define I2C0CONSET (*((volatile unsigned char *) 0xE001C000)) -#define I2C0STAT (*((volatile unsigned char *) 0xE001C004)) -#define I2C0DAT (*((volatile unsigned char *) 0xE001C008)) -#define I2C0ADR (*((volatile unsigned char *) 0xE001C00C)) -#define I2C0SCLH (*((volatile unsigned short*) 0xE001C010)) -#define I2C0SCLL (*((volatile unsigned short*) 0xE001C014)) -#define I2C0CONCLR (*((volatile unsigned char *) 0xE001C018)) - -/* I2C Interface 1 */ -#define I2C1CONSET (*((volatile unsigned char *) 0xE005C000)) -#define I2C1STAT (*((volatile unsigned char *) 0xE005C004)) -#define I2C1DAT (*((volatile unsigned char *) 0xE005C008)) -#define I2C1ADR (*((volatile unsigned char *) 0xE005C00C)) -#define I2C1SCLH (*((volatile unsigned short*) 0xE005C010)) -#define I2C1SCLL (*((volatile unsigned short*) 0xE005C014)) -#define I2C1CONCLR (*((volatile unsigned char *) 0xE005C018)) - -/* SPI0 (Serial Peripheral Interface 0) */ -#define S0SPCR (*((volatile unsigned short*) 0xE0020000)) -#define S0SPSR (*((volatile unsigned char *) 0xE0020004)) -#define S0SPDR (*((volatile unsigned short*) 0xE0020008)) -#define S0SPCCR (*((volatile unsigned char *) 0xE002000C)) -#define S0SPINT (*((volatile unsigned char *) 0xE002001C)) - -/* SSP Controller (SPI1) */ -#define SSPCR0 (*((volatile unsigned short*) 0xE0068000)) -#define SSPCR1 (*((volatile unsigned char *) 0xE0068004)) -#define SSPDR (*((volatile unsigned short*) 0xE0068008)) -#define SSPSR (*((volatile unsigned char *) 0xE006800C)) -#define SSPCPSR (*((volatile unsigned char *) 0xE0068010)) -#define SSPIMSC (*((volatile unsigned char *) 0xE0068014)) -#define SSPRIS (*((volatile unsigned char *) 0xE0068018)) -#define SSPMIS (*((volatile unsigned char *) 0xE006801C)) -#define SSPICR (*((volatile unsigned char *) 0xE0068020)) - -/* Real Time Clock */ -#define ILR (*((volatile unsigned char *) 0xE0024000)) -#define CTC (*((volatile unsigned short*) 0xE0024004)) -#define CCR (*((volatile unsigned char *) 0xE0024008)) -#define CIIR (*((volatile unsigned char *) 0xE002400C)) -#define AMR (*((volatile unsigned char *) 0xE0024010)) -#define CTIME0 (*((volatile unsigned long *) 0xE0024014)) -#define CTIME1 (*((volatile unsigned long *) 0xE0024018)) -#define CTIME2 (*((volatile unsigned long *) 0xE002401C)) -#define SEC (*((volatile unsigned char *) 0xE0024020)) -#define MIN (*((volatile unsigned char *) 0xE0024024)) -#define HOUR (*((volatile unsigned char *) 0xE0024028)) -#define DOM (*((volatile unsigned char *) 0xE002402C)) -#define DOW (*((volatile unsigned char *) 0xE0024030)) -#define DOY (*((volatile unsigned short*) 0xE0024034)) -#define MONTH (*((volatile unsigned char *) 0xE0024038)) -#define YEAR (*((volatile unsigned short*) 0xE002403C)) -#define ALSEC (*((volatile unsigned char *) 0xE0024060)) -#define ALMIN (*((volatile unsigned char *) 0xE0024064)) -#define ALHOUR (*((volatile unsigned char *) 0xE0024068)) -#define ALDOM (*((volatile unsigned char *) 0xE002406C)) -#define ALDOW (*((volatile unsigned char *) 0xE0024070)) -#define ALDOY (*((volatile unsigned short*) 0xE0024074)) -#define ALMON (*((volatile unsigned char *) 0xE0024078)) -#define ALYEAR (*((volatile unsigned short*) 0xE002407C)) -#define PREINT (*((volatile unsigned short*) 0xE0024080)) -#define PREFRAC (*((volatile unsigned short*) 0xE0024084)) - -/* A/D Converter 0 (AD0) */ -#define AD0CR (*((volatile unsigned long *) 0xE0034000)) -#define AD0GDR (*((volatile unsigned long *) 0xE0034004)) -#define AD0STAT (*((volatile unsigned long *) 0xE0034030)) -#define AD0INTEN (*((volatile unsigned long *) 0xE003400C)) -#define AD0DR0 (*((volatile unsigned long *) 0xE0034010)) -#define AD0DR1 (*((volatile unsigned long *) 0xE0034014)) -#define AD0DR2 (*((volatile unsigned long *) 0xE0034018)) -#define AD0DR3 (*((volatile unsigned long *) 0xE003401C)) -#define AD0DR4 (*((volatile unsigned long *) 0xE0034020)) -#define AD0DR5 (*((volatile unsigned long *) 0xE0034024)) -#define AD0DR6 (*((volatile unsigned long *) 0xE0034028)) -#define AD0DR7 (*((volatile unsigned long *) 0xE003402C)) - -/* A/D Converter 1 (AD1) */ -#define AD1CR (*((volatile unsigned long *) 0xE0060000)) -#define AD1GDR (*((volatile unsigned long *) 0xE0060004)) -#define AD1STAT (*((volatile unsigned long *) 0xE0060030)) -#define AD1INTEN (*((volatile unsigned long *) 0xE006000C)) -#define AD1DR0 (*((volatile unsigned long *) 0xE0060010)) -#define AD1DR1 (*((volatile unsigned long *) 0xE0060014)) -#define AD1DR2 (*((volatile unsigned long *) 0xE0060018)) -#define AD1DR3 (*((volatile unsigned long *) 0xE006001C)) -#define AD1DR4 (*((volatile unsigned long *) 0xE0060020)) -#define AD1DR5 (*((volatile unsigned long *) 0xE0060024)) -#define AD1DR6 (*((volatile unsigned long *) 0xE0060028)) -#define AD1DR7 (*((volatile unsigned long *) 0xE006002C)) - -/* A/D Converter Global */ -#define ADGSR (*((volatile unsigned long *) 0xE0034008)) - -/* D/A Converter */ -#define DACR (*((volatile unsigned long *) 0xE006C000)) - -/* Watchdog */ -#define WDMOD (*((volatile unsigned char *) 0xE0000000)) -#define WDTC (*((volatile unsigned long *) 0xE0000004)) -#define WDFEED (*((volatile unsigned char *) 0xE0000008)) -#define WDTV (*((volatile unsigned long *) 0xE000000C)) - -/* USB Controller */ -#define USBIntSt (*((volatile unsigned long *) 0xE01FC1C0)) -#define USBDevIntSt (*((volatile unsigned long *) 0xE0090000)) -#define USBDevIntEn (*((volatile unsigned long *) 0xE0090004)) -#define USBDevIntClr (*((volatile unsigned long *) 0xE0090008)) -#define USBDevIntSet (*((volatile unsigned long *) 0xE009000C)) -#define USBDevIntPri (*((volatile unsigned char *) 0xE009002C)) -#define USBEpIntSt (*((volatile unsigned long *) 0xE0090030)) -#define USBEpIntEn (*((volatile unsigned long *) 0xE0090034)) -#define USBEpIntClr (*((volatile unsigned long *) 0xE0090038)) -#define USBEpIntSet (*((volatile unsigned long *) 0xE009003C)) -#define USBEpIntPri (*((volatile unsigned long *) 0xE0090040)) -#define USBReEp (*((volatile unsigned long *) 0xE0090044)) -#define USBEpInd (*((volatile unsigned long *) 0xE0090048)) -#define USBMaxPSize (*((volatile unsigned long *) 0xE009004C)) -#define USBRxData (*((volatile unsigned long *) 0xE0090018)) -#define USBRxPLen (*((volatile unsigned long *) 0xE0090020)) -#define USBTxData (*((volatile unsigned long *) 0xE009001C)) -#define USBTxPLen (*((volatile unsigned long *) 0xE0090024)) -#define USBCtrl (*((volatile unsigned long *) 0xE0090028)) -#define USBCmdCode (*((volatile unsigned long *) 0xE0090010)) -#define USBCmdData (*((volatile unsigned long *) 0xE0090014)) -#define USBDMARSt (*((volatile unsigned long *) 0xE0090050)) -#define USBDMARClr (*((volatile unsigned long *) 0xE0090054)) -#define USBDMARSet (*((volatile unsigned long *) 0xE0090058)) -#define USBUDCAH (*((volatile unsigned long *) 0xE0090080)) -#define USBEpDMASt (*((volatile unsigned long *) 0xE0090084)) -#define USBEpDMAEn (*((volatile unsigned long *) 0xE0090088)) -#define USBEpDMADis (*((volatile unsigned long *) 0xE009008C)) -#define USBDMAIntSt (*((volatile unsigned long *) 0xE0090090)) -#define USBDMAIntEn (*((volatile unsigned long *) 0xE0090094)) -#define USBEoTIntSt (*((volatile unsigned long *) 0xE00900A0)) -#define USBEoTIntClr (*((volatile unsigned long *) 0xE00900A4)) -#define USBEoTIntSet (*((volatile unsigned long *) 0xE00900A8)) -#define USBNDDRIntSt (*((volatile unsigned long *) 0xE00900AC)) -#define USBNDDRIntClr (*((volatile unsigned long *) 0xE00900B0)) -#define USBNDDRIntSet (*((volatile unsigned long *) 0xE00900B4)) -#define USBSysErrIntSt (*((volatile unsigned long *) 0xE00900B8)) -#define USBSysErrIntClr (*((volatile unsigned long *) 0xE00900BC)) -#define USBSysErrIntSet (*((volatile unsigned long *) 0xE00900C0)) - -#define VIC_BASE_ADDR 0xFFFFF000 - -enum LPC214x_INT -{ - WDT_INT = 0, - SW_INT_reserved, - DbgCommRx_INT, - DbgCommTx_INT, - TIMER0_INT, - TIMER1_INT, - UART0_INT, - UART1_INT, - PWM0_INT, - I2C0_INT, - SP0_INT, - SP1_INT, - PLL_INT, - RTC_INT, - EINT0_INT, - EINT1_INT, - EINT2_INT, - EINT3_INT, - ADC0_INT, - I2C1_INT, - BOD_INT, - ADC1_INT, - USB_INT -}; - -#endif // __LPC214x_H diff --git a/rt-thread/libcpu/arm/lpc214x/start_rvds.S b/rt-thread/libcpu/arm/lpc214x/start_rvds.S deleted file mode 100644 index bef523b..0000000 --- a/rt-thread/libcpu/arm/lpc214x/start_rvds.S +++ /dev/null @@ -1,464 +0,0 @@ -;/*****************************************************************************/ -;/* STARTUP.S: Startup file for Philips LPC2000 */ -;/*****************************************************************************/ -;/* <<< Use Configuration Wizard in Context Menu >>> */ -;/*****************************************************************************/ -;/* This file is part of the uVision/ARM development tools. */ -;/* Copyright (c) 2005-2007 Keil Software. All rights reserved. */ -;/* This software may only be used under the terms of a valid, current, */ -;/* end user licence from KEIL for a compatible version of KEIL software */ -;/* development tools. Nothing else gives you the right to use this software. */ -;/*****************************************************************************/ - - -;/* -; * The STARTUP.S code is executed after CPU Reset. This file may be -; * translated with the following SET symbols. In uVision these SET -; * symbols are entered under Options - ASM - Define. -; * -; * REMAP: when set the startup code initializes the register MEMMAP -; * which overwrites the settings of the CPU configuration pins. The -; * startup and interrupt vectors are remapped from: -; * 0x00000000 default setting (not remapped) -; * 0x80000000 when EXTMEM_MODE is used -; * 0x40000000 when RAM_MODE is used -; * -; * EXTMEM_MODE: when set the device is configured for code execution -; * from external memory starting at address 0x80000000. -; * -; * RAM_MODE: when set the device is configured for code execution -; * from on-chip RAM starting at address 0x40000000. -; * -; * EXTERNAL_MODE: when set the PIN2SEL values are written that enable -; * the external BUS at startup. -; */ - - -; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled - - -;// Stack Configuration (Stack Sizes in Bytes) -;// Undefined Mode <0x0-0xFFFFFFFF:8> -;// Supervisor Mode <0x0-0xFFFFFFFF:8> -;// Abort Mode <0x0-0xFFFFFFFF:8> -;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> -;// Interrupt Mode <0x0-0xFFFFFFFF:8> -;// User/System Mode <0x0-0xFFFFFFFF:8> -;// - -UND_Stack_Size EQU 0x00000000 -SVC_Stack_Size EQU 0x00000100 -ABT_Stack_Size EQU 0x00000000 -FIQ_Stack_Size EQU 0x00000000 -IRQ_Stack_Size EQU 0x00000100 -USR_Stack_Size EQU 0x00000100 - -ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - -Stack_Mem SPACE USR_Stack_Size -__initial_sp SPACE ISR_Stack_Size - -Stack_Top - - -;// Heap Configuration -;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> -;// - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - -; VPBDIV definitions -VPBDIV EQU 0xE01FC100 ; VPBDIV Address - -;// VPBDIV Setup -;// Peripheral Bus Clock Rate -;// VPBDIV: VPB Clock -;// <0=> VPB Clock = CPU Clock / 4 -;// <1=> VPB Clock = CPU Clock -;// <2=> VPB Clock = CPU Clock / 2 -;// XCLKDIV: XCLK Pin -;// <0=> XCLK Pin = CPU Clock / 4 -;// <1=> XCLK Pin = CPU Clock -;// <2=> XCLK Pin = CPU Clock / 2 -;// -VPBDIV_SETUP EQU 0 -VPBDIV_Val EQU 0x00000000 - - -; Phase Locked Loop (PLL) definitions -PLL_BASE EQU 0xE01FC080 ; PLL Base Address -PLLCON_OFS EQU 0x00 ; PLL Control Offset -PLLCFG_OFS EQU 0x04 ; PLL Configuration Offset -PLLSTAT_OFS EQU 0x08 ; PLL Status Offset -PLLFEED_OFS EQU 0x0C ; PLL Feed Offset -PLLCON_PLLE EQU (1<<0) ; PLL Enable -PLLCON_PLLC EQU (1<<1) ; PLL Connect -PLLCFG_MSEL EQU (0x1F<<0) ; PLL Multiplier -PLLCFG_PSEL EQU (0x03<<5) ; PLL Divider -PLLSTAT_PLOCK EQU (1<<10) ; PLL Lock Status - -;// PLL Setup -;// MSEL: PLL Multiplier Selection -;// <1-32><#-1> -;// M Value -;// PSEL: PLL Divider Selection -;// <0=> 1 <1=> 2 <2=> 4 <3=> 8 -;// P Value -;// -PLL_SETUP EQU 1 -PLLCFG_Val EQU 0x00000024 - - -; Memory Accelerator Module (MAM) definitions -MAM_BASE EQU 0xE01FC000 ; MAM Base Address -MAMCR_OFS EQU 0x00 ; MAM Control Offset -MAMTIM_OFS EQU 0x04 ; MAM Timing Offset - -;// MAM Setup -;// MAM Control -;// <0=> Disabled -;// <1=> Partially Enabled -;// <2=> Fully Enabled -;// Mode -;// MAM Timing -;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3 -;// <4=> 4 <5=> 5 <6=> 6 <7=> 7 -;// Fetch Cycles -;// -MAM_SETUP EQU 1 -MAMCR_Val EQU 0x00000002 -MAMTIM_Val EQU 0x00000004 - - -; External Memory Controller (EMC) definitions -EMC_BASE EQU 0xFFE00000 ; EMC Base Address -BCFG0_OFS EQU 0x00 ; BCFG0 Offset -BCFG1_OFS EQU 0x04 ; BCFG1 Offset -BCFG2_OFS EQU 0x08 ; BCFG2 Offset -BCFG3_OFS EQU 0x0C ; BCFG3 Offset - -;// External Memory Controller (EMC) -EMC_SETUP EQU 0 - -;// Bank Configuration 0 (BCFG0) -;// IDCY: Idle Cycles <0-15> -;// WST1: Wait States 1 <0-31> -;// WST2: Wait States 2 <0-31> -;// RBLE: Read Byte Lane Enable -;// WP: Write Protect -;// BM: Burst ROM -;// MW: Memory Width <0=> 8-bit <1=> 16-bit -;// <2=> 32-bit <3=> Reserved -;// -BCFG0_SETUP EQU 0 -BCFG0_Val EQU 0x0000FBEF - -;// Bank Configuration 1 (BCFG1) -;// IDCY: Idle Cycles <0-15> -;// WST1: Wait States 1 <0-31> -;// WST2: Wait States 2 <0-31> -;// RBLE: Read Byte Lane Enable -;// WP: Write Protect -;// BM: Burst ROM -;// MW: Memory Width <0=> 8-bit <1=> 16-bit -;// <2=> 32-bit <3=> Reserved -;// -BCFG1_SETUP EQU 0 -BCFG1_Val EQU 0x0000FBEF - -;// Bank Configuration 2 (BCFG2) -;// IDCY: Idle Cycles <0-15> -;// WST1: Wait States 1 <0-31> -;// WST2: Wait States 2 <0-31> -;// RBLE: Read Byte Lane Enable -;// WP: Write Protect -;// BM: Burst ROM -;// MW: Memory Width <0=> 8-bit <1=> 16-bit -;// <2=> 32-bit <3=> Reserved -;// -BCFG2_SETUP EQU 0 -BCFG2_Val EQU 0x0000FBEF - -;// Bank Configuration 3 (BCFG3) -;// IDCY: Idle Cycles <0-15> -;// WST1: Wait States 1 <0-31> -;// WST2: Wait States 2 <0-31> -;// RBLE: Read Byte Lane Enable -;// WP: Write Protect -;// BM: Burst ROM -;// MW: Memory Width <0=> 8-bit <1=> 16-bit -;// <2=> 32-bit <3=> Reserved -;// -BCFG3_SETUP EQU 0 -BCFG3_Val EQU 0x0000FBEF - -;// End of EMC - - -; External Memory Pins definitions -PINSEL2 EQU 0xE002C014 ; PINSEL2 Address -PINSEL2_Val EQU 0x0E6149E4 ; CS0..3, OE, WE, BLS0..3, - ; D0..31, A2..23, JTAG Pins - - - PRESERVE8 - - -; Area Definition and Entry Point -; Startup Code must be linked first at Address at which it expects to run. - - AREA RESET, CODE, READONLY - ARM - - -; Exception Vectors -; Mapped to Address 0. -; Absolute addressing mode must be used. -; Dummy Handlers are implemented as infinite loops which can be modified. - -Vectors LDR PC, Reset_Addr - LDR PC, Undef_Addr - LDR PC, SWI_Addr - LDR PC, PAbt_Addr - LDR PC, DAbt_Addr - NOP ; Reserved Vector - LDR PC, IRQ_Addr - LDR PC, FIQ_Addr - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SWI_Addr DCD SWI_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler - DCD 0 ; Reserved Address -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - -Undef_Handler B Undef_Handler -SWI_Handler B SWI_Handler -PAbt_Handler B PAbt_Handler -DAbt_Handler B DAbt_Handler -FIQ_Handler B FIQ_Handler - - -; Reset Handler - - EXPORT Reset_Handler -Reset_Handler - - -; Setup External Memory Pins - IF :DEF:EXTERNAL_MODE - LDR R0, =PINSEL2 - LDR R1, =PINSEL2_Val - STR R1, [R0] - ENDIF - - -; Setup External Memory Controller - IF EMC_SETUP <> 0 - LDR R0, =EMC_BASE - - IF BCFG0_SETUP <> 0 - LDR R1, =BCFG0_Val - STR R1, [R0, #BCFG0_OFS] - ENDIF - - IF BCFG1_SETUP <> 0 - LDR R1, =BCFG1_Val - STR R1, [R0, #BCFG1_OFS] - ENDIF - - IF BCFG2_SETUP <> 0 - LDR R1, =BCFG2_Val - STR R1, [R0, #BCFG2_OFS] - ENDIF - - IF BCFG3_SETUP <> 0 - LDR R1, =BCFG3_Val - STR R1, [R0, #BCFG3_OFS] - ENDIF - - ENDIF ; EMC_SETUP - - -; Setup VPBDIV - IF VPBDIV_SETUP <> 0 - LDR R0, =VPBDIV - LDR R1, =VPBDIV_Val - STR R1, [R0] - ENDIF - - -; Setup PLL - IF PLL_SETUP <> 0 - LDR R0, =PLL_BASE - MOV R1, #0xAA - MOV R2, #0x55 - -; Configure and Enable PLL - MOV R3, #PLLCFG_Val - STR R3, [R0, #PLLCFG_OFS] - MOV R3, #PLLCON_PLLE - STR R3, [R0, #PLLCON_OFS] - STR R1, [R0, #PLLFEED_OFS] - STR R2, [R0, #PLLFEED_OFS] - -; Wait until PLL Locked -PLL_Loop LDR R3, [R0, #PLLSTAT_OFS] - ANDS R3, R3, #PLLSTAT_PLOCK - BEQ PLL_Loop - -; Switch to PLL Clock - MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC) - STR R3, [R0, #PLLCON_OFS] - STR R1, [R0, #PLLFEED_OFS] - STR R2, [R0, #PLLFEED_OFS] - ENDIF ; PLL_SETUP - - -; Setup MAM - IF MAM_SETUP <> 0 - LDR R0, =MAM_BASE - MOV R1, #MAMTIM_Val - STR R1, [R0, #MAMTIM_OFS] - MOV R1, #MAMCR_Val - STR R1, [R0, #MAMCR_OFS] - ENDIF ; MAM_SETUP - - -; Memory Mapping (when Interrupt Vectors are in RAM) -MEMMAP EQU 0xE01FC040 ; Memory Mapping Control - IF :DEF:REMAP - LDR R0, =MEMMAP - IF :DEF:EXTMEM_MODE - MOV R1, #3 - ELIF :DEF:RAM_MODE - MOV R1, #2 - ELSE - MOV R1, #1 - ENDIF - STR R1, [R0] - ENDIF - - -; Initialise Interrupt System -; ... - - -; Setup Stack for each mode - - LDR R0, =Stack_Top - -; Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #UND_Stack_Size - -; Enter Abort Mode and set its Stack Pointer - MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #ABT_Stack_Size - -; Enter FIQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #FIQ_Stack_Size - -; Enter IRQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #IRQ_Stack_Size - -; Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit - MOV SP, R0 - ; SUB R0, R0, #SVC_Stack_Size - -; Enter User Mode and set its Stack Pointer - ; RT-Thread does not use user mode - ; MSR CPSR_c, #Mode_USR - IF :DEF:__MICROLIB - - EXPORT __initial_sp - - ELSE - - ; MOV SP, R0 - ; SUB SL, SP, #USR_Stack_Size - - ENDIF - -; Enter the C code - - IMPORT __main - LDR R0, =__main - BX R0 - - IMPORT rt_interrupt_enter - IMPORT rt_interrupt_leave - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - IMPORT rt_hw_trap_irq - IMPORT rt_hw_context_switch_interrupt_do - -IRQ_Handler PROC - EXPORT IRQ_Handler - STMFD sp!, {r0-r12,lr} - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; if rt_thread_switch_interrupt_flag set, jump to - ; rt_hw_context_switch_interrupt_do and don't return - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD sp!, {r0-r12,lr} - SUBS pc, lr, #4 - ENDP - - IF :DEF:__MICROLIB - - EXPORT __heap_base - EXPORT __heap_limit - - ELSE -; User Initial Stack & Heap - AREA |.text|, CODE, READONLY - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + USR_Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDIF - - END diff --git a/rt-thread/libcpu/arm/lpc214x/startup_gcc.S b/rt-thread/libcpu/arm/lpc214x/startup_gcc.S deleted file mode 100644 index 22f316b..0000000 --- a/rt-thread/libcpu/arm/lpc214x/startup_gcc.S +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ - .extern main /* 引入外部Cå…¥å£ */ - - .extern rt_interrupt_enter - .extern rt_interrupt_leave - .extern rt_thread_switch_interrupt_flag - .extern rt_interrupt_from_thread - .extern rt_interrupt_to_thread - .extern rt_hw_trap_irq - - .global start - .global endless_loop - .global rt_hw_context_switch_interrupt_do - - /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ - .set MODE_USR, 0x10 /* User Mode */ - .set MODE_FIQ, 0x11 /* FIQ Mode */ - .set MODE_IRQ, 0x12 /* IRQ Mode */ - .set MODE_SVC, 0x13 /* Supervisor Mode */ - .set MODE_ABT, 0x17 /* Abort Mode */ - .set MODE_UND, 0x1B /* Undefined Mode */ - .set MODE_SYS, 0x1F /* System Mode */ - - .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ - .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ - .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */ - .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */ - - /* VPBDIV definitions*/ - .equ VPBDIV, 0xE01FC100 - .set VPBDIV_VALUE, 0x00000000 - - /* Phase Locked Loop (PLL) definitions*/ - .equ PLL_BASE, 0xE01FC080 /* PLL Base Address */ - .equ PLLCON_OFS, 0x00 /* PLL Control Offset */ - .equ PLLCFG_OFS, 0x04 /* PLL Configuration Offset */ - .equ PLLSTAT_OFS, 0x08 /* PLL Status Offset */ - .equ PLLFEED_OFS, 0x0C /* PLL Feed Offset */ - .equ PLLCON_PLLE, (1<<0) /* PLL Enable */ - .equ PLLCON_PLLC, (1<<1) /* PLL Connect */ - .equ PLLCFG_MSEL, (0x1F<<0) /* PLL Multiplier */ - .equ PLLCFG_PSEL, (0x03<<5) /* PLL Divider */ - .equ PLLSTAT_PLOCK, (1<<10) /* PLL Lock Status */ - .equ PLLCFG_Val, 0x00000024 /* MSEL: PLL Multiplier Selection, PSEL: PLL Divider Selection */ - - .equ MEMMAP, 0xE01FC040 /*Memory Mapping Control*/ - - - /* Memory Accelerator Module (MAM) definitions*/ - .equ MAM_BASE, 0xE01FC000 - .equ MAMCR_OFS, 0x00 - .equ MAMTIM_OFS, 0x04 - .equ MAMCR_Val, 0x00000002 - .equ MAMTIM_Val, 0x00000004 - - .equ VICIntEnClr, 0xFFFFF014 - .equ VICIntSelect, 0xFFFFF00C -/************* 目标é…ç½®ç»“æŸ *************/ - - -/* Setup the operating mode & stack.*/ -/* --------------------------------- */ - .global _reset -_reset: - .code 32 - .align 0 - -/************************* PLL_SETUP **********************************/ - ldr r0, =PLL_BASE - mov r1, #0xAA - mov r2, #0x55 - -/* Configure and Enable PLL */ - mov r3, #PLLCFG_Val - str r3, [r0, #PLLCFG_OFS] - mov r3, #PLLCON_PLLE - str r3, [r0, #PLLCON_OFS] - str r1, [r0, #PLLFEED_OFS] - str r2, [r0, #PLLFEED_OFS] - -/* Wait until PLL Locked */ -PLL_Locked_loop: - ldr r3, [r0, #PLLSTAT_OFS] - ands r3, r3, #PLLSTAT_PLOCK - beq PLL_Locked_loop - -/* Switch to PLL Clock */ - mov r3, #(PLLCON_PLLE|PLLCON_PLLC) - str r3, [r0, #PLLCON_OFS] - str r1, [r0, #PLLFEED_OFS] - str R2, [r0, #PLLFEED_OFS] -/************************* PLL_SETUP **********************************/ - -/************************ Setup VPBDIV ********************************/ - ldr r0, =VPBDIV - ldr r1, =VPBDIV_VALUE - str r1, [r0] -/************************ Setup VPBDIV ********************************/ - -/************** Setup MAM **************/ - ldr r0, =MAM_BASE - mov r1, #MAMTIM_Val - str r1, [r0, #MAMTIM_OFS] - mov r1, #MAMCR_Val - str r1, [r0, #MAMCR_OFS] -/************** Setup MAM **************/ - -/************************ setup stack *********************************/ - ldr r0, .undefined_stack_top - sub r0, r0, #4 - msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */ - mov sp, r0 - - ldr r0, .abort_stack_top - sub r0, r0, #4 - msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */ - mov sp, r0 - - ldr r0, .fiq_stack_top - sub r0, r0, #4 - msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */ - mov sp, r0 - - ldr r0, .irq_stack_top - sub r0, r0, #4 - msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */ - mov sp, r0 - - ldr r0, .svc_stack_top - sub r0, r0, #4 - msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */ - mov sp, r0 -/************************ setup stack ********************************/ - - /* copy .data to SRAM */ - ldr r1, =_sidata /* .data start in image */ - ldr r2, =_edata /* .data end in image */ - ldr r3, =_sdata /* sram data start */ -data_loop: - ldr r0, [r1, #0] - str r0, [r3] - - add r1, r1, #4 - add r3, r3, #4 - - cmp r3, r2 /* check if data to clear */ - blo data_loop /* loop until done */ - - /* clear .bss */ - mov r0,#0 /* get a zero */ - ldr r1,=__bss_start /* bss start */ - ldr r2,=__bss_end /* bss end */ - -bss_loop: - cmp r1,r2 /* check if data to clear */ - strlo r0,[r1],#4 /* clear 4 bytes */ - blo bss_loop /* loop until done */ - - - /* call C++ constructors of global objects */ - ldr r0, =__ctors_start__ - ldr r1, =__ctors_end__ - -ctor_loop: - cmp r0, r1 - beq ctor_end - ldr r2, [r0], #4 - stmfd sp!, {r0-r1} - mov lr, pc - bx r2 - ldmfd sp!, {r0-r1} - b ctor_loop -ctor_end: - - /* enter C code */ - bl main - - .align 0 - .undefined_stack_top: - .word _undefined_stack_top - .abort_stack_top: - .word _abort_stack_top - .fiq_stack_top: - .word _fiq_stack_top - .irq_stack_top: - .word _irq_stack_top - .svc_stack_top: - .word _svc_stack_top -/*********************** END Clear BSS ******************************/ - -.section .init,"ax" -.code 32 -.align 0 -.globl _start -_start: - - ldr pc, __start /* reset - _start */ - ldr pc, _undf /* undefined - _undf */ - ldr pc, _swi /* SWI - _swi */ - ldr pc, _pabt /* program abort - _pabt */ - ldr pc, _dabt /* data abort - _dabt */ - .word 0xB8A06F58 /* reserved */ - ldr pc, __IRQ_Handler /* IRQ - read the VIC */ - ldr pc, _fiq /* FIQ - _fiq */ - -__start:.word _reset -_undf: .word __undf /* undefined */ -_swi: .word __swi /* SWI */ -_pabt: .word __pabt /* program abort */ -_dabt: .word __dabt /* data abort */ -temp1: .word 0 -__IRQ_Handler: .word IRQ_Handler -_fiq: .word __fiq /* FIQ */ - -__undf: b . /* undefined */ -__swi : b . -__pabt: b . /* program abort */ -__dabt: b . /* data abort */ -__fiq : b . /* FIQ */ - -/* IRQå…¥å£ */ -IRQ_Handler : - stmfd sp!, {r0-r12,lr} /* 对R0 – R12，LR寄存器压栈 */ - bl rt_interrupt_enter /* 通知RT-Threadè¿›å…¥ä¸­æ–­æ¨¡å¼ */ - bl rt_hw_trap_irq /* 相应中断æœåŠ¡ä¾‹ç¨‹å¤„ç† */ - bl rt_interrupt_leave /* ; 通知RT-Threadè¦ç¦»å¼€ä¸­æ–­æ¨¡å¼ */ - - /* 如果设置了rt_thread_switch_interrupt_flagï¼Œè¿›è¡Œä¸­æ–­ä¸­çš„çº¿ç¨‹ä¸Šä¸‹æ–‡å¤„ç† */ - ldr r0, =rt_thread_switch_interrupt_flag - ldr r1, [r0] - cmp r1, #1 - beq rt_hw_context_switch_interrupt_do /* 中断中切æ¢å‘生 */ - /* 如果跳转了，将ä¸ä¼šå›žæ¥ */ - ldmfd sp!, {r0-r12,lr} /* æ¢å¤æ ˆ */ - subs pc, lr, #4 /* 从IRQ中返回 */ - -/* -* void rt_hw_context_switch_interrupt_do(rt_base_t flag) -* 中断结æŸåŽçš„ä¸Šä¸‹æ–‡åˆ‡æ¢ -*/ -rt_hw_context_switch_interrupt_do: - mov r1, #0 /* clear flag */ - /* 清楚中断中切æ¢æ ‡å¿— */ - str r1, [r0] /* */ - - ldmfd sp!, {r0-r12,lr}/* reload saved registers */ - /* å…ˆæ¢å¤è¢«ä¸­æ–­çº¿ç¨‹çš„上下文 */ - stmfd sp!, {r0-r3} /* save r0-r3 */ - /* 对R0 – R3压栈，因为åŽé¢ä¼šç”¨åˆ° */ - mov r1, sp /* 把此处的栈值ä¿å­˜åˆ°R1 */ - add sp, sp, #16 /* restore sp */ - /* æ¢å¤IRQ的栈，åŽé¢ä¼šè·³å‡ºIRQæ¨¡å¼ */ - sub r2, lr, #4 /* save old task's pc to r2 */ - /* ä¿å­˜åˆ‡æ¢å‡ºçº¿ç¨‹çš„PC到R2 */ - - mrs r3, spsr /* disable interrupt ä¿å­˜ä¸­æ–­å‰çš„CPSR到R3寄存器 */ - /* 获得SPSR寄存器值 */ - orr r0, r3, #I_BIT|F_BIT - msr spsr_c, r0 /* 关闭SPSR中的IRQ/FIQ中断 */ - - ldr r0, =.+8 /* 把当å‰åœ°å€+8载入到R0寄存器中 switch to interrupted task's stack */ - movs pc, r0 /* 退出IRQ模å¼ï¼Œç”±äºŽSPSR被设置æˆå…³ä¸­æ–­æ¨¡å¼ */ - /* 所以从IRQ返回åŽï¼Œä¸­æ–­å¹¶æ²¡æœ‰æ‰“å¼€ - ; R0寄存器中的ä½ç½®å®žé™…就是下一æ¡æŒ‡ä»¤ï¼Œ - ; å³PC继续往下走 - ; 此时 - ; 模å¼å·²ç»æ¢æˆä¸­æ–­å‰çš„SVC模å¼ï¼Œ - ; SP寄存器也是SVC模å¼ä¸‹çš„栈寄存器 - ; R1ä¿å­˜IRQ模å¼ä¸‹çš„栈指针 - ; R2ä¿å­˜åˆ‡æ¢å‡ºçº¿ç¨‹çš„PC - ; R3ä¿å­˜åˆ‡æ¢å‡ºçº¿ç¨‹çš„CPSR */ - stmfd sp!, {r2} /* push old task's pc */ - /* ä¿å­˜åˆ‡æ¢å‡ºä»»åŠ¡çš„PC */ - stmfd sp!, {r4-r12,lr}/* push old task's lr,r12-r4 */ - /* ä¿å­˜R4 – R12，LR寄存器 */ - mov r4, r1 /* Special optimised code below */ - /* R1ä¿å­˜æœ‰åŽ‹æ ˆR0 – R3处的栈ä½ç½® */ - mov r5, r3 /* R3切æ¢å‡ºçº¿ç¨‹çš„CPSR */ - ldmfd r4!, {r0-r3} /* æ¢å¤R0 – R3 */ - stmfd sp!, {r0-r3} /* push old task's r3-r0 */ - /* R0 – R3压栈到切æ¢å‡ºçº¿ç¨‹ */ - stmfd sp!, {r5} /* push old task's psr */ - /* 切æ¢å‡ºçº¿ç¨‹CPSR压栈 */ - mrs r4, spsr - stmfd sp!, {r4} /* push old task's spsr */ - /* 切æ¢å‡ºçº¿ç¨‹SPSR压栈 */ - - ldr r4, =rt_interrupt_from_thread - ldr r5, [r4] - str sp, [r5] /* store sp in preempted tasks's TCB */ - /* ä¿å­˜åˆ‡æ¢å‡ºçº¿ç¨‹çš„SP指针 */ - - ldr r6, =rt_interrupt_to_thread - ldr r6, [r6] - ldr sp, [r6] /* get new task's stack pointer */ - /* 获得切æ¢åˆ°çº¿ç¨‹çš„æ ˆ */ - - ldmfd sp!, {r4} /* pop new task's spsr */ - /* æ¢å¤SPSR */ - msr SPSR_cxsf, r4 - ldmfd sp!, {r4} /* pop new task's psr */ - /* æ¢å¤CPSR */ - msr CPSR_cxsf, r4 - - ldmfd sp!, {r0-r12,lr,pc} /* pop new task's r0-r12,lr & pc */ - /* æ¢å¤R0 – R12，LRåŠPC寄存器 */ - -/* 代ç åŠ å¯†åŠŸèƒ½ */ -#if defined(CODE_PROTECTION) -.org 0x01FC -.word 0x87654321 -#endif - diff --git a/rt-thread/libcpu/arm/lpc24xx/LPC24xx.h b/rt-thread/libcpu/arm/lpc24xx/LPC24xx.h deleted file mode 100644 index 827310c..0000000 --- a/rt-thread/libcpu/arm/lpc24xx/LPC24xx.h +++ /dev/null @@ -1,1197 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2008-12-11 xuxinming first version - */ - -#ifndef __LPC24xx_H -#define __LPC24xx_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -#define MCLK (72000000) - -/* Vectored Interrupt Controller (VIC) */ -#define VIC_BASE_ADDR 0xFFFFF000 -#define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000)) -#define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004)) -#define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008)) -#define VICIntSelect (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C)) -#define VICIntEnable (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010)) -#define VICIntEnClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014)) -#define VICSoftInt (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018)) -#define VICSoftIntClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C)) -#define VICProtection (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020)) -#define VICSWPrioMask (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x024)) - -#define VICVectAddr0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x100)) -#define VICVectAddr1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x104)) -#define VICVectAddr2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x108)) -#define VICVectAddr3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x10C)) -#define VICVectAddr4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x110)) -#define VICVectAddr5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x114)) -#define VICVectAddr6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x118)) -#define VICVectAddr7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x11C)) -#define VICVectAddr8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x120)) -#define VICVectAddr9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x124)) -#define VICVectAddr10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x128)) -#define VICVectAddr11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x12C)) -#define VICVectAddr12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x130)) -#define VICVectAddr13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x134)) -#define VICVectAddr14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x138)) -#define VICVectAddr15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x13C)) -#define VICVectAddr16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x140)) -#define VICVectAddr17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x144)) -#define VICVectAddr18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x148)) -#define VICVectAddr19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x14C)) -#define VICVectAddr20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x150)) -#define VICVectAddr21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x154)) -#define VICVectAddr22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x158)) -#define VICVectAddr23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x15C)) -#define VICVectAddr24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x160)) -#define VICVectAddr25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x164)) -#define VICVectAddr26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x168)) -#define VICVectAddr27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x16C)) -#define VICVectAddr28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x170)) -#define VICVectAddr29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x174)) -#define VICVectAddr30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x178)) -#define VICVectAddr31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x17C)) - -/* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx, -these registers are known as "VICVectPriority(x)". */ -#define VICVectCntl0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200)) -#define VICVectCntl1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204)) -#define VICVectCntl2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208)) -#define VICVectCntl3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C)) -#define VICVectCntl4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210)) -#define VICVectCntl5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214)) -#define VICVectCntl6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218)) -#define VICVectCntl7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C)) -#define VICVectCntl8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220)) -#define VICVectCntl9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224)) -#define VICVectCntl10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228)) -#define VICVectCntl11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C)) -#define VICVectCntl12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230)) -#define VICVectCntl13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234)) -#define VICVectCntl14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238)) -#define VICVectCntl15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C)) -#define VICVectCntl16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x240)) -#define VICVectCntl17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x244)) -#define VICVectCntl18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x248)) -#define VICVectCntl19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x24C)) -#define VICVectCntl20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x250)) -#define VICVectCntl21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x254)) -#define VICVectCntl22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x258)) -#define VICVectCntl23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x25C)) -#define VICVectCntl24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x260)) -#define VICVectCntl25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x264)) -#define VICVectCntl26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x268)) -#define VICVectCntl27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x26C)) -#define VICVectCntl28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x270)) -#define VICVectCntl29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x274)) -#define VICVectCntl30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x278)) -#define VICVectCntl31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x27C)) - -#define VICVectAddr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0xF00)) - - -/* Pin Connect Block */ -#define PINSEL_BASE_ADDR 0xE002C000 -#define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00)) -#define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04)) -#define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08)) -#define PINSEL3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x0C)) -#define PINSEL4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x10)) -#define PINSEL5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14)) -#define PINSEL6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x18)) -#define PINSEL7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x1C)) -#define PINSEL8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x20)) -#define PINSEL9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x24)) -#define PINSEL10 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x28)) -#define PINSEL11 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x2C)) - -#define PINMODE0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x40)) -#define PINMODE1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x44)) -#define PINMODE2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x48)) -#define PINMODE3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x4C)) -#define PINMODE4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x50)) -#define PINMODE5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x54)) -#define PINMODE6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x58)) -#define PINMODE7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x5C)) -#define PINMODE8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x60)) -#define PINMODE9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64)) - -/* General Purpose Input/Output (GPIO) */ -#define GPIO_BASE_ADDR 0xE0028000 -#define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00)) -#define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04)) -#define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08)) -#define IOCLR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C)) -#define IOPIN1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10)) -#define IOSET1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14)) -#define IODIR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18)) -#define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C)) - -/* GPIO Interrupt Registers */ -#define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) -#define IO0_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94)) -#define IO0_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84)) -#define IO0_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88)) -#define IO0_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C)) - -#define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) -#define IO2_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4)) -#define IO2_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4)) -#define IO2_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8)) -#define IO2_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xAC)) - -#define IO_INT_STAT (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80)) - -#define PARTCFG_BASE_ADDR 0x3FFF8000 -#define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) - -/* Fast I/O setup */ -#define FIO_BASE_ADDR 0x3FFFC000 -#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) -#define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10)) -#define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14)) -#define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18)) -#define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C)) - -#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) -#define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30)) -#define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34)) -#define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38)) -#define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C)) - -#define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) -#define FIO2MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50)) -#define FIO2PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54)) -#define FIO2SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58)) -#define FIO2CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C)) - -#define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) -#define FIO3MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70)) -#define FIO3PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74)) -#define FIO3SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78)) -#define FIO3CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C)) - -#define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) -#define FIO4MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90)) -#define FIO4PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94)) -#define FIO4SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98)) -#define FIO4CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C)) - -/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ -#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) -#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) -#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) -#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) -#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) - -#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) -#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) -#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) -#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) -#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) - -#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) -#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) -#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) -#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) -#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) - -#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) -#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) -#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) -#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) -#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) - -#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) -#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) -#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) -#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) -#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) - -#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) -#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) -#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) -#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) -#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) - -#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) -#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) -#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) -#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) -#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) - -#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) -#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) -#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) -#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) -#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) - -#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) -#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) -#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) -#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) -#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) - -#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) -#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) -#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) -#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) -#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) - -#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) -#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) -#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) -#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) -#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) - -#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) -#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) -#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) -#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) -#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) - -#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) -#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) -#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) -#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) -#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) - -#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) -#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35)) -#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) -#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) -#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) - -#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) -#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) -#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) -#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) -#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) - -#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) -#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) -#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) -#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) -#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) - -#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) -#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) -#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) -#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) -#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) - -#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) -#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) -#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) -#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) -#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) - -#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) -#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) -#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) -#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) -#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) - -#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) -#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) -#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) -#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) -#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) - -#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) -#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) -#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) -#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) -#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) - -#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) -#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) -#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) -#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) -#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) - -#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) -#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) -#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) -#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) -#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) - -#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) -#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) -#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) -#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) -#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) - -#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) - -#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) -#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) -#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) -#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) -#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) - -#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) -#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) -#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) -#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) -#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) - -#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) -#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) -#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) -#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) -#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) - -#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) - -#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) -#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) -#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) -#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) -#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) - - -/* System Control Block(SCB) modules include Memory Accelerator Module, -Phase Locked Loop, VPB divider, Power Control, External Interrupt, -Reset, and Code Security/Debugging */ -#define SCB_BASE_ADDR 0xE01FC000 - -/* Memory Accelerator Module (MAM) */ -#define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000)) -#define MAMTIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004)) -#define MEMMAP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x040)) - -/* Phase Locked Loop (PLL) */ -#define PLLCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080)) -#define PLLCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084)) -#define PLLSTAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088)) -#define PLLFEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C)) - -/* Power Control */ -#define PCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0)) -#define PCONP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4)) - -/* Clock Divider */ -#define CCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104)) -#define USBCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108)) -#define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C)) -#define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8)) -#define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC)) - -/* External Interrupts */ -#define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140)) -#define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144)) -#define EXTMODE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148)) -#define EXTPOLAR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C)) - -/* Reset, reset source identification */ -#define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180)) - -/* RSID, code security protection */ -#define CSPR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x184)) - -/* AHB configuration */ -#define AHBCFG1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x188)) -#define AHBCFG2 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C)) - -/* System Controls and Status */ -#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) - -/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers -are for LPC24xx only. */ -#define STATIC_MEM0_BASE 0x80000000 -#define STATIC_MEM1_BASE 0x81000000 -#define STATIC_MEM2_BASE 0x82000000 -#define STATIC_MEM3_BASE 0x83000000 - -#define DYNAMIC_MEM0_BASE 0xA0000000 -#define DYNAMIC_MEM1_BASE 0xB0000000 -#define DYNAMIC_MEM2_BASE 0xC0000000 -#define DYNAMIC_MEM3_BASE 0xD0000000 - -/* External Memory Controller (EMC) */ -#define EMC_BASE_ADDR 0xFFE08000 -#define EMC_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000)) -#define EMC_STAT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004)) -#define EMC_CONFIG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008)) - -/* Dynamic RAM access registers */ -#define EMC_DYN_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x020)) -#define EMC_DYN_RFSH (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x024)) -#define EMC_DYN_RD_CFG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x028)) -#define EMC_DYN_RP (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x030)) -#define EMC_DYN_RAS (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x034)) -#define EMC_DYN_SREX (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x038)) -#define EMC_DYN_APR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x03C)) -#define EMC_DYN_DAL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x040)) -#define EMC_DYN_WR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x044)) -#define EMC_DYN_RC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x048)) -#define EMC_DYN_RFC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x04C)) -#define EMC_DYN_XSR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x050)) -#define EMC_DYN_RRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x054)) -#define EMC_DYN_MRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x058)) - -#define EMC_DYN_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x100)) -#define EMC_DYN_RASCAS0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x104)) -#define EMC_DYN_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x140)) -#define EMC_DYN_RASCAS1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x144)) -#define EMC_DYN_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x160)) -#define EMC_DYN_RASCAS2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x164)) -#define EMC_DYN_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x180)) -#define EMC_DYN_RASCAS3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x184)) - -/* static RAM access registers */ -#define EMC_STA_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x200)) -#define EMC_STA_WAITWEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x204)) -#define EMC_STA_WAITOEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x208)) -#define EMC_STA_WAITRD0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x20C)) -#define EMC_STA_WAITPAGE0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x210)) -#define EMC_STA_WAITWR0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x214)) -#define EMC_STA_WAITTURN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x218)) - -#define EMC_STA_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x220)) -#define EMC_STA_WAITWEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x224)) -#define EMC_STA_WAITOEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x228)) -#define EMC_STA_WAITRD1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x22C)) -#define EMC_STA_WAITPAGE1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x230)) -#define EMC_STA_WAITWR1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x234)) -#define EMC_STA_WAITTURN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x238)) - -#define EMC_STA_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x240)) -#define EMC_STA_WAITWEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x244)) -#define EMC_STA_WAITOEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x248)) -#define EMC_STA_WAITRD2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x24C)) -#define EMC_STA_WAITPAGE2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x250)) -#define EMC_STA_WAITWR2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x254)) -#define EMC_STA_WAITTURN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x258)) - -#define EMC_STA_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x260)) -#define EMC_STA_WAITWEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x264)) -#define EMC_STA_WAITOEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x268)) -#define EMC_STA_WAITRD3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x26C)) -#define EMC_STA_WAITPAGE3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x270)) -#define EMC_STA_WAITWR3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x274)) -#define EMC_STA_WAITTURN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x278)) - -#define EMC_STA_EXT_WAIT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880)) - - -/* Timer 0 */ -#define TMR0_BASE_ADDR 0xE0004000 -#define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00)) -#define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04)) -#define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08)) -#define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C)) -#define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10)) -#define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14)) -#define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18)) -#define T0MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C)) -#define T0MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20)) -#define T0MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24)) -#define T0CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28)) -#define T0CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C)) -#define T0CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30)) -#define T0CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34)) -#define T0CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38)) -#define T0EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C)) -#define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70)) - -/* Timer 1 */ -#define TMR1_BASE_ADDR 0xE0008000 -#define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00)) -#define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04)) -#define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08)) -#define T1PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C)) -#define T1PC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10)) -#define T1MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14)) -#define T1MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18)) -#define T1MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C)) -#define T1MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20)) -#define T1MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24)) -#define T1CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28)) -#define T1CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C)) -#define T1CR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30)) -#define T1CR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34)) -#define T1CR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38)) -#define T1EMR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C)) -#define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70)) - -/* Timer 2 */ -#define TMR2_BASE_ADDR 0xE0070000 -#define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00)) -#define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04)) -#define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08)) -#define T2PR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C)) -#define T2PC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10)) -#define T2MCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14)) -#define T2MR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18)) -#define T2MR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C)) -#define T2MR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20)) -#define T2MR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24)) -#define T2CCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28)) -#define T2CR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C)) -#define T2CR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30)) -#define T2CR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34)) -#define T2CR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38)) -#define T2EMR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C)) -#define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70)) - -/* Timer 3 */ -#define TMR3_BASE_ADDR 0xE0074000 -#define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00)) -#define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04)) -#define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08)) -#define T3PR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C)) -#define T3PC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10)) -#define T3MCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14)) -#define T3MR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18)) -#define T3MR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C)) -#define T3MR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20)) -#define T3MR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24)) -#define T3CCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28)) -#define T3CR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C)) -#define T3CR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30)) -#define T3CR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34)) -#define T3CR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38)) -#define T3EMR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C)) -#define T3CTCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70)) - - -/* Pulse Width Modulator (PWM) */ -#define PWM0_BASE_ADDR 0xE0014000 -#define PWM0IR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00)) -#define PWM0TCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04)) -#define PWM0TC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08)) -#define PWM0PR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x0C)) -#define PWM0PC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x10)) -#define PWM0MCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x14)) -#define PWM0MR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x18)) -#define PWM0MR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x1C)) -#define PWM0MR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x20)) -#define PWM0MR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x24)) -#define PWM0CCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x28)) -#define PWM0CR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x2C)) -#define PWM0CR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x30)) -#define PWM0CR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x34)) -#define PWM0CR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x38)) -#define PWM0EMR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x3C)) -#define PWM0MR4 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x40)) -#define PWM0MR5 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x44)) -#define PWM0MR6 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x48)) -#define PWM0PCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x4C)) -#define PWM0LER (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50)) -#define PWM0CTCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70)) - -#define PWM1_BASE_ADDR 0xE0018000 -#define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00)) -#define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04)) -#define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08)) -#define PWM1PR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C)) -#define PWM1PC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10)) -#define PWM1MCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14)) -#define PWM1MR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18)) -#define PWM1MR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C)) -#define PWM1MR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20)) -#define PWM1MR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24)) -#define PWM1CCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28)) -#define PWM1CR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C)) -#define PWM1CR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30)) -#define PWM1CR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x34)) -#define PWM1CR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x38)) -#define PWM1EMR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x3C)) -#define PWM1MR4 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x40)) -#define PWM1MR5 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x44)) -#define PWM1MR6 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x48)) -#define PWM1PCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x4C)) -#define PWM1LER (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x50)) -#define PWM1CTCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x70)) - - -/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ -#define UART0_BASE_ADDR 0xE000C000 -#define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) -#define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) -#define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) -#define U0DLM (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) -#define U0IER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) -#define U0IIR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) -#define U0FCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) -#define U0LCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C)) -#define U0LSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14)) -#define U0SCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C)) -#define U0ACR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20)) -#define U0ICR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x24)) -#define U0FDR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28)) -#define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30)) - -/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ -#define UART1_BASE_ADDR 0xE0010000 -#define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) -#define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) -#define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) -#define U1DLM (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04)) -#define U1IER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04)) -#define U1IIR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08)) -#define U1FCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08)) -#define U1LCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C)) -#define U1MCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10)) -#define U1LSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14)) -#define U1MSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18)) -#define U1SCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C)) -#define U1ACR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20)) -#define U1FDR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28)) -#define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30)) - -/* Universal Asynchronous Receiver Transmitter 2 (UART2) */ -#define UART2_BASE_ADDR 0xE0078000 -#define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) -#define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) -#define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) -#define U2DLM (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04)) -#define U2IER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04)) -#define U2IIR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08)) -#define U2FCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08)) -#define U2LCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C)) -#define U2LSR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14)) -#define U2SCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C)) -#define U2ACR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20)) -#define U2ICR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x24)) -#define U2FDR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28)) -#define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30)) - -/* Universal Asynchronous Receiver Transmitter 3 (UART3) */ -#define UART3_BASE_ADDR 0xE007C000 -#define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) -#define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) -#define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) -#define U3DLM (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04)) -#define U3IER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04)) -#define U3IIR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08)) -#define U3FCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08)) -#define U3LCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C)) -#define U3LSR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14)) -#define U3SCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C)) -#define U3ACR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20)) -#define U3ICR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24)) -#define U3FDR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28)) -#define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30)) - -/* I2C Interface 0 */ -#define I2C0_BASE_ADDR 0xE001C000 -#define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00)) -#define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04)) -#define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08)) -#define I20ADR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C)) -#define I20SCLH (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10)) -#define I20SCLL (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14)) -#define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18)) - -/* I2C Interface 1 */ -#define I2C1_BASE_ADDR 0xE005C000 -#define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00)) -#define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04)) -#define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08)) -#define I21ADR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C)) -#define I21SCLH (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10)) -#define I21SCLL (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14)) -#define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18)) - -/* I2C Interface 2 */ -#define I2C2_BASE_ADDR 0xE0080000 -#define I22CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00)) -#define I22STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04)) -#define I22DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08)) -#define I22ADR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C)) -#define I22SCLH (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10)) -#define I22SCLL (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14)) -#define I22CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18)) - -/* SPI0 (Serial Peripheral Interface 0) */ -#define SPI0_BASE_ADDR 0xE0020000 -#define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00)) -#define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04)) -#define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08)) -#define S0SPCCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C)) -#define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C)) - -/* SSP0 Controller */ -#define SSP0_BASE_ADDR 0xE0068000 -#define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00)) -#define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04)) -#define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08)) -#define SSP0SR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C)) -#define SSP0CPSR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10)) -#define SSP0IMSC (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14)) -#define SSP0RIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18)) -#define SSP0MIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C)) -#define SSP0ICR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20)) -#define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24)) - -/* SSP1 Controller */ -#define SSP1_BASE_ADDR 0xE0030000 -#define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00)) -#define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04)) -#define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08)) -#define SSP1SR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C)) -#define SSP1CPSR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10)) -#define SSP1IMSC (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14)) -#define SSP1RIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18)) -#define SSP1MIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C)) -#define SSP1ICR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20)) -#define SSP1DMACR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24)) - - -/* Real Time Clock */ -#define RTC_BASE_ADDR 0xE0024000 -#define RTC_ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00)) -#define RTC_CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04)) -#define RTC_CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08)) -#define RTC_CIIR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C)) -#define RTC_AMR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10)) -#define RTC_CTIME0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14)) -#define RTC_CTIME1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18)) -#define RTC_CTIME2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C)) -#define RTC_SEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20)) -#define RTC_MIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24)) -#define RTC_HOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28)) -#define RTC_DOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C)) -#define RTC_DOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30)) -#define RTC_DOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34)) -#define RTC_MONTH (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38)) -#define RTC_YEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C)) -#define RTC_CISS (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40)) -#define RTC_ALSEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60)) -#define RTC_ALMIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64)) -#define RTC_ALHOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68)) -#define RTC_ALDOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C)) -#define RTC_ALDOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70)) -#define RTC_ALDOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74)) -#define RTC_ALMON (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78)) -#define RTC_ALYEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C)) -#define RTC_PREINT (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80)) -#define RTC_PREFRAC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84)) - - -/* A/D Converter 0 (AD0) */ -#define AD0_BASE_ADDR 0xE0034000 -#define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00)) -#define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04)) -#define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C)) -#define AD0DR0 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10)) -#define AD0DR1 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14)) -#define AD0DR2 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18)) -#define AD0DR3 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C)) -#define AD0DR4 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20)) -#define AD0DR5 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24)) -#define AD0DR6 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28)) -#define AD0DR7 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C)) -#define AD0STAT (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30)) - - -/* D/A Converter */ -#define DAC_BASE_ADDR 0xE006C000 -#define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00)) - - -/* Watchdog */ -#define WDG_BASE_ADDR 0xE0000000 -#define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00)) -#define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04)) -#define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08)) -#define WDTV (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C)) -#define WDCLKSEL (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10)) - -/* CAN CONTROLLERS AND ACCEPTANCE FILTER */ -#define CAN_ACCEPT_BASE_ADDR 0xE003C000 -#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00)) -#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04)) -#define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08)) -#define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) -#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10)) -#define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14)) -#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18)) -#define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) - -#define CAN_CENTRAL_BASE_ADDR 0xE0040000 -#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00)) -#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04)) -#define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08)) - -#define CAN1_BASE_ADDR 0xE0044000 -#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) -#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) -#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) -#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) -#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10)) -#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) -#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) -#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) -#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) -#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24)) -#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) -#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) - -#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) -#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) -#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38)) -#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) -#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) -#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) -#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) -#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C)) -#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) -#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) -#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) -#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C)) - -#define CAN2_BASE_ADDR 0xE0048000 -#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) -#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) -#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) -#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) -#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10)) -#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) -#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) -#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) -#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) -#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24)) -#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) -#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) - -#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) -#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) -#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38)) -#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) -#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) -#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) -#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) -#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C)) -#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) -#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) -#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) -#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C)) - - -/* MultiMedia Card Interface(MCI) Controller */ -#define MCI_BASE_ADDR 0xE008C000 -#define MCI_POWER (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00)) -#define MCI_CLOCK (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04)) -#define MCI_ARGUMENT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08)) -#define MCI_COMMAND (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x0C)) -#define MCI_RESP_CMD (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x10)) -#define MCI_RESP0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x14)) -#define MCI_RESP1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x18)) -#define MCI_RESP2 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x1C)) -#define MCI_RESP3 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x20)) -#define MCI_DATA_TMR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x24)) -#define MCI_DATA_LEN (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x28)) -#define MCI_DATA_CTRL (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x2C)) -#define MCI_DATA_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x30)) -#define MCI_STATUS (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x34)) -#define MCI_CLEAR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x38)) -#define MCI_MASK0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x3C)) -#define MCI_MASK1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x40)) -#define MCI_FIFO_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x48)) -#define MCI_FIFO (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x80)) - - -/* I2S Interface Controller (I2S) */ -#define I2S_BASE_ADDR 0xE0088000 -#define I2S_DAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00)) -#define I2S_DAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04)) -#define I2S_TX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08)) -#define I2S_RX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C)) -#define I2S_STATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10)) -#define I2S_DMA1 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14)) -#define I2S_DMA2 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18)) -#define I2S_IRQ (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C)) -#define I2S_TXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20)) -#define I2S_RXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24)) - - -/* General-purpose DMA Controller */ -#define DMA_BASE_ADDR 0xFFE04000 -#define GPDMA_INT_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000)) -#define GPDMA_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004)) -#define GPDMA_INT_TCCLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008)) -#define GPDMA_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C)) -#define GPDMA_INT_ERR_CLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010)) -#define GPDMA_RAW_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014)) -#define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018)) -#define GPDMA_ENABLED_CHNS (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C)) -#define GPDMA_SOFT_BREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020)) -#define GPDMA_SOFT_SREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024)) -#define GPDMA_SOFT_LBREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028)) -#define GPDMA_SOFT_LSREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C)) -#define GPDMA_CONFIG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030)) -#define GPDMA_SYNC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034)) - -/* DMA channel 0 registers */ -#define GPDMA_CH0_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100)) -#define GPDMA_CH0_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104)) -#define GPDMA_CH0_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108)) -#define GPDMA_CH0_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C)) -#define GPDMA_CH0_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110)) - -/* DMA channel 1 registers */ -#define GPDMA_CH1_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120)) -#define GPDMA_CH1_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124)) -#define GPDMA_CH1_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128)) -#define GPDMA_CH1_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C)) -#define GPDMA_CH1_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130)) - - -/* USB Controller */ -#define USB_INT_BASE_ADDR 0xE01FC1C0 -#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ - -#define USB_INT_STAT (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00)) - -/* USB Device Interrupt Registers */ -#define DEV_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00)) -#define DEV_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04)) -#define DEV_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08)) -#define DEV_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C)) -#define DEV_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C)) - -/* USB Device Endpoint Interrupt Registers */ -#define EP_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30)) -#define EP_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34)) -#define EP_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38)) -#define EP_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C)) -#define EP_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40)) - -/* USB Device Endpoint Realization Registers */ -#define REALIZE_EP (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44)) -#define EP_INDEX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48)) -#define MAXPACKET_SIZE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C)) - -/* USB Device Command Reagisters */ -#define CMD_CODE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10)) -#define CMD_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14)) - -/* USB Device Data Transfer Registers */ -#define RX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18)) -#define TX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C)) -#define RX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20)) -#define TX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24)) -#define USB_CTRL (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28)) - -/* USB Device DMA Registers */ -#define DMA_REQ_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x50)) -#define DMA_REQ_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x54)) -#define DMA_REQ_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x58)) -#define UDCA_HEAD (*(volatile unsigned long *)(USB_BASE_ADDR + 0x80)) -#define EP_DMA_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x84)) -#define EP_DMA_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x88)) -#define EP_DMA_DIS (*(volatile unsigned long *)(USB_BASE_ADDR + 0x8C)) -#define DMA_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x90)) -#define DMA_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x94)) -#define EOT_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA0)) -#define EOT_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA4)) -#define EOT_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA8)) -#define NDD_REQ_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xAC)) -#define NDD_REQ_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB0)) -#define NDD_REQ_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB4)) -#define SYS_ERR_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB8)) -#define SYS_ERR_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xBC)) -#define SYS_ERR_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xC0)) - -/* USB Host and OTG registers are for LPC24xx only */ -/* USB Host Controller */ -#define USBHC_BASE_ADDR 0xFFE0C000 -#define HC_REVISION (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00)) -#define HC_CONTROL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04)) -#define HC_CMD_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08)) -#define HC_INT_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x0C)) -#define HC_INT_EN (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x10)) -#define HC_INT_DIS (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x14)) -#define HC_HCCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x18)) -#define HC_PERIOD_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x1C)) -#define HC_CTRL_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x20)) -#define HC_CTRL_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x24)) -#define HC_BULK_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x28)) -#define HC_BULK_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x2C)) -#define HC_DONE_HEAD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x30)) -#define HC_FM_INTERVAL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x34)) -#define HC_FM_REMAINING (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x38)) -#define HC_FM_NUMBER (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x3C)) -#define HC_PERIOD_START (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x40)) -#define HC_LS_THRHLD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x44)) -#define HC_RH_DESCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x48)) -#define HC_RH_DESCB (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x4C)) -#define HC_RH_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x50)) -#define HC_RH_PORT_STAT1 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x54)) -#define HC_RH_PORT_STAT2 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58)) - -/* USB OTG Controller */ -#define USBOTG_BASE_ADDR 0xFFE0C100 -#define OTG_INT_STAT (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00)) -#define OTG_INT_EN (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04)) -#define OTG_INT_SET (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08)) -#define OTG_INT_CLR (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C)) -/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ -#define OTG_STAT_CTRL (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) -#define OTG_TIMER (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14)) - -#define USBOTG_I2C_BASE_ADDR 0xFFE0C300 -#define OTG_I2C_RX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) -#define OTG_I2C_TX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) -#define OTG_I2C_STS (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04)) -#define OTG_I2C_CTL (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x08)) -#define OTG_I2C_CLKHI (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C)) -#define OTG_I2C_CLKLO (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10)) - -/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are -OTG_CLK_CTRL and OTG_CLK_STAT respectively. */ -#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 -#define OTG_CLK_CTRL (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) -#define OTG_CLK_STAT (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) - -/* Note: below three register name convention is for LPC23xx USB device only, match -with the spec. update in USB Device Section. */ -#define USBPortSel (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) -#define USBClkCtrl (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) -#define USBClkSt (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) - -/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ -#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ -#define MAC_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */ -#define MAC_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */ -#define MAC_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */ -#define MAC_IPGR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */ -#define MAC_CLRT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */ -#define MAC_MAXF (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */ -#define MAC_SUPP (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */ -#define MAC_TEST (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */ -#define MAC_MCFG (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */ -#define MAC_MCMD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */ -#define MAC_MADR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */ -#define MAC_MWTD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */ -#define MAC_MRDD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */ -#define MAC_MIND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */ - -#define MAC_SA0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */ -#define MAC_SA1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */ -#define MAC_SA2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */ - -#define MAC_COMMAND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */ -#define MAC_STATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */ -#define MAC_RXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */ -#define MAC_RXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */ -#define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */ -#define MAC_RXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */ -#define MAC_RXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */ -#define MAC_TXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */ -#define MAC_TXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */ -#define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */ -#define MAC_TXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */ -#define MAC_TXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */ - -#define MAC_TSV0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */ -#define MAC_TSV1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */ -#define MAC_RSV (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */ - -#define MAC_FLOWCONTROLCNT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */ -#define MAC_FLOWCONTROLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */ - -#define MAC_RXFILTERCTRL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */ -#define MAC_RXFILTERWOLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */ -#define MAC_RXFILTERWOLCLR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */ - -#define MAC_HASHFILTERL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */ -#define MAC_HASHFILTERH (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */ - -#define MAC_INTSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */ -#define MAC_INTENABLE (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */ -#define MAC_INTCLEAR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */ -#define MAC_INTSET (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */ - -#define MAC_POWERDOWN (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */ -#define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ - -/* LCD Controller registers */ -#define LCD_BASE_ADDR 0xFFE10000 /* AHB Peripheral # 4 */ -#define LCD_CFG (*(volatile unsigned long *)(0xE01FC1B8)) -#define LCD_TIMH (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x000)) -#define LCD_TIMV (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x004)) -#define LCD_POL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x008)) -#define LCD_LE (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x00C)) -#define LCD_UPBASE (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x010)) -#define LCD_LPBASE (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x014)) -#define LCD_CTRL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x018)) -#define LCD_INTMSK (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x01C)) -#define LCD_INTRAW (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x020)) -#define LCD_INTSTAT (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x024)) -#define LCD_INTCLR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x028)) -#define LCD_UPCURR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x02C)) -#define LCD_LPCURR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x030)) -#define LCD_PAL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x200)) -#define CRSR_IMG (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x800)) -#define CRSR_CTRL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC00)) -#define CRSR_CFG (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC04)) -#define CRSR_PAL0 (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC08)) -#define CRSR_PAL1 (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC0C)) -#define CRSR_XY (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC10)) -#define CRSR_CLIP (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC14)) -#define CRSR_INTMSK (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC20)) -#define CRSR_INTCLR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC24)) -#define CRSR_INTRAW (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC28)) -#define CRSR_INTSTAT (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC2C)) - -struct rt_hw_register -{ - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; - unsigned long ORIG_r0; -}; - -#ifdef __cplusplus -} -#endif - -#endif // __LPC24xx_H - diff --git a/rt-thread/libcpu/arm/lpc24xx/SConscript b/rt-thread/libcpu/arm/lpc24xx/SConscript deleted file mode 100644 index b259a94..0000000 --- a/rt-thread/libcpu/arm/lpc24xx/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/lpc24xx/context_gcc.S b/rt-thread/libcpu/arm/lpc24xx/context_gcc.S deleted file mode 100644 index b824a91..0000000 --- a/rt-thread/libcpu/arm/lpc24xx/context_gcc.S +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2008-12-11 XuXinming first version - */ - -/*! - * \addtogroup LPC2478 - */ -/*@{*/ - -#define NOINT 0xc0 - -/* - * rt_base_t rt_hw_interrupt_disable(); - */ -.globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mrs r0, cpsr - orr r1, r0, #NOINT - msr cpsr_c, r1 - mov pc, lr - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ -.globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - msr cpsr, r0 - mov pc, lr - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to - */ -.globl rt_hw_context_switch -rt_hw_context_switch: - stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) - stmfd sp!, {r0-r12, lr} @ push lr & register file - - mrs r4, cpsr - stmfd sp!, {r4} @ push cpsr - mrs r4, spsr - stmfd sp!, {r4} @ push spsr - - str sp, [r0] @ store sp in preempted tasks TCB - ldr sp, [r1] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - ldmfd sp!, {r4} @ pop new task cpsr - msr cpsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc} @ pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to - */ -.globl rt_hw_context_switch_to -rt_hw_context_switch_to: - ldr sp, [r0] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - ldmfd sp!, {r4} @ pop new task cpsr - msr cpsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc} @ pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - */ -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -.globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - ldr r2, =rt_thread_switch_interrupt_flag - ldr r3, [r2] - cmp r3, #1 - beq _reswitch - mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 - str r3, [r2] - ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread - str r0, [r2] -_reswitch: - ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread - str r1, [r2] - mov pc, lr diff --git a/rt-thread/libcpu/arm/lpc24xx/context_rvds.S b/rt-thread/libcpu/arm/lpc24xx/context_rvds.S deleted file mode 100644 index 9666127..0000000 --- a/rt-thread/libcpu/arm/lpc24xx/context_rvds.S +++ /dev/null @@ -1,107 +0,0 @@ -;/* -; * Copyright (c) 2006-2022, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2009-01-20 Bernard first version -; * 2011-07-22 Bernard added thumb mode porting -; */ - -NOINT EQU 0xc0 ; disable interrupt in psr - - AREA |.text|, CODE, READONLY, ALIGN=2 - ARM - REQUIRE8 - PRESERVE8 - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ -rt_hw_interrupt_disable PROC - EXPORT rt_hw_interrupt_disable - MRS r0, cpsr - ORR r1, r0, #NOINT - MSR cpsr_c, r1 - BX lr - ENDP - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ -rt_hw_interrupt_enable PROC - EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0 - BX lr - ENDP - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ -rt_hw_context_switch PROC - EXPORT rt_hw_context_switch - STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC) - STMFD sp!, {r0-r12, lr} ; push lr & register file - - MRS r4, cpsr - TST lr, #0x01 - BEQ _ARM_MODE - ORR r4, r4, #0x20 ; it's thumb code - -_ARM_MODE - STMFD sp!, {r4} ; push cpsr - - STR sp, [r0] ; store sp in preempted tasks TCB - LDR sp, [r1] ; get new task stack pointer - - LDMFD sp!, {r4} ; pop new task cpsr to spsr - MSR spsr_cxsf, r4 - BIC r4, r4, #0x20 ; must be ARM mode - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr - ENDP - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; */ -rt_hw_context_switch_to PROC - EXPORT rt_hw_context_switch_to - LDR sp, [r0] ; get new task stack pointer - - LDMFD sp!, {r4} ; pop new task cpsr to spsr - MSR spsr_cxsf, r4 - BIC r4, r4, #0x20 ; must be ARM mode - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr - ENDP - -;/* -; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); -; */ - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -rt_hw_context_switch_interrupt PROC - EXPORT rt_hw_context_switch_interrupt - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1 - STR r3, [r2] - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - BX lr - ENDP - - END diff --git a/rt-thread/libcpu/arm/lpc24xx/cpu.c b/rt-thread/libcpu/arm/lpc24xx/cpu.c deleted file mode 100644 index d9c7402..0000000 --- a/rt-thread/libcpu/arm/lpc24xx/cpu.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2008-12-11 XuXinming first version - */ - -#include -#include "LPC24xx.h" - -/** - * @addtogroup LPC2478 - */ -/*@{*/ - -/** - * this function will reset CPU - * - */ -RT_WEAK void rt_hw_cpu_reset() -{ -} - -/** - * this function will shutdown CPU - * - */ -RT_WEAK void rt_hw_cpu_shutdown() -{ - rt_kprintf("shutdown...\n"); - - while (1); -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/lpc24xx/interrupt.c b/rt-thread/libcpu/arm/lpc24xx/interrupt.c deleted file mode 100644 index 87bb86b..0000000 --- a/rt-thread/libcpu/arm/lpc24xx/interrupt.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2008-12-11 XuXinming first version - * 2013-03-29 aozima Modify the interrupt interface implementations. - */ - -#include -#include -#include "LPC24xx.h" - -#define MAX_HANDLERS 32 - -/* exception and interrupt handler table */ -struct rt_irq_desc irq_desc[MAX_HANDLERS]; - -extern rt_uint32_t rt_interrupt_nest; - -/* exception and interrupt handler table */ -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -/** - * @addtogroup LPC2478 - */ -/*@{*/ -void rt_hw_interrupt_handler(int vector, void *param) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -void rt_hw_interrupt_init(void) -{ - register int i; - - rt_uint32_t *vect_addr, *vect_cntl; - - /* initialize VIC*/ - VICIntEnClr = 0xffffffff; - VICVectAddr = 0; - VICIntSelect = 0; - - /* init exceptions table */ - rt_memset(irq_desc, 0x00, sizeof(irq_desc)); - for(i=0; i < MAX_HANDLERS; i++) - { - irq_desc[i].handler = rt_hw_interrupt_handler; - - vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + i*4); - vect_cntl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + i*4); - *vect_addr = (rt_uint32_t)&irq_desc[i]; - *vect_cntl = 0xF; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -void rt_hw_interrupt_mask(int vector) -{ - VICIntEnClr = (1 << vector); -} - -void rt_hw_interrupt_umask(int vector) -{ - VICIntEnable = (1 << vector); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param handler the interrupt service routine to be installed - * @param param the parameter for interrupt service routine - * @name unused. - * - * @return the old handler - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if(vector >= 0 && vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = handler; - irq_desc[vector].param = param; - } - } - - return old_handler; -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/lpc24xx/stack.c b/rt-thread/libcpu/arm/lpc24xx/stack.c deleted file mode 100644 index a7bce75..0000000 --- a/rt-thread/libcpu/arm/lpc24xx/stack.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2008-12-11 XuXinming first version - */ -#include -#include "LPC24xx.h" - -/** - * @addtogroup LPC2478 - */ -/*@{*/ - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - - stack_addr += sizeof(rt_uint32_t); - stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); - stk = (rt_uint32_t *)stack_addr; - - *(--stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0xdeadbeef; /* r12 */ - *(--stk) = 0xdeadbeef; /* r11 */ - *(--stk) = 0xdeadbeef; /* r10 */ - *(--stk) = 0xdeadbeef; /* r9 */ - *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = 0xdeadbeef; /* r4 */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = 0xdeadbeef; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/lpc24xx/start_gcc.S b/rt-thread/libcpu/arm/lpc24xx/start_gcc.S deleted file mode 100644 index 8e63ffa..0000000 --- a/rt-thread/libcpu/arm/lpc24xx/start_gcc.S +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2008-12-11 XuXinming first version - * 2011-03-17 Bernard update to 0.4.x - */ - -#define WDMOD (0xE0000000 + 0x00) -#define VICIntEnClr (0xFFFFF000 + 0x014) -#define VICVectAddr (0xFFFFF000 + 0xF00) -#define VICIntSelect (0xFFFFF000 + 0x00C) -#define PLLCFG (0xE01FC000 + 0x084) -#define PLLCON (0xE01FC000 + 0x080) -#define PLLFEED (0xE01FC000 + 0x08C) -#define PLLSTAT (0xE01FC000 + 0x088) -#define CCLKCFG (0xE01FC000 + 0x104) -#define MEMMAP (0xE01FC000 + 0x040) -#define SCS (0xE01FC000 + 0x1A0) -#define CLKSRCSEL (0xE01FC000 + 0x10C) -#define MAMCR (0xE01FC000 + 0x000) -#define MAMTIM (0xE01FC000 + 0x004) - -/* stack memory */ -.section .bss.noinit -.equ IRQ_STACK_SIZE, 0x00000200 -.equ FIQ_STACK_SIZE, 0x00000100 -.equ UDF_STACK_SIZE, 0x00000004 -.equ ABT_STACK_SIZE, 0x00000004 -.equ SVC_STACK_SIZE, 0x00000200 - -.space IRQ_STACK_SIZE -IRQ_STACK: - -.space FIQ_STACK_SIZE -FIQ_STACK: - -.space UDF_STACK_SIZE -UDF_STACK: - -.space ABT_STACK_SIZE -ABT_STACK: - -.space SVC_STACK_SIZE -SVC_STACK: - -.section .init, "ax" -.code 32 -.globl _start -_start: - b reset - ldr pc, _vector_undef - ldr pc, _vector_swi - ldr pc, _vector_pabt - ldr pc, _vector_dabt - ldr pc, _vector_resv - ldr pc, _vector_irq - ldr pc, _vector_fiq - -_vector_undef: .word vector_undef -_vector_swi: .word vector_swi -_vector_pabt: .word vector_pabt -_vector_dabt: .word vector_dabt -_vector_resv: .word vector_resv -_vector_irq: .word vector_irq -_vector_fiq: .word vector_fiq - -.balignl 16,0xdeadbeef - -/* - * rtthread kernel start and end - * which are defined in linker script - */ -.globl _rtthread_start -_rtthread_start: - .word _start - -.globl _rtthread_end -_rtthread_end: - .word _end - -/* - * rtthread bss start and end which are defined in linker script - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word __bss_end - -.text -.code 32 - -/* the system entry */ -reset: - /* enter svc mode */ - msr cpsr_c, #SVCMODE|NOINT - - /*watch dog disable */ - ldr r0,=WDMOD - ldr r1,=0x0 - str r1,[r0] - - /* all interrupt disable */ - ldr r0,=VICIntEnClr - ldr r1,=0xffffffff - str r1,[r0] - - ldr r1, =VICVectAddr - ldr r0, =0x00 - str r0, [r1] - - ldr r1, =VICIntSelect - ldr r0, =0x00 - str r0, [r1] - - /* setup stack */ - bl stack_setup - - /* copy .data to SRAM */ - ldr r1, =_sidata /* .data start in image */ - ldr r2, =_edata /* .data end in image */ - ldr r3, =_sdata /* sram data start */ -data_loop: - ldr r0, [r1, #0] - str r0, [r3] - - add r1, r1, #4 - add r3, r3, #4 - - cmp r3, r2 /* check if data to clear */ - blo data_loop /* loop until done */ - - /* clear .bss */ - mov r0,#0 /* get a zero */ - ldr r1,=__bss_start /* bss start */ - ldr r2,=__bss_end /* bss end */ - -bss_loop: - cmp r1,r2 /* check if data to clear */ - strlo r0,[r1],#4 /* clear 4 bytes */ - blo bss_loop /* loop until done */ - - /* call C++ constructors of global objects */ - ldr r0, =__ctors_start__ - ldr r1, =__ctors_end__ - -ctor_loop: - cmp r0, r1 - beq ctor_end - ldr r2, [r0], #4 - stmfd sp!, {r0-r1} - mov lr, pc - bx r2 - ldmfd sp!, {r0-r1} - b ctor_loop -ctor_end: - - /* start RT-Thread Kernel */ - ldr pc, _rtthread_startup - -_rtthread_startup: - .word rtthread_startup - - .equ USERMODE, 0x10 - .equ FIQMODE, 0x11 - .equ IRQMODE, 0x12 - .equ SVCMODE, 0x13 - .equ ABORTMODE, 0x17 - .equ UNDEFMODE, 0x1b - .equ MODEMASK, 0x1f - .equ NOINT, 0xc0 - -/* exception handlers */ -vector_undef: bl rt_hw_trap_udef -vector_swi: bl rt_hw_trap_swi -vector_pabt: bl rt_hw_trap_pabt -vector_dabt: bl rt_hw_trap_dabt -vector_resv: bl rt_hw_trap_resv - -.globl rt_interrupt_enter -.globl rt_interrupt_leave -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -vector_irq: - stmfd sp!, {r0-r12,lr} - bl rt_interrupt_enter - bl rt_hw_trap_irq - bl rt_interrupt_leave - - /* if rt_thread_switch_interrupt_flag set, - * jump to _interrupt_thread_switch and don't return - */ - ldr r0, =rt_thread_switch_interrupt_flag - ldr r1, [r0] - cmp r1, #1 - beq _interrupt_thread_switch - - ldmfd sp!, {r0-r12,lr} - subs pc, lr, #4 - - .align 5 -vector_fiq: - stmfd sp!,{r0-r7,lr} - bl rt_hw_trap_fiq - ldmfd sp!,{r0-r7,lr} - subs pc,lr,#4 - -_interrupt_thread_switch: - mov r1, #0 /* clear rt_thread_switch_interrupt_flag */ - str r1, [r0] - - ldmfd sp!, {r0-r12,lr} /* reload saved registers */ - stmfd sp!, {r0-r3} /* save r0-r3 */ - mov r1, sp - add sp, sp, #16 /* restore sp */ - sub r2, lr, #4 /* save old task's pc to r2 */ - - mrs r3, spsr /* disable interrupt */ - orr r0, r3, #NOINT - msr spsr_c, r0 - - ldr r0, =.+8 /* switch to interrupted task's stack */ - movs pc, r0 - - stmfd sp!, {r2} /* push old task's pc */ - stmfd sp!, {r4-r12,lr} /* push old task's lr,r12-r4 */ - mov r4, r1 /* Special optimised code below */ - mov r5, r3 - ldmfd r4!, {r0-r3} - stmfd sp!, {r0-r3} /* push old task's r3-r0 */ - stmfd sp!, {r5} /* push old task's psr */ - mrs r4, spsr - stmfd sp!, {r4} /* push old task's spsr */ - - ldr r4, =rt_interrupt_from_thread - ldr r5, [r4] - str sp, [r5] /* store sp in preempted tasks's TCB */ - - ldr r6, =rt_interrupt_to_thread - ldr r6, [r6] - ldr sp, [r6] /* get new task's stack pointer */ - - ldmfd sp!, {r4} /* pop new task's spsr */ - msr SPSR_cxsf, r4 - ldmfd sp!, {r4} /* pop new task's psr */ - msr CPSR_cxsf, r4 - - ldmfd sp!, {r0-r12,lr,pc} /* pop new task's r0-r12,lr & pc */ - -stack_setup: - mrs r0, cpsr - bic r0, r0, #MODEMASK - orr r1, r0, #UNDEFMODE|NOINT - msr cpsr_cxsf, r1 /* undef mode */ - ldr sp, =UDF_STACK - - orr r1,r0,#ABORTMODE|NOINT - msr cpsr_cxsf,r1 /* abort mode */ - ldr sp, =ABT_STACK - - orr r1,r0,#IRQMODE|NOINT - msr cpsr_cxsf,r1 /* IRQ mode */ - ldr sp, =IRQ_STACK - - orr r1,r0,#FIQMODE|NOINT - msr cpsr_cxsf,r1 /* FIQ mode */ - ldr sp, =FIQ_STACK - - bic r0,r0,#MODEMASK - orr r1,r0,#SVCMODE|NOINT - msr cpsr_cxsf,r1 /* SVC mode */ - ldr sp, =SVC_STACK - - /* USER mode is not initialized. */ - mov pc,lr /* The LR register may be not valid for the mode changes.*/ diff --git a/rt-thread/libcpu/arm/lpc24xx/start_rvds.S b/rt-thread/libcpu/arm/lpc24xx/start_rvds.S deleted file mode 100644 index 6357cfc..0000000 --- a/rt-thread/libcpu/arm/lpc24xx/start_rvds.S +++ /dev/null @@ -1,1641 +0,0 @@ -;/* -; * Copyright (c) 2006-2022, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; */ -; -;/*****************************************************************************/ -;/* LPC2400.S: Startup file for Philips LPC2400 device series */ -;/*****************************************************************************/ -;/* <<< Use Configuration Wizard in Context Menu >>> */ -;/*****************************************************************************/ -;/* This file is part of the uVision/ARM development tools. */ -;/* Copyright (c) 2007-2008 Keil - An ARM Company. All rights reserved. */ -;/* This software may only be used under the terms of a valid, current, */ -;/* end user licence from KEIL for a compatible version of KEIL software */ -;/* development tools. Nothing else gives you the right to use this software. */ -;/*****************************************************************************/ - -;/* -; * The LPC2400.S code is executed after CPU Reset. This file may be -; * translated with the following SET symbols. In uVision these SET -; * symbols are entered under Options - ASM - Define. -; * -; * NO_CLOCK_SETUP: when set the startup code will not initialize Clock -; * (used mostly when clock is already initialized from script .ini -; * file). -; * -; * NO_EMC_SETUP: when set the startup code will not initialize -; * External Bus Controller. -; * -; * RAM_INTVEC: when set the startup code copies exception vectors -; * from on-chip Flash to on-chip RAM. -; * -; * REMAP: when set the startup code initializes the register MEMMAP -; * which overwrites the settings of the CPU configuration pins. The -; * startup and interrupt vectors are remapped from: -; * 0x00000000 default setting (not remapped) -; * 0x40000000 when RAM_MODE is used -; * 0x80000000 when EXTMEM_MODE is used -; * -; * EXTMEM_MODE: when set the device is configured for code execution -; * from external memory starting at address 0x80000000. -; * -; * RAM_MODE: when set the device is configured for code execution -; * from on-chip RAM starting at address 0x40000000. -; */ - - -; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled - -;----------------------- Memory Definitions ------------------------------------ - -; Internal Memory Base Addresses -FLASH_BASE EQU 0x00000000 -RAM_BASE EQU 0x40000000 -EXTMEM_BASE EQU 0x80000000 - -; External Memory Base Addresses -STA_MEM0_BASE EQU 0x80000000 -STA_MEM1_BASE EQU 0x81000000 -STA_MEM2_BASE EQU 0x82000000 -STA_MEM3_BASE EQU 0x83000000 -DYN_MEM0_BASE EQU 0xA0000000 -DYN_MEM1_BASE EQU 0xB0000000 -DYN_MEM2_BASE EQU 0xC0000000 -DYN_MEM3_BASE EQU 0xD0000000 - - -;----------------------- Stack and Heap Definitions ---------------------------- - -;// Stack Configuration (Stack Sizes in Bytes) -;// Undefined Mode <0x0-0xFFFFFFFF:8> -;// Supervisor Mode <0x0-0xFFFFFFFF:8> -;// Abort Mode <0x0-0xFFFFFFFF:8> -;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> -;// Interrupt Mode <0x0-0xFFFFFFFF:8> -;// User/System Mode <0x0-0xFFFFFFFF:8> -;// - -UND_Stack_Size EQU 0x00000000 -SVC_Stack_Size EQU 0x00000100 -ABT_Stack_Size EQU 0x00000000 -FIQ_Stack_Size EQU 0x00000000 -IRQ_Stack_Size EQU 0x00000100 -USR_Stack_Size EQU 0x00000100 - -ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - -Stack_Mem SPACE USR_Stack_Size -__initial_sp SPACE ISR_Stack_Size - -Stack_Top - - -;// Heap Configuration -;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> -;// - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - -;----------------------- Clock Definitions ------------------------------------- - -; System Control Block (SCB) Module Definitions -SCB_BASE EQU 0xE01FC000 ; SCB Base Address -PLLCON_OFS EQU 0x80 ; PLL Control Offset -PLLCFG_OFS EQU 0x84 ; PLL Configuration Offset -PLLSTAT_OFS EQU 0x88 ; PLL Status Offset -PLLFEED_OFS EQU 0x8C ; PLL Feed Offset -CCLKCFG_OFS EQU 0x104 ; CPU Clock Divider Reg Offset -USBCLKCFG_OFS EQU 0x108 ; USB Clock Divider Reg Offset -CLKSRCSEL_OFS EQU 0x10C ; Clock Source Sel Reg Offset -SCS_OFS EQU 0x1A0 ; Sys Control and Status Reg Offset -PCLKSEL0_OFS EQU 0x1A8 ; Periph Clock Sel Reg 0 Offset -PCLKSEL1_OFS EQU 0x1AC ; Periph Clock Sel Reg 0 Offset - -PCON_OFS EQU 0x0C0 ; Power Mode Control Reg Offset -PCONP_OFS EQU 0x0C4 ; Power Control for Periphs Reg Offset - -; Constants -OSCRANGE EQU (1<<4) ; Oscillator Range Select -OSCEN EQU (1<<5) ; Main oscillator Enable -OSCSTAT EQU (1<<6) ; Main Oscillator Status -PLLCON_PLLE EQU (1<<0) ; PLL Enable -PLLCON_PLLC EQU (1<<1) ; PLL Connect -PLLSTAT_M EQU (0x7FFF<<0) ; PLL M Value -PLLSTAT_N EQU (0xFF<<16) ; PLL N Value -PLLSTAT_PLOCK EQU (1<<26) ; PLL Lock Status - -;// Clock Setup -;// System Controls and Status Register (SYS) -;// OSCRANGE: Main Oscillator Range Select -;// <0=> 1 MHz to 20 MHz -;// <1=> 15 MHz to 24 MHz -;// OSCEN: Main Oscillator Enable -;// -;// -;// -;// PLL Clock Source Select Register (CLKSRCSEL) -;// CLKSRC: PLL Clock Source Selection -;// <0=> Internal RC oscillator -;// <1=> Main oscillator -;// <2=> RTC oscillator -;// -;// -;// PLL Configuration Register (PLLCFG) -;// PLL_clk = (2* M * PLL_clk_src) / N -;// MSEL: PLL Multiplier Selection -;// <1-32768><#-1> -;// M Value -;// NSEL: PLL Divider Selection -;// <1-256><#-1> -;// N Value -;// -;// -;// CPU Clock Configuration Register (CCLKCFG) -;// CCLKSEL: Divide Value for CPU Clock from PLL -;// <1-256><#-1> -;// -;// -;// USB Clock Configuration Register (USBCLKCFG) -;// USBSEL: Divide Value for USB Clock from PLL -;// <1-16><#-1> -;// -;// -;// Peripheral Clock Selection Register 0 (PCLKSEL0) -;// PCLK_WDT: Peripheral Clock Selection for WDT -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_TIMER0: Peripheral Clock Selection for TIMER0 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_TIMER1: Peripheral Clock Selection for TIMER1 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_UART0: Peripheral Clock Selection for UART0 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_UART1: Peripheral Clock Selection for UART1 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_PWM0: Peripheral Clock Selection for PWM0 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_PWM1: Peripheral Clock Selection for PWM1 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_I2C0: Peripheral Clock Selection for I2C0 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_SPI: Peripheral Clock Selection for SPI -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_RTC: Peripheral Clock Selection for RTC -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_SSP1: Peripheral Clock Selection for SSP1 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_DAC: Peripheral Clock Selection for DAC -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_ADC: Peripheral Clock Selection for ADC -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_CAN1: Peripheral Clock Selection for CAN1 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 6 -;// PCLK_CAN2: Peripheral Clock Selection for CAN2 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 6 -;// PCLK_ACF: Peripheral Clock Selection for ACF -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 6 -;// -;// -;// Peripheral Clock Selection Register 1 (PCLKSEL1) -;// PCLK_BAT_RAM: Peripheral Clock Selection for the Battery Supported RAM -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_GPIO: Peripheral Clock Selection for GPIOs -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_PCB: Peripheral Clock Selection for Pin Connect Block -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_I2C1: Peripheral Clock Selection for I2C1 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_SSP0: Peripheral Clock Selection for SSP0 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_TIMER2: Peripheral Clock Selection for TIMER2 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_TIMER3: Peripheral Clock Selection for TIMER3 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_UART2: Peripheral Clock Selection for UART2 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_UART3: Peripheral Clock Selection for UART3 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_I2C2: Peripheral Clock Selection for I2C2 -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_I2S: Peripheral Clock Selection for I2S -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_MCI: Peripheral Clock Selection for MCI -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// PCLK_SYSCON: Peripheral Clock Selection for System Control Block -;// <0=> Pclk = Cclk / 4 -;// <1=> Pclk = Cclk -;// <2=> Pclk = Cclk / 2 -;// <3=> Pclk = Cclk / 8 -;// -;// -CLOCK_SETUP EQU 1 -SCS_Val EQU 0x00000020 -CLKSRCSEL_Val EQU 0x00000001 -PLLCFG_Val EQU 0x0000000B -CCLKCFG_Val EQU 0x00000004 -USBCLKCFG_Val EQU 0x00000005 -PCLKSEL0_Val EQU 0x00000000 -PCLKSEL1_Val EQU 0x00000000 - - -;----------------------- Memory Accelerator Module (MAM) Definitions ----------- - -MAM_BASE EQU 0xE01FC000 ; MAM Base Address -MAMCR_OFS EQU 0x00 ; MAM Control Offset -MAMTIM_OFS EQU 0x04 ; MAM Timing Offset - -;// MAM Setup -;// MAM Control -;// <0=> Disabled -;// <1=> Partially Enabled -;// <2=> Fully Enabled -;// Mode -;// MAM Timing -;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3 -;// <4=> 4 <5=> 5 <6=> 6 <7=> 7 -;// Fetch Cycles -;// -MAM_SETUP EQU 1 -MAMCR_Val EQU 0x00000002 -MAMTIM_Val EQU 0x00000004 - - -;----------------------- Pin Connect Block Definitions ------------------------- - -PCB_BASE EQU 0xE002C000 ; PCB Base Address -PINSEL0_OFS EQU 0x00 ; PINSEL0 Address Offset -PINSEL1_OFS EQU 0x04 ; PINSEL1 Address Offset -PINSEL2_OFS EQU 0x08 ; PINSEL2 Address Offset -PINSEL3_OFS EQU 0x0C ; PINSEL3 Address Offset -PINSEL4_OFS EQU 0x10 ; PINSEL4 Address Offset -PINSEL5_OFS EQU 0x14 ; PINSEL5 Address Offset -PINSEL6_OFS EQU 0x18 ; PINSEL6 Address Offset -PINSEL7_OFS EQU 0x1C ; PINSEL7 Address Offset -PINSEL8_OFS EQU 0x20 ; PINSEL8 Address Offset -PINSEL9_OFS EQU 0x24 ; PINSEL9 Address Offset -PINSEL10_OFS EQU 0x28 ; PINSEL10 Address Offset - - -;----------------------- External Memory Controller (EMC) Definitons ----------- - -EMC_BASE EQU 0xFFE08000 ; EMC Base Address - -EMC_CTRL_OFS EQU 0x000 -EMC_STAT_OFS EQU 0x004 -EMC_CONFIG_OFS EQU 0x008 -EMC_DYN_CTRL_OFS EQU 0x020 -EMC_DYN_RFSH_OFS EQU 0x024 -EMC_DYN_RD_CFG_OFS EQU 0x028 -EMC_DYN_RP_OFS EQU 0x030 -EMC_DYN_RAS_OFS EQU 0x034 -EMC_DYN_SREX_OFS EQU 0x038 -EMC_DYN_APR_OFS EQU 0x03C -EMC_DYN_DAL_OFS EQU 0x040 -EMC_DYN_WR_OFS EQU 0x044 -EMC_DYN_RC_OFS EQU 0x048 -EMC_DYN_RFC_OFS EQU 0x04C -EMC_DYN_XSR_OFS EQU 0x050 -EMC_DYN_RRD_OFS EQU 0x054 -EMC_DYN_MRD_OFS EQU 0x058 -EMC_DYN_CFG0_OFS EQU 0x100 -EMC_DYN_RASCAS0_OFS EQU 0x104 -EMC_DYN_CFG1_OFS EQU 0x140 -EMC_DYN_RASCAS1_OFS EQU 0x144 -EMC_DYN_CFG2_OFS EQU 0x160 -EMC_DYN_RASCAS2_OFS EQU 0x164 -EMC_DYN_CFG3_OFS EQU 0x180 -EMC_DYN_RASCAS3_OFS EQU 0x184 -EMC_STA_CFG0_OFS EQU 0x200 -EMC_STA_WWEN0_OFS EQU 0x204 -EMC_STA_WOEN0_OFS EQU 0x208 -EMC_STA_WRD0_OFS EQU 0x20C -EMC_STA_WPAGE0_OFS EQU 0x210 -EMC_STA_WWR0_OFS EQU 0x214 -EMC_STA_WTURN0_OFS EQU 0x218 -EMC_STA_CFG1_OFS EQU 0x220 -EMC_STA_WWEN1_OFS EQU 0x224 -EMC_STA_WOEN1_OFS EQU 0x228 -EMC_STA_WRD1_OFS EQU 0x22C -EMC_STA_WPAGE1_OFS EQU 0x230 -EMC_STA_WWR1_OFS EQU 0x234 -EMC_STA_WTURN1_OFS EQU 0x238 -EMC_STA_CFG2_OFS EQU 0x240 -EMC_STA_WWEN2_OFS EQU 0x244 -EMC_STA_WOEN2_OFS EQU 0x248 -EMC_STA_WRD2_OFS EQU 0x24C -EMC_STA_WPAGE2_OFS EQU 0x250 -EMC_STA_WWR2_OFS EQU 0x254 -EMC_STA_WTURN2_OFS EQU 0x258 -EMC_STA_CFG3_OFS EQU 0x260 -EMC_STA_WWEN3_OFS EQU 0x264 -EMC_STA_WOEN3_OFS EQU 0x268 -EMC_STA_WRD3_OFS EQU 0x26C -EMC_STA_WPAGE3_OFS EQU 0x270 -EMC_STA_WWR3_OFS EQU 0x274 -EMC_STA_WTURN3_OFS EQU 0x278 -EMC_STA_EXT_W_OFS EQU 0x880 - -; Constants -NORMAL_CMD EQU (0x0 << 7) ; NORMAL Command -MODE_CMD EQU (0x1 << 7) ; MODE Command -PALL_CMD EQU (0x2 << 7) ; Precharge All Command -NOP_CMD EQU (0x3 << 7) ; NOP Command - -BUFEN_Const EQU (1 << 19) ; Buffer enable bit -EMC_PCONP_Const EQU (1 << 11) ; PCONP val to enable power for EMC - -; External Memory Pins definitions -; pin functions for SDRAM, NOR and NAND flash interfacing -EMC_PINSEL5_Val EQU 0x05010115 ; !CAS, !RAS, CLKOUT0, !DYCS0, DQMOUT0, DQMOUT1 -EMC_PINSEL6_Val EQU 0x55555555 ; D0 .. D15 -EMC_PINSEL8_Val EQU 0x55555555 ; A0 .. A15 -EMC_PINSEL9_Val EQU 0x50055555; ; A16 .. A23, !OE, !WE, !CS0, !CS1 - -;// External Memory Controller Setup (EMC) --------------------------------- -;// External Memory Controller Setup (EMC) -EMC_SETUP EQU 0 - -;// EMC Control Register (EMCControl) -;// Controls operation of the memory controller -;// L: Low-power mode enable -;// M: Address mirror enable -;// E: EMC enable -;// -EMC_CTRL_Val EQU 0x00000001 - -;// EMC Configuration Register (EMCConfig) -;// Configures operation of the memory controller -;// CCLK: CLKOUT ratio -;// <0=> 1:1 -;// <1=> 1:2 -;// Endian mode -;// <0=> Little-endian -;// <1=> Big-endian -;// -EMC_CONFIG_Val EQU 0x00000000 - -;// Dynamic Memory Interface Setup --------------------------------------- -;// Dynamic Memory Interface Setup -EMC_DYNAMIC_SETUP EQU 1 - -;// Dynamic Memory Refresh Timer Register (EMCDynamicRefresh) -;// Configures dynamic memory refresh operation -;// REFRESH: Refresh timer <0x000-0x7FF> -;// 0 = refresh disabled, 0x01-0x7FF: value * 16 CCLKS -;// -EMC_DYN_RFSH_Val EQU 0x0000001C - -;// Dynamic Memory Read Configuration Register (EMCDynamicReadConfig) -;// Configures the dynamic memory read strategy -;// RD: Read data strategy -;// <0=> Clock out delayed strategy -;// <1=> Command delayed strategy -;// <2=> Command delayed strategy plus one clock cycle -;// <3=> Command delayed strategy plus two clock cycles -;// -EMC_DYN_RD_CFG_Val EQU 0x00000001 - -;// Dynamic Memory Timings -;// Dynamic Memory Percentage Command Period Register (EMCDynamictRP) -;// tRP: Precharge command period <1-16> <#-1> -;// The delay is in EMCCLK cycles -;// This value is normally found in SDRAM data sheets as tRP -;// -;// Dynamic Memory Active to Precharge Command Period Register (EMCDynamictRAS) -;// tRAS: Active to precharge command period <1-16> <#-1> -;// The delay is in EMCCLK cycles -;// This value is normally found in SDRAM data sheets as tRAS -;// -;// Dynamic Memory Self-refresh Exit Time Register (EMCDynamictSREX) -;// tSREX: Self-refresh exit time <1-16> <#-1> -;// The delay is in CCLK cycles -;// This value is normally found in SDRAM data sheets as tSREX, -;// for devices without this parameter you use the same value as tXSR -;// -;// Dynamic Memory Last Data Out to Active Time Register (EMCDynamictAPR) -;// tAPR: Last-data-out to active command time <1-16> <#-1> -;// The delay is in CCLK cycles -;// This value is normally found in SDRAM data sheets as tAPR -;// -;// Dynamic Memory Data-in to Active Command Time Register (EMCDynamictDAL) -;// tDAL: Data-in to active command time <1-16> <#-1> -;// The delay is in CCLK cycles -;// This value is normally found in SDRAM data sheets as tDAL or tAPW -;// -;// Dynamic Memory Write Recovery Time Register (EMCDynamictWR) -;// tWR: Write recovery time <1-16> <#-1> -;// The delay is in CCLK cycles -;// This value is normally found in SDRAM data sheets as tWR, tDPL, tRWL, or tRDL -;// -;// Dynamic Memory Active to Active Command Period Register (EMCDynamictRC) -;// tRC: Active to active command period <1-32> <#-1> -;// The delay is in CCLK cycles -;// This value is normally found in SDRAM data sheets as tRC -;// -;// Dynamic Memory Auto-refresh Period Register (EMCDynamictRFC) -;// tRFC: Auto-refresh period and auto-refresh to active command period <1-32> <#-1> -;// The delay is in CCLK cycles -;// This value is normally found in SDRAM data sheets as tRFC or tRC -;// -;// Dynamic Memory Exit Self-refresh Register (EMCDynamictXSR) -;// tXSR: Exit self-refresh to active command time <1-32> <#-1> -;// The delay is in CCLK cycles -;// This value is normally found in SDRAM data sheets as tXSR -;// -;// Dynamic Memory Active Bank A to Active Bank B Time Register (EMCDynamicRRD) -;// tRRD: Active bank A to active bank B latency <1-16> <#-1> -;// The delay is in CCLK cycles -;// This value is normally found in SDRAM data sheets as tRRD -;// -;// Dynamic Memory Load Mode Register to Active Command Time (EMCDynamictMRD) -;// tMRD: Load mode register to active command time <1-16> <#-1> -;// The delay is in CCLK cycles -;// This value is normally found in SDRAM data sheets as tMRD or tRSA -;// -;// -EMC_DYN_RP_Val EQU 0x00000002 -EMC_DYN_RAS_Val EQU 0x00000003 -EMC_DYN_SREX_Val EQU 0x00000007 -EMC_DYN_APR_Val EQU 0x00000002 -EMC_DYN_DAL_Val EQU 0x00000005 -EMC_DYN_WR_Val EQU 0x00000001 -EMC_DYN_RC_Val EQU 0x00000005 -EMC_DYN_RFC_Val EQU 0x00000005 -EMC_DYN_XSR_Val EQU 0x00000007 -EMC_DYN_RRD_Val EQU 0x00000001 -EMC_DYN_MRD_Val EQU 0x00000002 - -;// Configure External Bus Behaviour for Dynamic CS0 Area -EMC_DYNCS0_SETUP EQU 1 - -;// Dynamic Memory Configuration Register (EMCDynamicConfig0) -;// Defines the configuration information for the dynamic memory CS0 -;// P: Write protect -;// B: Buffer enable -;// AM 14: External bus data width -;// <0=> 16 bit -;// <1=> 32 bit -;// AM 12: External bus memory type -;// <0=> High-performance -;// <1=> Low-power SDRAM -;// AM 11..7: External bus address mapping (Row, Bank, Column) -;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 -;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 -;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 -;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 -;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 -;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 -;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 -;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 -;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 -;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 -;// MD: Memory device -;// <0=> SDRAM -;// <1=> Low-power SDRAM -;// <2=> Micron SyncFlash -;// -EMC_DYN_CFG0_Val EQU 0x00080680 - -;// Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS0) -;// Controls the RAS and CAS latencies for the dynamic memory CS0 -;// CAS: CAS latency -;// <1=> One CCLK cycle -;// <2=> Two CCLK cycles -;// <3=> Three CCLK cycles -;// RAS: RAS latency (active to read/write delay) -;// <1=> One CCLK cycle -;// <2=> Two CCLK cycles -;// <3=> Three CCLK cycles -;// -EMC_DYN_RASCAS0_Val EQU 0x00000303 - -;// End of Dynamic Setup for CS0 Area - - -;// Configure External Bus Behaviour for Dynamic CS1 Area -EMC_DYNCS1_SETUP EQU 0 - -;// Dynamic Memory Configuration Register (EMCDynamicConfig1) -;// Defines the configuration information for the dynamic memory CS1 -;// P: Write protect -;// B: Buffer enable -;// AM 14: External bus data width -;// <0=> 16 bit -;// <1=> 32 bit -;// AM 12: External bus memory type -;// <0=> High-performance -;// <1=> Low-power SDRAM -;// AM 11..7: External bus address mapping (Row, Bank, Column) -;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 -;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 -;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 -;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 -;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 -;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 -;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 -;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 -;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 -;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 -;// MD: Memory device -;// <0=> SDRAM -;// <1=> Low-power SDRAM -;// <2=> Micron SyncFlash -;// -EMC_DYN_CFG1_Val EQU 0x00000000 - -;// Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS1) -;// Controls the RAS and CAS latencies for the dynamic memory CS1 -;// CAS: CAS latency -;// <1=> One CCLK cycle -;// <2=> Two CCLK cycles -;// <3=> Three CCLK cycles -;// RAS: RAS latency (active to read/write delay) -;// <1=> One CCLK cycle -;// <2=> Two CCLK cycles -;// <3=> Three CCLK cycles -;// -EMC_DYN_RASCAS1_Val EQU 0x00000303 - -;// End of Dynamic Setup for CS1 Area - -;// Configure External Bus Behaviour for Dynamic CS2 Area -EMC_DYNCS2_SETUP EQU 0 - -;// Dynamic Memory Configuration Register (EMCDynamicConfig2) -;// Defines the configuration information for the dynamic memory CS2 -;// P: Write protect -;// B: Buffer enable -;// AM 14: External bus data width -;// <0=> 16 bit -;// <1=> 32 bit -;// AM 12: External bus memory type -;// <0=> High-performance -;// <1=> Low-power SDRAM -;// AM 11..7: External bus address mapping (Row, Bank, Column) -;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 -;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 -;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 -;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 -;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 -;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 -;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 -;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 -;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 -;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 -;// MD: Memory device -;// <0=> SDRAM -;// <1=> Low-power SDRAM -;// <2=> Micron SyncFlash -;// -EMC_DYN_CFG2_Val EQU 0x00000000 - -;// Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS2) -;// Controls the RAS and CAS latencies for the dynamic memory CS2 -;// CAS: CAS latency -;// <1=> One CCLK cycle -;// <2=> Two CCLK cycles -;// <3=> Three CCLK cycles -;// RAS: RAS latency (active to read/write delay) -;// <1=> One CCLK cycle -;// <2=> Two CCLK cycles -;// <3=> Three CCLK cycles -;// -EMC_DYN_RASCAS2_Val EQU 0x00000303 - -;// End of Dynamic Setup for CS2 Area - -;// Configure External Bus Behaviour for Dynamic CS3 Area -EMC_DYNCS3_SETUP EQU 0 - -;// Dynamic Memory Configuration Register (EMCDynamicConfig3) -;// Defines the configuration information for the dynamic memory CS3 -;// P: Write protect -;// B: Buffer enable -;// AM 14: External bus data width -;// <0=> 16 bit -;// <1=> 32 bit -;// AM 12: External bus memory type -;// <0=> High-performance -;// <1=> Low-power SDRAM -;// AM 11..7: External bus address mapping (Row, Bank, Column) -;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 -;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 -;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 -;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 -;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 -;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 -;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 -;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 -;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 -;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 -;// MD: Memory device -;// <0=> SDRAM -;// <1=> Low-power SDRAM -;// <2=> Micron SyncFlash -;// -EMC_DYN_CFG3_Val EQU 0x00000000 - -;// Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS3) -;// Controls the RAS and CAS latencies for the dynamic memory CS3 -;// CAS: CAS latency -;// <1=> One CCLK cycle -;// <2=> Two CCLK cycles -;// <3=> Three CCLK cycles -;// RAS: RAS latency (active to read/write delay) -;// <1=> One CCLK cycle -;// <2=> Two CCLK cycles -;// <3=> Three CCLK cycles -;// -EMC_DYN_RASCAS3_Val EQU 0x00000303 - -;// End of Dynamic Setup for CS3 Area - -;// End of Dynamic Setup - -;// Static Memory Interface Setup ---------------------------------------- -;// Static Memory Interface Setup -EMC_STATIC_SETUP EQU 1 - -;// Configure External Bus Behaviour for Static CS0 Area --------------- -;// Configure External Bus Behaviour for Static CS0 Area -EMC_STACS0_SETUP EQU 1 - -;// Static Memory Configuration Register (EMCStaticConfig0) -;// Defines the configuration information for the static memory CS0 -;// WP: Write protect -;// B: Buffer enable -;// EW: Extended wait enable -;// PB: Byte lane state -;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW -;// <1=> For reads BLSn are LOW, for writes BLSn are LOW -;// PC: Chip select polarity -;// <0=> Active LOW chip select -;// <1=> Active HIGH chip select -;// PM: Page mode enable -;// MW: Memory width -;// <0=> 8 bit -;// <1=> 16 bit -;// <2=> 32 bit -;// -EMC_STA_CFG0_Val EQU 0x00000081 - -;// Static Memory Write Enable Delay Register (EMCStaticWaitWen0) -;// Selects the delay from CS0 to write enable -;// WAITWEN: Wait write enable <1-16> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WWEN0_Val EQU 0x00000002 - -;// Static Memory Output Enable Delay register (EMCStaticWaitOen0) -;// Selects the delay from CS0 or address change, whichever is later, to output enable -;// WAITOEN: Wait output enable <0-15> -;// The delay is in CCLK cycles -;// -EMC_STA_WOEN0_Val EQU 0x00000002 - -;// Static Memory Read Delay Register (EMCStaticWaitRd0) -;// Selects the delay from CS0 to a read access -;// WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WRD0_Val EQU 0x0000001F - -;// Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0) -;// Selects the delay for asynchronous page mode sequential accesses for CS0 -;// WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WPAGE0_Val EQU 0x0000001F - -;// Static Memory Write Delay Register (EMCStaticWaitWr0) -;// Selects the delay from CS0 to a write access -;// WAITWR: Write wait states <2-33> <#-2> -;// The delay is in CCLK cycles -;// -EMC_STA_WWR0_Val EQU 0x0000001F - -;// Static Memory Turn Round Delay Register (EMCStaticWaitTurn0) -;// Selects the number of bus turnaround cycles for CS0 -;// WAITTURN: Bus turnaround cycles <1-16> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WTURN0_Val EQU 0x0000000F - -;// End of Static Setup for Static CS0 Area - -;// Configure External Bus Behaviour for Static CS1 Area --------------- -;// Configure External Bus Behaviour for Static CS1 Area -EMC_STACS1_SETUP EQU 0 - -;// Static Memory Configuration Register (EMCStaticConfig1) -;// Defines the configuration information for the static memory CS1 -;// WP: Write protect -;// B: Buffer enable -;// EW: Extended wait enable -;// PB: Byte lane state -;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW -;// <1=> For reads BLSn are LOW, for writes BLSn are LOW -;// PC: Chip select polarity -;// <0=> Active LOW chip select -;// <1=> Active HIGH chip select -;// PM: Page mode enable -;// MW: Memory width -;// <0=> 8 bit -;// <1=> 16 bit -;// <2=> 32 bit -;// -EMC_STA_CFG1_Val EQU 0x00000000 - -;// Static Memory Write Enable Delay Register (EMCStaticWaitWen1) -;// Selects the delay from CS1 to write enable -;// WAITWEN: Wait write enable <1-16> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WWEN1_Val EQU 0x00000000 - -;// Static Memory Output Enable Delay register (EMCStaticWaitOen1) -;// Selects the delay from CS1 or address change, whichever is later, to output enable -;// WAITOEN: Wait output enable <0-15> -;// The delay is in CCLK cycles -;// -EMC_STA_WOEN1_Val EQU 0x00000000 - -;// Static Memory Read Delay Register (EMCStaticWaitRd1) -;// Selects the delay from CS1 to a read access -;// WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WRD1_Val EQU 0x0000001F - -;// Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0) -;// Selects the delay for asynchronous page mode sequential accesses for CS1 -;// WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WPAGE1_Val EQU 0x0000001F - -;// Static Memory Write Delay Register (EMCStaticWaitWr1) -;// Selects the delay from CS1 to a write access -;// WAITWR: Write wait states <2-33> <#-2> -;// The delay is in CCLK cycles -;// -EMC_STA_WWR1_Val EQU 0x0000001F - -;// Static Memory Turn Round Delay Register (EMCStaticWaitTurn1) -;// Selects the number of bus turnaround cycles for CS1 -;// WAITTURN: Bus turnaround cycles <1-16> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WTURN1_Val EQU 0x0000000F - -;// End of Static Setup for Static CS1 Area - -;// Configure External Bus Behaviour for Static CS2 Area --------------- -;// Configure External Bus Behaviour for Static CS2 Area -EMC_STACS2_SETUP EQU 0 - -;// Static Memory Configuration Register (EMCStaticConfig2) -;// Defines the configuration information for the static memory CS2 -;// WP: Write protect -;// B: Buffer enable -;// EW: Extended wait enable -;// PB: Byte lane state -;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW -;// <1=> For reads BLSn are LOW, for writes BLSn are LOW -;// PC: Chip select polarity -;// <0=> Active LOW chip select -;// <1=> Active HIGH chip select -;// PM: Page mode enable -;// MW: Memory width -;// <0=> 8 bit -;// <1=> 16 bit -;// <2=> 32 bit -;// -EMC_STA_CFG2_Val EQU 0x00000000 - -;// Static Memory Write Enable Delay Register (EMCStaticWaitWen2) -;// Selects the delay from CS2 to write enable -;// WAITWEN: Wait write enable <1-16> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WWEN2_Val EQU 0x00000000 - -;// Static Memory Output Enable Delay register (EMCStaticWaitOen2) -;// Selects the delay from CS2 or address change, whichever is later, to output enable -;// WAITOEN: Wait output enable <0-15> -;// The delay is in CCLK cycles -;// -EMC_STA_WOEN2_Val EQU 0x00000000 - -;// Static Memory Read Delay Register (EMCStaticWaitRd2) -;// Selects the delay from CS2 to a read access -;// WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WRD2_Val EQU 0x0000001F - -;// Static Memory Page Mode Read Delay Register (EMCStaticWaitPage2) -;// Selects the delay for asynchronous page mode sequential accesses for CS2 -;// WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WPAGE2_Val EQU 0x0000001F - -;// Static Memory Write Delay Register (EMCStaticWaitWr2) -;// Selects the delay from CS2 to a write access -;// WAITWR: Write wait states <2-33> <#-2> -;// The delay is in CCLK cycles -;// -EMC_STA_WWR2_Val EQU 0x0000001F - -;// Static Memory Turn Round Delay Register (EMCStaticWaitTurn2) -;// Selects the number of bus turnaround cycles for CS2 -;// WAITTURN: Bus turnaround cycles <1-16> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WTURN2_Val EQU 0x0000000F - -;// End of Static Setup for Static CS2 Area - -;// Configure External Bus Behaviour for Static CS3 Area --------------- -;// Configure External Bus Behaviour for Static CS3 Area -EMC_STACS3_SETUP EQU 0 - -;// Static Memory Configuration Register (EMCStaticConfig3) -;// Defines the configuration information for the static memory CS3 -;// WP: Write protect -;// B: Buffer enable -;// EW: Extended wait enable -;// PB: Byte lane state -;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW -;// <1=> For reads BLSn are LOW, for writes BLSn are LOW -;// PC: Chip select polarity -;// <0=> Active LOW chip select -;// <1=> Active HIGH chip select -;// PM: Page mode enable -;// MW: Memory width -;// <0=> 8 bit -;// <1=> 16 bit -;// <2=> 32 bit -;// -EMC_STA_CFG3_Val EQU 0x00000000 - -;// Static Memory Write Enable Delay Register (EMCStaticWaitWen3) -;// Selects the delay from CS3 to write enable -;// WAITWEN: Wait write enable <1-16> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WWEN3_Val EQU 0x00000000 - -;// Static Memory Output Enable Delay register (EMCStaticWaitOen3) -;// Selects the delay from CS3 or address change, whichever is later, to output enable -;// WAITOEN: Wait output enable <0-15> -;// The delay is in CCLK cycles -;// -EMC_STA_WOEN3_Val EQU 0x00000000 - -;// Static Memory Read Delay Register (EMCStaticWaitRd3) -;// Selects the delay from CS3 to a read access -;// WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WRD3_Val EQU 0x0000001F - -;// Static Memory Page Mode Read Delay Register (EMCStaticWaitPage3) -;// Selects the delay for asynchronous page mode sequential accesses for CS3 -;// WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WPAGE3_Val EQU 0x0000001F - -;// Static Memory Write Delay Register (EMCStaticWaitWr3) -;// Selects the delay from CS3 to a write access -;// WAITWR: Write wait states <2-33> <#-2> -;// The delay is in CCLK cycles -;// -EMC_STA_WWR3_Val EQU 0x0000001F - -;// Static Memory Turn Round Delay Register (EMCStaticWaitTurn3) -;// Selects the number of bus turnaround cycles for CS3 -;// WAITTURN: Bus turnaround cycles <1-16> <#-1> -;// The delay is in CCLK cycles -;// -EMC_STA_WTURN3_Val EQU 0x0000000F - -;// End of Static Setup for Static CS3 Area - -;// Static Memory Extended Wait Register (EMCStaticExtendedWait) -;// Time long static memory read and write transfers -;// EXTENDEDWAIT: Extended wait time out <0-1023> -;// The delay is in (16 * CCLK) cycles -;// -EMC_STA_EXT_W_Val EQU 0x00000000 - -;// End of Static Setup - -;// End of EMC Setup - - - PRESERVE8 - -; Area Definition and Entry Point -; Startup Code must be linked first at Address at which it expects to run. - - AREA RESET, CODE, READONLY - ARM - - -; Exception Vectors -; Mapped to Address 0. -; Absolute addressing mode must be used. -; Dummy Handlers are implemented as infinite loops which can be modified. - -Vectors LDR PC, Reset_Addr - LDR PC, Undef_Addr - LDR PC, SWI_Addr - LDR PC, PAbt_Addr - LDR PC, DAbt_Addr - NOP ; Reserved Vector - LDR PC, IRQ_Addr - LDR PC, FIQ_Addr - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SWI_Addr DCD SWI_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler - DCD 0 ; Reserved Address -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - - -; Exception Handler - IMPORT rt_hw_trap_udef - IMPORT rt_hw_trap_swi - IMPORT rt_hw_trap_pabt - IMPORT rt_hw_trap_dabt - IMPORT rt_hw_trap_fiq - -; Prepare Fatal Context - MACRO - prepare_fatal - STMFD sp!, {r0-r3} - MOV r1, sp - ADD sp, sp, #16 - SUB r2, lr, #4 - MRS r3, spsr - - ; switch to SVC mode and no interrupt - MSR cpsr_c, #I_Bit :OR: F_Bit :OR: Mode_SVC - - STMFD sp!, {r0} ; old r0 - ; get sp - ADD r0, sp, #4 - STMFD sp!, {r3} ; cpsr - STMFD sp!, {r2} ; pc - STMFD sp!, {lr} ; lr - STMFD sp!, {r0} ; sp - STMFD sp!, {r4-r12} - - MOV r4, r1 - - LDMFD r4!, {r0-r3} - STMFD sp!, {r0-r3} - - MOV r0, sp - MEND - -Undef_Handler - prepare_fatal - BL rt_hw_trap_irq - B . - -SWI_Handler - prepare_fatal - BL rt_hw_trap_swi - B . - -PAbt_Handler - prepare_fatal - BL rt_hw_trap_pabt - B . - -DAbt_Handler - prepare_fatal - BL rt_hw_trap_dabt - B . - -FIQ_Handler - prepare_fatal - BL rt_hw_trap_fiq - B . - -; Reset Handler - - EXPORT Reset_Handler -Reset_Handler - - -; Clock Setup ------------------------------------------------------------------ - - IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0) - LDR R0, =SCB_BASE - MOV R1, #0xAA - MOV R2, #0x55 - -; Configure and Enable PLL - LDR R3, =SCS_Val ; Enable main oscillator - STR R3, [R0, #SCS_OFS] - - IF (SCS_Val:AND:OSCEN) != 0 -OSC_Loop LDR R3, [R0, #SCS_OFS] ; Wait for main osc stabilize - ANDS R3, R3, #OSCSTAT - BEQ OSC_Loop - ENDIF - - LDR R3, =CLKSRCSEL_Val ; Select PLL source clock - STR R3, [R0, #CLKSRCSEL_OFS] - LDR R3, =PLLCFG_Val - STR R3, [R0, #PLLCFG_OFS] - STR R1, [R0, #PLLFEED_OFS] - STR R2, [R0, #PLLFEED_OFS] - MOV R3, #PLLCON_PLLE - STR R3, [R0, #PLLCON_OFS] - STR R1, [R0, #PLLFEED_OFS] - STR R2, [R0, #PLLFEED_OFS] - - IF (CLKSRCSEL_Val:AND:3) != 2 -; Wait until PLL Locked (if source is not RTC oscillator) -PLL_Loop LDR R3, [R0, #PLLSTAT_OFS] - ANDS R3, R3, #PLLSTAT_PLOCK - BEQ PLL_Loop - ELSE -; Wait at least 200 cycles (if source is RTC oscillator) - MOV R3, #(200/4) -PLL_Loop SUBS R3, R3, #1 - BNE PLL_Loop - ENDIF - -M_N_Lock LDR R3, [R0, #PLLSTAT_OFS] - LDR R4, =(PLLSTAT_M:OR:PLLSTAT_N) - AND R3, R3, R4 - LDR R4, =PLLCFG_Val - EORS R3, R3, R4 - BNE M_N_Lock - -; Setup CPU clock divider - MOV R3, #CCLKCFG_Val - STR R3, [R0, #CCLKCFG_OFS] - -; Setup USB clock divider - LDR R3, =USBCLKCFG_Val - STR R3, [R0, #USBCLKCFG_OFS] - -; Setup Peripheral Clock - LDR R3, =PCLKSEL0_Val - STR R3, [R0, #PCLKSEL0_OFS] - LDR R3, =PCLKSEL1_Val - STR R3, [R0, #PCLKSEL1_OFS] - -; Switch to PLL Clock - MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC) - STR R3, [R0, #PLLCON_OFS] - STR R1, [R0, #PLLFEED_OFS] - STR R2, [R0, #PLLFEED_OFS] - ENDIF ; CLOCK_SETUP - - -; Setup Memory Accelerator Module ---------------------------------------------- - - IF MAM_SETUP != 0 - LDR R0, =MAM_BASE - MOV R1, #MAMTIM_Val - STR R1, [R0, #MAMTIM_OFS] - MOV R1, #MAMCR_Val - STR R1, [R0, #MAMCR_OFS] - ENDIF ; MAM_SETUP - - -; Setup External Memory Controller --------------------------------------------- - - IF (:LNOT:(:DEF:NO_EMC_SETUP)):LAND:(EMC_SETUP != 0) - LDR R0, =EMC_BASE - LDR R1, =SCB_BASE - LDR R2, =PCB_BASE - - LDR R4, =EMC_PCONP_Const ; Enable EMC - LDR R3, [R1, #PCONP_OFS] - ORR R4, R4, R3 - STR R4, [R1, #PCONP_OFS] - - LDR R4, =EMC_CTRL_Val - STR R4, [R0, #EMC_CTRL_OFS] - LDR R4, =EMC_CONFIG_Val - STR R4, [R0, #EMC_CONFIG_OFS] - -; Setup pin functions for External Bus functionality - LDR R4, =EMC_PINSEL5_Val - STR R4, [R2, #PINSEL5_OFS] - LDR R4, =EMC_PINSEL6_Val - STR R4, [R2, #PINSEL6_OFS] - LDR R4, =EMC_PINSEL8_Val - STR R4, [R2, #PINSEL8_OFS] - LDR R4, =EMC_PINSEL9_Val - STR R4, [R2, #PINSEL9_OFS] - -; Setup Dynamic Memory Interface - IF (EMC_DYNAMIC_SETUP != 0) - - LDR R4, =EMC_DYN_RP_Val - STR R4, [R0, #EMC_DYN_RP_OFS] - LDR R4, =EMC_DYN_RAS_Val - STR R4, [R0, #EMC_DYN_RAS_OFS] - LDR R4, =EMC_DYN_SREX_Val - STR R4, [R0, #EMC_DYN_SREX_OFS] - LDR R4, =EMC_DYN_APR_Val - STR R4, [R0, #EMC_DYN_APR_OFS] - LDR R4, =EMC_DYN_DAL_Val - STR R4, [R0, #EMC_DYN_DAL_OFS] - LDR R4, =EMC_DYN_WR_Val - STR R4, [R0, #EMC_DYN_WR_OFS] - LDR R4, =EMC_DYN_RC_Val - STR R4, [R0, #EMC_DYN_RC_OFS] - LDR R4, =EMC_DYN_RFC_Val - STR R4, [R0, #EMC_DYN_RFC_OFS] - LDR R4, =EMC_DYN_XSR_Val - STR R4, [R0, #EMC_DYN_XSR_OFS] - LDR R4, =EMC_DYN_RRD_Val - STR R4, [R0, #EMC_DYN_RRD_OFS] - LDR R4, =EMC_DYN_MRD_Val - STR R4, [R0, #EMC_DYN_MRD_OFS] - - LDR R4, =EMC_DYN_RD_CFG_Val - STR R4, [R0, #EMC_DYN_RD_CFG_OFS] - - IF (EMC_DYNCS0_SETUP != 0) - LDR R4, =EMC_DYN_RASCAS0_Val - STR R4, [R0, #EMC_DYN_RASCAS0_OFS] - LDR R4, =EMC_DYN_CFG0_Val - MVN R5, #BUFEN_Const - AND R4, R4, R5 - STR R4, [R0, #EMC_DYN_CFG0_OFS] - ENDIF - IF (EMC_DYNCS1_SETUP != 0) - LDR R4, =EMC_DYN_RASCAS1_Val - STR R4, [R0, #EMC_DYN_RASCAS1_OFS] - LDR R4, =EMC_DYN_CFG1_Val - MVN R5, =BUFEN_Const - AND R4, R4, R5 - STR R4, [R0, #EMC_DYN_CFG1_OFS] - ENDIF - IF (EMC_DYNCS2_SETUP != 0) - LDR R4, =EMC_DYN_RASCAS2_Val - STR R4, [R0, #EMC_DYN_RASCAS2_OFS] - LDR R4, =EMC_DYN_CFG2_Val - MVN R5, =BUFEN_Const - AND R4, R4, R5 - STR R4, [R0, #EMC_DYN_CFG2_OFS] - ENDIF - IF (EMC_DYNCS3_SETUP != 0) - LDR R4, =EMC_DYN_RASCAS3_Val - STR R4, [R0, #EMC_DYN_RASCAS3_OFS] - LDR R4, =EMC_DYN_CFG3_Val - MVN R5, =BUFEN_Const - AND R4, R4, R5 - STR R4, [R0, #EMC_DYN_CFG3_OFS] - ENDIF - - LDR R6, =1440000 ; Number of cycles to delay -Wait_0 SUBS R6, R6, #1 ; Delay ~100 ms proc clk 57.6 MHz - BNE Wait_0 ; BNE (3 cyc) + SUBS (1 cyc) = 4 cyc - - LDR R4, =(NOP_CMD:OR:0x03) ; Write NOP Command - STR R4, [R0, #EMC_DYN_CTRL_OFS] - - LDR R6, =2880000 ; Number of cycles to delay -Wait_1 SUBS R6, R6, #1 ; Delay ~200 ms proc clk 57.6 MHz - BNE Wait_1 - - LDR R4, =(PALL_CMD:OR:0x03) ; Write Precharge All Command - STR R4, [R0, #EMC_DYN_CTRL_OFS] - - MOV R4, #2 - STR R4, [R0, #EMC_DYN_RFSH_OFS] - - MOV R6, #64 ; Number of cycles to delay -Wait_2 SUBS R6, R6, #1 ; Delay - BNE Wait_2 - - LDR R4, =EMC_DYN_RFSH_Val - STR R4, [R0, #EMC_DYN_RFSH_OFS] - - LDR R4, =(MODE_CMD:OR:0x03) ; Write MODE Command - STR R4, [R0, #EMC_DYN_CTRL_OFS] - - ; Dummy read - IF (EMC_DYNCS0_SETUP != 0) - LDR R4, =DYN_MEM0_BASE - MOV R5, #(0x33 << 12) - ADD R4, R4, R5 - LDR R4, [R4, #0] - ENDIF - IF (EMC_DYNCS1_SETUP != 0) - LDR R4, =DYN_MEM1_BASE - MOV R5, #(0x33 << 12) - ADD R4, R4, R5 - LDR R4, [R4, #0] - ENDIF - IF (EMC_DYNCS2_SETUP != 0) - LDR R4, =DYN_MEM2_BASE - MOV R5, #(0x33 << 12) - ADD R4, R4, R5 - LDR R4, [R4, #0] - ENDIF - IF (EMC_DYNCS3_SETUP != 0) - LDR R4, =DYN_MEM3_BASE - MOV R5, #(0x33 << 12) - ADD R4, R4, R5 - LDR R4, [R4, #0] - ENDIF - - LDR R4, =NORMAL_CMD ; Write NORMAL Command - STR R4, [R0, #EMC_DYN_CTRL_OFS] - - ; Enable buffer if requested by settings - IF (EMC_DYNCS0_SETUP != 0):LAND:((EMC_DYN_CFG0_Val:AND:BUFEN_Const) != 0) - LDR R4, =EMC_DYN_CFG0_Val - STR R4, [R0, #EMC_DYN_CFG0_OFS] - ENDIF - IF (EMC_DYNCS1_SETUP != 0):LAND:((EMC_DYN_CFG1_Val:AND:BUFEN_Const) != 0) - LDR R4, =EMC_DYN_CFG1_Val - STR R4, [R0, #EMC_DYN_CFG1_OFS] - ENDIF - IF (EMC_DYNCS2_SETUP != 0):LAND:((EMC_DYN_CFG2_Val:AND:BUFEN_Const) != 0) - LDR R4, =EMC_DYN_CFG2_Val - STR R4, [R0, #EMC_DYN_CFG2_OFS] - ENDIF - IF (EMC_DYNCS3_SETUP != 0):LAND:((EMC_DYN_CFG3_Val:AND:BUFEN_Const) != 0) - LDR R4, =EMC_DYN_CFG3_Val - STR R4, [R0, #EMC_DYN_CFG3_OFS] - ENDIF - - LDR R6, =14400 ; Number of cycles to delay -Wait_3 SUBS R6, R6, #1 ; Delay ~1 ms @ proc clk 57.6 MHz - BNE Wait_3 - - ENDIF ; EMC_DYNAMIC_SETUP - -; Setup Static Memory Interface - IF (EMC_STATIC_SETUP != 0) - - LDR R6, =1440000 ; Number of cycles to delay -Wait_4 SUBS R6, R6, #1 ; Delay ~100 ms @ proc clk 57.6 MHz - BNE Wait_4 - - IF (EMC_STACS0_SETUP != 0) - LDR R4, =EMC_STA_CFG0_Val - STR R4, [R0, #EMC_STA_CFG0_OFS] - LDR R4, =EMC_STA_WWEN0_Val - STR R4, [R0, #EMC_STA_WWEN0_OFS] - LDR R4, =EMC_STA_WOEN0_Val - STR R4, [R0, #EMC_STA_WOEN0_OFS] - LDR R4, =EMC_STA_WRD0_Val - STR R4, [R0, #EMC_STA_WRD0_OFS] - LDR R4, =EMC_STA_WPAGE0_Val - STR R4, [R0, #EMC_STA_WPAGE0_OFS] - LDR R4, =EMC_STA_WWR0_Val - STR R4, [R0, #EMC_STA_WWR0_OFS] - LDR R4, =EMC_STA_WTURN0_Val - STR R4, [R0, #EMC_STA_WTURN0_OFS] - ENDIF - - IF (EMC_STACS1_SETUP != 0) - LDR R4, =EMC_STA_CFG1_Val - STR R4, [R0, #EMC_STA_CFG1_OFS] - LDR R4, =EMC_STA_WWEN1_Val - STR R4, [R0, #EMC_STA_WWEN1_OFS] - LDR R4, =EMC_STA_WOEN1_Val - STR R4, [R0, #EMC_STA_WOEN1_OFS] - LDR R4, =EMC_STA_WRD1_Val - STR R4, [R0, #EMC_STA_WRD1_OFS] - LDR R4, =EMC_STA_WPAGE1_Val - STR R4, [R0, #EMC_STA_WPAGE1_OFS] - LDR R4, =EMC_STA_WWR1_Val - STR R4, [R0, #EMC_STA_WWR1_OFS] - LDR R4, =EMC_STA_WTURN1_Val - STR R4, [R0, #EMC_STA_WTURN1_OFS] - ENDIF - - IF (EMC_STACS2_SETUP != 0) - LDR R4, =EMC_STA_CFG2_Val - STR R4, [R0, #EMC_STA_CFG2_OFS] - LDR R4, =EMC_STA_WWEN2_Val - STR R4, [R0, #EMC_STA_WWEN2_OFS] - LDR R4, =EMC_STA_WOEN2_Val - STR R4, [R0, #EMC_STA_WOEN2_OFS] - LDR R4, =EMC_STA_WRD2_Val - STR R4, [R0, #EMC_STA_WRD2_OFS] - LDR R4, =EMC_STA_WPAGE2_Val - STR R4, [R0, #EMC_STA_WPAGE2_OFS] - LDR R4, =EMC_STA_WWR2_Val - STR R4, [R0, #EMC_STA_WWR2_OFS] - LDR R4, =EMC_STA_WTURN2_Val - STR R4, [R0, #EMC_STA_WTURN2_OFS] - ENDIF - - IF (EMC_STACS3_SETUP != 0) - LDR R4, =EMC_STA_CFG3_Val - STR R4, [R0, #EMC_STA_CFG3_OFS] - LDR R4, =EMC_STA_WWEN3_Val - STR R4, [R0, #EMC_STA_WWEN3_OFS] - LDR R4, =EMC_STA_WOEN3_Val - STR R4, [R0, #EMC_STA_WOEN3_OFS] - LDR R4, =EMC_STA_WRD3_Val - STR R4, [R0, #EMC_STA_WRD3_OFS] - LDR R4, =EMC_STA_WPAGE3_Val - STR R4, [R0, #EMC_STA_WPAGE3_OFS] - LDR R4, =EMC_STA_WWR3_Val - STR R4, [R0, #EMC_STA_WWR3_OFS] - LDR R4, =EMC_STA_WTURN3_Val - STR R4, [R0, #EMC_STA_WTURN3_OFS] - ENDIF - - LDR R6, =144000 ; Number of cycles to delay -Wait_5 SUBS R6, R6, #1 ; Delay ~10 ms @ proc clk 57.6 MHz - BNE Wait_5 - - LDR R4, =EMC_STA_EXT_W_Val - LDR R5, =EMC_STA_EXT_W_OFS - ADD R5, R5, R0 - STR R4, [R5, #0] - - ENDIF ; EMC_STATIC_SETUP - - ENDIF ; EMC_SETUP - - -; Copy Exception Vectors to Internal RAM --------------------------------------- - - IF :DEF:RAM_INTVEC - ADR R8, Vectors ; Source - LDR R9, =RAM_BASE ; Destination - LDMIA R8!, {R0-R7} ; Load Vectors - STMIA R9!, {R0-R7} ; Store Vectors - LDMIA R8!, {R0-R7} ; Load Handler Addresses - STMIA R9!, {R0-R7} ; Store Handler Addresses - ENDIF - - -; Memory Mapping (when Interrupt Vectors are in RAM) --------------------------- - -MEMMAP EQU 0xE01FC040 ; Memory Mapping Control - IF :DEF:REMAP - LDR R0, =MEMMAP - IF :DEF:EXTMEM_MODE - MOV R1, #3 - ELIF :DEF:RAM_MODE - MOV R1, #2 - ELSE - MOV R1, #1 - ENDIF - STR R1, [R0] - ENDIF - - -; Setup Stack for each mode ---------------------------------------------------- - - LDR R0, =Stack_Top - -; Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #UND_Stack_Size - -; Enter Abort Mode and set its Stack Pointer - MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #ABT_Stack_Size - -; Enter FIQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #FIQ_Stack_Size - -; Enter IRQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #IRQ_Stack_Size - -; Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #SVC_Stack_Size - - IF :DEF:__MICROLIB - EXPORT __initial_sp - ELSE - ENDIF - -; Enter the C code ------------------------------------------------------------- - - IMPORT __main - LDR R0, =__main - BX R0 - - IMPORT rt_interrupt_enter - IMPORT rt_interrupt_leave - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - IMPORT rt_hw_trap_irq - -IRQ_Handler PROC - EXPORT IRQ_Handler - STMFD sp!, {r0-r12,lr} - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; if rt_thread_switch_interrupt_flag set, jump to - ; rt_hw_context_switch_interrupt_do and don't return - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD sp!, {r0-r12,lr} - SUBS pc, lr, #4 - ENDP - -; /* -; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) -; */ -rt_hw_context_switch_interrupt_do PROC - EXPORT rt_hw_context_switch_interrupt_do - MOV r1, #0 ; clear flag - STR r1, [r0] - - LDMFD sp!, {r0-r12,lr}; reload saved registers - STMFD sp!, {r0-r3} ; save r0-r3 - MOV r1, sp - ADD sp, sp, #16 ; restore sp - SUB r2, lr, #4 ; save old task's pc to r2 - - MRS r3, spsr ; get cpsr of interrupt thread - - ; switch to SVC mode and no interrupt - MSR cpsr_c, #I_Bit :OR: F_Bit :OR: Mode_SVC - - STMFD sp!, {r2} ; push old task's pc - STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 - MOV r4, r1 ; Special optimised code below - MOV r5, r3 - LDMFD r4!, {r0-r3} - STMFD sp!, {r0-r3} ; push old task's r3-r0 - STMFD sp!, {r5} ; push old task's cpsr - - LDR r4, =rt_interrupt_from_thread - LDR r5, [r4] - STR sp, [r5] ; store sp in preempted tasks's TCB - - LDR r6, =rt_interrupt_to_thread - LDR r6, [r6] - LDR sp, [r6] ; get new task's stack pointer - - LDMFD sp!, {r4} ; pop new task's cpsr to spsr - MSR spsr_cxsf, r4 - BIC r4, r4, #0x20 ; must be ARM mode - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr - ENDP - - IF :DEF:__MICROLIB - - EXPORT __heap_base - EXPORT __heap_limit - - ELSE -; User Initial Stack & Heap - AREA |.text|, CODE, READONLY - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + USR_Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDIF - - - END diff --git a/rt-thread/libcpu/arm/lpc24xx/trap.c b/rt-thread/libcpu/arm/lpc24xx/trap.c deleted file mode 100644 index 7ad7328..0000000 --- a/rt-thread/libcpu/arm/lpc24xx/trap.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2008-12-11 XuXinming first version - */ - -#include -#include - -#include "LPC24xx.h" - -//#define BSP_INT_DEBUG - -/** - * @addtogroup LPC2478 - */ -/*@{*/ - -/** - * this function will show registers of CPU - * - * @param regs the registers point - */ -void rt_hw_show_register (struct rt_hw_register *regs) -{ - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); -} - -/** - * When ARM7TDMI comes across an instruction which it cannot handle, - * it takes the undefined instruction trap. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_udef(struct rt_hw_register *regs) -{ - rt_kprintf("undefined instruction\n"); - rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); - rt_hw_cpu_shutdown(); -} - -/** - * The software interrupt instruction (SWI) is used for entering - * Supervisor mode, usually to request a particular supervisor - * function. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_swi(struct rt_hw_register *regs) -{ - rt_kprintf("software interrupt\n"); - rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during an instruction prefetch. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_pabt(struct rt_hw_register *regs) -{ - rt_kprintf("prefetch abort\n"); - rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during a data access. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_dabt(struct rt_hw_register *regs) -{ - rt_kprintf("Data Abort "); - rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); - rt_hw_cpu_shutdown(); -} - -/** - * Normally, system will never reach here - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_resv(struct rt_hw_register *regs) -{ - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); - rt_hw_cpu_shutdown(); -} - -extern rt_isr_handler_t isr_table[]; -void rt_hw_trap_irq(void) -{ - int irqno; - struct rt_irq_desc* irq; - extern struct rt_irq_desc irq_desc[]; - - irq = (struct rt_irq_desc*) VICVectAddr; - irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); - - /* invoke isr */ - irq->handler(irqno, irq->param); -} - -void rt_hw_trap_fiq(void) -{ - rt_kprintf("fast interrupt request\n"); -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/realview-a8-vmm/SConscript b/rt-thread/libcpu/arm/realview-a8-vmm/SConscript deleted file mode 100644 index b259a94..0000000 --- a/rt-thread/libcpu/arm/realview-a8-vmm/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/realview-a8-vmm/armv7.h b/rt-thread/libcpu/arm/realview-a8-vmm/armv7.h deleted file mode 100644 index f284bb5..0000000 --- a/rt-thread/libcpu/arm/realview-a8-vmm/armv7.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ -#ifndef __ARMV7_H__ -#define __ARMV7_H__ - -/* the exception stack without VFP registers */ -struct rt_hw_exp_stack -{ - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; -}; - -struct rt_hw_stack -{ - unsigned long cpsr; - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long lr; - unsigned long pc; -}; - -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define MONITORMODE 0x16 -#define ABORTMODE 0x17 -#define HYPMODE 0x1b -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -#define T_Bit (1<<5) -#define F_Bit (1<<6) -#define I_Bit (1<<7) -#define A_Bit (1<<8) -#define E_Bit (1<<9) -#define J_Bit (1<<24) - -#endif diff --git a/rt-thread/libcpu/arm/realview-a8-vmm/context_gcc.S b/rt-thread/libcpu/arm/realview-a8-vmm/context_gcc.S deleted file mode 100644 index ae672d9..0000000 --- a/rt-thread/libcpu/arm/realview-a8-vmm/context_gcc.S +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - */ - -#include - -#ifdef RT_USING_VMM -#include -#endif - -.section .text, "ax" -/* - * rt_base_t rt_hw_interrupt_disable(); - */ -.globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mrs r0, cpsr - cpsid i - bx lr - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ -.globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - msr cpsr, r0 - bx lr - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to - */ -.globl rt_hw_context_switch_to -rt_hw_context_switch_to: - ldr sp, [r0] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc - -.section .bss.share.isr -_guest_switch_lvl: - .word 0 - -.globl vmm_virq_update - -.section .text.isr, "ax" -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to - */ -.globl rt_hw_context_switch -rt_hw_context_switch: - stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) - stmfd sp!, {r0-r12, lr} @ push lr & register file - - mrs r4, cpsr - tst lr, #0x01 - orrne r4, r4, #0x20 @ it's thumb code - - stmfd sp!, {r4} @ push cpsr - - str sp, [r0] @ store sp in preempted tasks TCB - ldr sp, [r1] @ get new task stack pointer - -#ifdef RT_USING_VMM -#ifdef RT_VMM_USING_DOMAIN - @ need to make sure we are in vmm domain as we would use rt_current_thread - ldr r2, =vmm_domain_val - ldr r7, [r2] - mcr p15, 0, r7, c3, c0 -#endif - - /* check whether vmm thread, otherwise, update vIRQ */ - ldr r3, =rt_current_thread - ldr r4, [r3] - ldr r5, =vmm_thread - cmp r4, r5 - beq switch_to_guest - - @ not falling into guest. Simple task ;-) - ldmfd sp!, {r6} @ pop new task cpsr to spsr - msr spsr_cxsf, r6 - ldmfd sp!, {r0-r12, lr, pc}^ - -switch_to_guest: -#ifdef RT_VMM_USING_DOMAIN - @ the stack is saved in the guest domain so we need to - @ come back to the guest domain to get the registers. - ldr r1, =super_domain_val - ldr r0, [r1] - mcr p15, 0, r0, c3, c0 -#endif - /* The user can do nearly anything in rt_thread_idle_excute because it will - call the thread->cleanup. One common thing is sending events and wake up - threads. So the guest thread will be preempted. This is the only point that - the guest thread would call rt_hw_context_switch and "yield". - - More over, rt_schedule will call this function and this function *will* - reentrant. If that happens, we need to make sure that call the - rt_thread_idle_excute and vmm_virq_update again and we are in super domain. - I use a "reference count" to achieve such behaviour. If you have better - idea, tell me. */ - ldr r4, =_guest_switch_lvl - ldr r5, [r4] - add r5, r5, #1 - str r5, [r4] - cmp r5, #1 - bne _switch_through - - bl rt_thread_idle_excute - bl vmm_virq_update - - /* we need _guest_switch_lvl to protect until _switch_through, but it's OK - * to cleanup the reference count here because the code below will not be - * reentrant. */ - sub r5, r5, #1 - str r5, [r4] - -#ifdef RT_VMM_USING_DOMAIN - ldr r1, =guest_domain_val - ldr r0, [r1] - mcr p15, 0, r0, c3, c0 -#endif -_switch_through: -#endif /* RT_USING_VMM */ - ldmfd sp!, {r4} @ pop new task cpsr to spsr - msr spsr_cxsf, r4 - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - */ -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -.globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - ldr r2, =rt_thread_switch_interrupt_flag - ldr r3, [r2] - cmp r3, #1 - beq _reswitch - ldr ip, =rt_interrupt_from_thread @ set rt_interrupt_from_thread - mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 - str r0, [ip] - str r3, [r2] -_reswitch: - ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread - str r1, [r2] - bx lr diff --git a/rt-thread/libcpu/arm/realview-a8-vmm/cp15.h b/rt-thread/libcpu/arm/realview-a8-vmm/cp15.h deleted file mode 100644 index b18331a..0000000 --- a/rt-thread/libcpu/arm/realview-a8-vmm/cp15.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ -#ifndef __CP15_H__ -#define __CP15_H__ - -unsigned long rt_cpu_get_smp_id(void); - -void rt_cpu_mmu_disable(void); -void rt_cpu_mmu_enable(void); -void rt_cpu_tlb_set(volatile unsigned long*); - -void rt_cpu_vector_set_base(unsigned int addr); - -#endif diff --git a/rt-thread/libcpu/arm/realview-a8-vmm/cp15_gcc.S b/rt-thread/libcpu/arm/realview-a8-vmm/cp15_gcc.S deleted file mode 100644 index 0e3e606..0000000 --- a/rt-thread/libcpu/arm/realview-a8-vmm/cp15_gcc.S +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - */ - -.globl rt_cpu_get_smp_id -rt_cpu_get_smp_id: - mrc p15, #0, r0, c0, c0, #5 - bx lr - -.globl rt_cpu_vector_set_base -rt_cpu_vector_set_base: - mcr p15, #0, r0, c12, c0, #0 - dsb - bx lr - -.globl rt_hw_cpu_dcache_enable -rt_hw_cpu_dcache_enable: - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x00000004 - mcr p15, #0, r0, c1, c0, #0 - bx lr - -.globl rt_hw_cpu_icache_enable -rt_hw_cpu_icache_enable: - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x00001000 - mcr p15, #0, r0, c1, c0, #0 - bx lr - -_FLD_MAX_WAY: - .word 0x3ff -_FLD_MAX_IDX: - .word 0x7ff - -.globl rt_cpu_dcache_clean_flush -rt_cpu_dcache_clean_flush: - push {r4-r11} - dmb - mrc p15, #1, r0, c0, c0, #1 @ read clid register - ands r3, r0, #0x7000000 @ get level of coherency - mov r3, r3, lsr #23 - beq finished - mov r10, #0 -loop1: - add r2, r10, r10, lsr #1 - mov r1, r0, lsr r2 - and r1, r1, #7 - cmp r1, #2 - blt skip - mcr p15, #2, r10, c0, c0, #0 - isb - mrc p15, #1, r1, c0, c0, #0 - and r2, r1, #7 - add r2, r2, #4 - ldr r4, _FLD_MAX_WAY - ands r4, r4, r1, lsr #3 - clz r5, r4 - ldr r7, _FLD_MAX_IDX - ands r7, r7, r1, lsr #13 -loop2: - mov r9, r4 -loop3: - orr r11, r10, r9, lsl r5 - orr r11, r11, r7, lsl r2 - mcr p15, #0, r11, c7, c14, #2 - subs r9, r9, #1 - bge loop3 - subs r7, r7, #1 - bge loop2 -skip: - add r10, r10, #2 - cmp r3, r10 - bgt loop1 - -finished: - dsb - isb - pop {r4-r11} - bx lr - -.globl rt_hw_cpu_dcache_disable -rt_hw_cpu_dcache_disable: - push {r4-r11, lr} - bl rt_cpu_dcache_clean_flush - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #0x00000004 - mcr p15, #0, r0, c1, c0, #0 - pop {r4-r11, lr} - bx lr - -.globl rt_hw_cpu_icache_disable -rt_hw_cpu_icache_disable: - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #0x00001000 - mcr p15, #0, r0, c1, c0, #0 - bx lr - -.globl rt_cpu_mmu_disable -rt_cpu_mmu_disable: - mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #1 - mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit - dsb - bx lr - -.globl rt_cpu_mmu_enable -rt_cpu_mmu_enable: - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x001 - mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit - dsb - bx lr - -.globl rt_cpu_tlb_set -rt_cpu_tlb_set: - mcr p15, #0, r0, c2, c0, #0 - dmb - bx lr diff --git a/rt-thread/libcpu/arm/realview-a8-vmm/cpu.c b/rt-thread/libcpu/arm/realview-a8-vmm/cpu.c deleted file mode 100644 index 48e859e..0000000 --- a/rt-thread/libcpu/arm/realview-a8-vmm/cpu.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-09-15 Bernard first version - */ - -#include -#include -#include - -/** - * @addtogroup AM33xx - */ -/*@{*/ - -/** shutdown CPU */ -RT_WEAK void rt_hw_cpu_shutdown() -{ - rt_base_t level; - rt_kprintf("shutdown...\n"); - - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/realview-a8-vmm/gic.c b/rt-thread/libcpu/arm/realview-a8-vmm/gic.c deleted file mode 100644 index 9623178..0000000 --- a/rt-thread/libcpu/arm/realview-a8-vmm/gic.c +++ /dev/null @@ -1,312 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - * 2014-04-03 Grissiom many enhancements - */ - -#include -#include - -#include "gic.h" -#include "cp15.h" - -struct arm_gic -{ - rt_uint32_t offset; - - rt_uint32_t dist_hw_base; - rt_uint32_t cpu_hw_base; -}; -static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; - -#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00) -#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04) -#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08) -#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c) -#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10) -#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14) -#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18) - -#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000) -#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004) -#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4) -#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4) -#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) -#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) -#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4) -#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380 + ((n)/32) * 4) -#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4) -#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4) -#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) -#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) -#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + ((n)/4) * 4) -#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8) - -static unsigned int _gic_max_irq; - -int arm_gic_get_active_irq(rt_uint32_t index) -{ - int irq; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base); - irq += _gic_table[index].offset; - return irq; -} - -void arm_gic_ack(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; - GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; -} - -void arm_gic_mask(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; -} - -void arm_gic_clear_pending(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; -} - -void arm_gic_clear_active(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; -} - -void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) -{ - rt_uint32_t old_tgt; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); - - old_tgt &= ~(0x0FFUL << ((irq % 4)*8)); - old_tgt |= cpumask << ((irq % 4)*8); - - GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; -} - -void arm_gic_umask(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; -} - -void arm_gic_dump_type(rt_uint32_t index) -{ - unsigned int gic_type; - - gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); - rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", - (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf, - _gic_table[index].dist_hw_base, - _gic_max_irq, - gic_type & (1 << 10) ? "has" : "no", - gic_type); -} - -void arm_gic_dump(rt_uint32_t index) -{ - unsigned int i, k; - - k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); - rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); - rt_kprintf("--- hw mask ---\n"); - for (i = 0; i < _gic_max_irq / 32; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, - i * 32)); - } - rt_kprintf("\n--- hw pending ---\n"); - for (i = 0; i < _gic_max_irq / 32; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, - i * 32)); - } - rt_kprintf("\n--- hw active ---\n"); - for (i = 0; i < _gic_max_irq / 32; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, - i * 32)); - } - rt_kprintf("\n"); -} -#ifdef RT_USING_FINSH -#include -FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status); -#endif - -int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) -{ - unsigned int gic_type, i; - rt_uint32_t cpumask = 1 << 0; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - _gic_table[index].dist_hw_base = dist_base; - _gic_table[index].offset = irq_start; - - /* Find out how many interrupts are supported. */ - gic_type = GIC_DIST_TYPE(dist_base); - _gic_max_irq = ((gic_type & 0x1f) + 1) * 32; - - /* - * The GIC only supports up to 1020 interrupt sources. - * Limit this to either the architected maximum, or the - * platform maximum. - */ - if (_gic_max_irq > 1020) - _gic_max_irq = 1020; - if (_gic_max_irq > ARM_GIC_NR_IRQS) - _gic_max_irq = ARM_GIC_NR_IRQS; - -#ifndef RT_PRETENT_AS_CPU0 - /* If we are run on the second core, the GIC should have already been setup - * by BootStrapProcessor. */ - if ((rt_cpu_get_smp_id() & 0xF) != 0) - return 0; -#endif -#ifdef RT_USING_VMM - return 0; -#endif - - cpumask |= cpumask << 8; - cpumask |= cpumask << 16; - - GIC_DIST_CTRL(dist_base) = 0x0; - - /* Set all global interrupts to be level triggered, active low. */ - for (i = 32; i < _gic_max_irq; i += 16) - GIC_DIST_CONFIG(dist_base, i) = 0x0; - - /* Set all global interrupts to this CPU only. */ - for (i = 32; i < _gic_max_irq; i += 4) - GIC_DIST_TARGET(dist_base, i) = cpumask; - - /* Set priority on all interrupts. */ - for (i = 0; i < _gic_max_irq; i += 4) - GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0; - - /* Disable all interrupts. */ - for (i = 0; i < _gic_max_irq; i += 32) - GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff; - /* All interrupts defaults to IGROUP1(IRQ). */ - for (i = 0; i < _gic_max_irq; i += 32) - GIC_DIST_IGROUP(dist_base, i) = 0xffffffff; - - /* Enable group0 and group1 interrupt forwarding. */ - GIC_DIST_CTRL(dist_base) = 0x03; - - return 0; -} - -int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - _gic_table[index].cpu_hw_base = cpu_base; - -#ifndef RT_PRETENT_AS_CPU0 - /* If we are run on the second core, the GIC should have already been setup - * by BootStrapProcessor. */ - if ((rt_cpu_get_smp_id() & 0xF) != 0) - return 0; -#endif -#ifdef RT_USING_VMM - return 0; -#endif - - GIC_CPU_PRIMASK(cpu_base) = 0xf0; - /* Enable CPU interrupt */ - GIC_CPU_CTRL(cpu_base) = 0x01; - - return 0; -} - -void arm_gic_set_group(rt_uint32_t index, int vector, int group) -{ - /* As for GICv2, there are only group0 and group1. */ - RT_ASSERT(group <= 1); - RT_ASSERT(vector < _gic_max_irq); - - if (group == 0) - { - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, - vector) &= ~(1 << (vector % 32)); - } - else if (group == 1) - { - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, - vector) |= (1 << (vector % 32)); - } -} - -void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq) -{ - unsigned int reg; - - RT_ASSERT(irq <= 15); - RT_ASSERT(target_cpu <= 255); - - reg = (target_cpu << 16) | irq; - GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = reg; -} - -void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq) -{ - RT_ASSERT(irq <= 15); - RT_ASSERT(target_cpu <= 255); - - GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = target_cpu << (irq % 4); -} diff --git a/rt-thread/libcpu/arm/realview-a8-vmm/gic.h b/rt-thread/libcpu/arm/realview-a8-vmm/gic.h deleted file mode 100644 index 7c781ad..0000000 --- a/rt-thread/libcpu/arm/realview-a8-vmm/gic.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#ifndef __GIC_H__ -#define __GIC_H__ - -int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); -int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); - -void arm_gic_mask(rt_uint32_t index, int irq); -void arm_gic_umask(rt_uint32_t index, int irq); -void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); -void arm_gic_set_group(rt_uint32_t index, int vector, int group); - -int arm_gic_get_active_irq(rt_uint32_t index); -void arm_gic_ack(rt_uint32_t index, int irq); - -void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq); -void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq); - -void arm_gic_dump_type(rt_uint32_t index); - -#endif - diff --git a/rt-thread/libcpu/arm/realview-a8-vmm/interrupt.c b/rt-thread/libcpu/arm/realview-a8-vmm/interrupt.c deleted file mode 100644 index 23ff062..0000000 --- a/rt-thread/libcpu/arm/realview-a8-vmm/interrupt.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-06 Bernard first version - * 2014-04-03 Grissiom port to VMM - */ - -#include -#include -#include "realview.h" -#include "gic.h" - -#ifdef RT_USING_VMM -#include -#endif - -#define MAX_HANDLERS NR_IRQS_PBA8 - -extern volatile rt_uint8_t rt_interrupt_nest; - -/* exception and interrupt handler table */ -struct rt_irq_desc isr_table[MAX_HANDLERS]; - -/* Those varibles will be accessed in ISR, so we need to share them. */ -rt_uint32_t rt_interrupt_from_thread RT_SECTION(".bss.share.int"); -rt_uint32_t rt_interrupt_to_thread RT_SECTION(".bss.share.int"); -rt_uint32_t rt_thread_switch_interrupt_flag RT_SECTION(".bss.share.int"); - -const unsigned int VECTOR_BASE = 0x00; -extern void rt_cpu_vector_set_base(unsigned int addr); -extern int system_vectors; - -static void rt_hw_vector_init(void) -{ -#ifndef RT_USING_VMM - unsigned int *dest = (unsigned int *)VECTOR_BASE; - unsigned int *src = (unsigned int *)&system_vectors; - - rt_memcpy(dest, src, 16 * 4); - rt_cpu_vector_set_base(VECTOR_BASE); -#endif -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - rt_uint32_t gic_cpu_base; - rt_uint32_t gic_dist_base; - - /* initialize vector table */ - rt_hw_vector_init(); - - /* initialize exceptions table */ - rt_memset(isr_table, 0x00, sizeof(isr_table)); - - /* initialize ARM GIC */ -#ifdef RT_USING_VMM - gic_dist_base = vmm_find_iomap("GIC_DIST"); - gic_cpu_base = vmm_find_iomap("GIC_CPU"); -#else - gic_dist_base = REALVIEW_GIC_DIST_BASE; - gic_cpu_base = REALVIEW_GIC_CPU_BASE; -#endif - arm_gic_dist_init(0, gic_dist_base, 0); - arm_gic_cpu_init(0, gic_cpu_base); - /*arm_gic_dump_type(0);*/ - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - arm_gic_mask(0, vector); -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - arm_gic_umask(0, vector); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param new_handler the interrupt service routine to be installed - * @param old_handler the old interrupt service routine - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if (vector < MAX_HANDLERS) - { - old_handler = isr_table[vector].handler; - - if (handler != RT_NULL) - { -#ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); -#endif /* RT_USING_INTERRUPT_INFO */ - isr_table[vector].handler = handler; - isr_table[vector].param = param; - } - } - - return old_handler; -} - -/** - * Trigger a software IRQ - * - * Since we are running in single core, the target CPU are always CPU0. - */ -void rt_hw_interrupt_trigger(int vector) -{ - arm_gic_trigger(0, 1, vector); -} - -void rt_hw_interrupt_clear(int vector) -{ - arm_gic_clear_sgi(0, 1, vector); -} diff --git a/rt-thread/libcpu/arm/realview-a8-vmm/interrupt.h b/rt-thread/libcpu/arm/realview-a8-vmm/interrupt.h deleted file mode 100644 index 90f392f..0000000 --- a/rt-thread/libcpu/arm/realview-a8-vmm/interrupt.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-06 Bernard first version - */ - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#define INT_IRQ 0x00 -#define INT_FIQ 0x01 - -#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) -#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) -#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) -#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) -#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) -#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) -#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) -#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) -#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) -#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) -#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) -#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) -#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) -#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) -#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) -#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) -#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) -#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) -#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) -#define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20)) -#define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20)) -#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) - -void rt_hw_interrupt_control(int vector, int priority, int route); -int rt_hw_interrupt_get_active(int fiq_irq); -void rt_hw_interrupt_ack(int fiq_irq); -void rt_hw_interrupt_trigger(int vector); -void rt_hw_interrupt_clear(int vector); - -#endif diff --git a/rt-thread/libcpu/arm/realview-a8-vmm/mmu.c b/rt-thread/libcpu/arm/realview-a8-vmm/mmu.c deleted file mode 100644 index f4d6068..0000000 --- a/rt-thread/libcpu/arm/realview-a8-vmm/mmu.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2012-01-10 bernard porting to AM1808 - */ - -#include -#include -#include - -#include "cp15.h" - -#define DESC_SEC (0x2) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO -#define XN (1<<4) // eXecute Never - -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) - -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) - -/* Read/Write, cache, write back */ -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) -/* Read/Write, cache, write through */ -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) -/* Read/Write without cache and write buffer */ -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) -/* Read/Write without cache and write buffer, no execute */ -#define RW_NCNBXN (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN) -/* Read/Write without cache and write buffer */ -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) - -/* dump 2nd level page table */ -void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb) -{ - int i; - int fcnt = 0; - - for (i = 0; i < 256; i++) - { - rt_uint32_t pte2 = ptb[i]; - if ((pte2 & 0x3) == 0) - { - if (fcnt == 0) - rt_kprintf(" "); - rt_kprintf("%04x: ", i); - fcnt++; - if (fcnt == 16) - { - rt_kprintf("fault\n"); - fcnt = 0; - } - continue; - } - if (fcnt != 0) - { - rt_kprintf("fault\n"); - fcnt = 0; - } - - rt_kprintf(" %04x: %x: ", i, pte2); - if ((pte2 & 0x3) == 0x1) - { - rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n", - ((pte2 >> 7) | (pte2 >> 4))& 0xf, - (pte2 >> 15) & 0x1, - ((pte2 >> 10) | (pte2 >> 2)) & 0x1f); - } - else - { - rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n", - ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1, - ((pte2 >> 4) | (pte2 >> 2)) & 0x1f); - } - } -} - -void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) -{ - int i; - int fcnt = 0; - - rt_kprintf("page table@%p\n", ptb); - for (i = 0; i < 1024*4; i++) - { - rt_uint32_t pte1 = ptb[i]; - if ((pte1 & 0x3) == 0) - { - rt_kprintf("%03x: ", i); - fcnt++; - if (fcnt == 16) - { - rt_kprintf("fault\n"); - fcnt = 0; - } - continue; - } - if (fcnt != 0) - { - rt_kprintf("fault\n"); - fcnt = 0; - } - - rt_kprintf("%03x: %08x: ", i, pte1); - if ((pte1 & 0x3) == 0x3) - { - rt_kprintf("LPAE\n"); - } - else if ((pte1 & 0x3) == 0x1) - { - rt_kprintf("pte,ns:%d,domain:%d\n", - (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); - /* - *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) - * - 0x80000000 + 0xC0000000)); - */ - } - else if (pte1 & (1 << 18)) - { - rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", - (pte1 >> 19) & 0x1, - ((pte1 >> 13) | (pte1 >> 10))& 0xf, - (pte1 >> 4) & 0x1, - ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); - } - else - { - rt_kprintf("section,ns:%d,ap:%x," - "xn:%d,texcb:%02x,domain:%d\n", - (pte1 >> 19) & 0x1, - ((pte1 >> 13) | (pte1 >> 10))& 0xf, - (pte1 >> 4) & 0x1, - (((pte1 & (0x7 << 12)) >> 10) | - ((pte1 & 0x0c) >> 2)) & 0x1f, - (pte1 >> 5) & 0xf); - } - } -} - -/* level1 page table, each entry for 1MB memory. */ -volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); -void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, - rt_uint32_t vaddrEnd, - rt_uint32_t paddrStart, - rt_uint32_t attr) -{ - volatile rt_uint32_t *pTT; - volatile int i, nSec; - pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20); - nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); - for(i = 0; i <= nSec; i++) - { - *pTT = attr | (((paddrStart >> 20) + i) << 20); - pTT++; - } -} - -unsigned long rt_hw_set_domain_register(unsigned long domain_val) -{ - unsigned long old_domain; - - asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); - asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); - - return old_domain; -} - -void rt_hw_mmu_init(void) -{ - rt_hw_cpu_dcache_disable(); - rt_hw_cpu_icache_disable(); - rt_cpu_mmu_disable(); - - /* set page table */ - /* 4G 1:1 memory */ - rt_hw_mmu_setmtt(0, 0xffffffff-1, 0, RW_CB); - /* IO memory region */ - rt_hw_mmu_setmtt(0x44000000, 0x80000000-1, 0x44000000, RW_NCNBXN); - - /*rt_hw_cpu_dump_page_table(MMUTable);*/ - rt_hw_set_domain_register(0x55555555); - - rt_cpu_tlb_set(MMUTable); - - rt_cpu_mmu_enable(); - - rt_hw_cpu_icache_enable(); - rt_hw_cpu_dcache_enable(); -} - diff --git a/rt-thread/libcpu/arm/realview-a8-vmm/pmu.c b/rt-thread/libcpu/arm/realview-a8-vmm/pmu.c deleted file mode 100644 index 2b9165c..0000000 --- a/rt-thread/libcpu/arm/realview-a8-vmm/pmu.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ -#include -#include "pmu.h" - -void rt_hw_pmu_dump_feature(void) -{ - unsigned long reg; - - reg = rt_hw_pmu_get_control(); - rt_kprintf("ARM PMU Implementor: %c, ID code: %02x, %d counters\n", - reg >> 24, (reg >> 16) & 0xff, (reg >> 11) & 0x1f); - RT_ASSERT(ARM_PMU_CNTER_NR == ((reg >> 11) & 0x1f)); -} diff --git a/rt-thread/libcpu/arm/realview-a8-vmm/pmu.h b/rt-thread/libcpu/arm/realview-a8-vmm/pmu.h deleted file mode 100644 index 64a74b5..0000000 --- a/rt-thread/libcpu/arm/realview-a8-vmm/pmu.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ -#ifndef __PMU_H__ -#define __PMU_H__ - -#include "board.h" - -/* Number of counters */ -#define ARM_PMU_CNTER_NR 4 - -enum rt_hw_pmu_event_type { - ARM_PMU_EVENT_PMNC_SW_INCR = 0x00, - ARM_PMU_EVENT_L1_ICACHE_REFILL = 0x01, - ARM_PMU_EVENT_ITLB_REFILL = 0x02, - ARM_PMU_EVENT_L1_DCACHE_REFILL = 0x03, - ARM_PMU_EVENT_L1_DCACHE_ACCESS = 0x04, - ARM_PMU_EVENT_DTLB_REFILL = 0x05, - ARM_PMU_EVENT_MEM_READ = 0x06, - ARM_PMU_EVENT_MEM_WRITE = 0x07, - ARM_PMU_EVENT_INSTR_EXECUTED = 0x08, - ARM_PMU_EVENT_EXC_TAKEN = 0x09, - ARM_PMU_EVENT_EXC_EXECUTED = 0x0A, - ARM_PMU_EVENT_CID_WRITE = 0x0B, -}; - -/* Enable bit */ -#define ARM_PMU_PMCR_E (0x01 << 0) -/* Event counter reset */ -#define ARM_PMU_PMCR_P (0x01 << 1) -/* Cycle counter reset */ -#define ARM_PMU_PMCR_C (0x01 << 2) -/* Cycle counter divider */ -#define ARM_PMU_PMCR_D (0x01 << 3) - -#ifdef __GNUC__ -rt_inline void rt_hw_pmu_enable_cnt(int divide64) -{ - unsigned long pmcr; - unsigned long pmcntenset; - - asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); - pmcr |= ARM_PMU_PMCR_E | ARM_PMU_PMCR_P | ARM_PMU_PMCR_C; - if (divide64) - pmcr |= ARM_PMU_PMCR_D; - else - pmcr &= ~ARM_PMU_PMCR_D; - asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr)); - - /* enable all the counters */ - pmcntenset = ~0; - asm volatile ("mcr p15, 0, %0, c9, c12, 1" :: "r"(pmcntenset)); - /* clear overflows(just in case) */ - asm volatile ("mcr p15, 0, %0, c9, c12, 3" :: "r"(pmcntenset)); -} - -rt_inline unsigned long rt_hw_pmu_get_control(void) -{ - unsigned long pmcr; - asm ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); - return pmcr; -} - -rt_inline unsigned long rt_hw_pmu_get_ceid(void) -{ - unsigned long reg; - /* only PMCEID0 is supported, PMCEID1 is RAZ. */ - asm ("mrc p15, 0, %0, c9, c12, 6" : "=r"(reg)); - return reg; -} - -rt_inline unsigned long rt_hw_pmu_get_cnten(void) -{ - unsigned long pmcnt; - asm ("mrc p15, 0, %0, c9, c12, 1" : "=r"(pmcnt)); - return pmcnt; -} - -rt_inline void rt_hw_pmu_reset_cycle(void) -{ - unsigned long pmcr; - - asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); - pmcr |= ARM_PMU_PMCR_C; - asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr)); - asm volatile ("isb"); -} - -rt_inline void rt_hw_pmu_reset_event(void) -{ - unsigned long pmcr; - - asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); - pmcr |= ARM_PMU_PMCR_P; - asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr)); - asm volatile ("isb"); -} - -rt_inline unsigned long rt_hw_pmu_get_cycle(void) -{ - unsigned long cyc; - asm volatile ("isb"); - asm volatile ("mrc p15, 0, %0, c9, c13, 0" : "=r"(cyc)); - return cyc; -} - -rt_inline void rt_hw_pmu_select_counter(int idx) -{ - RT_ASSERT(idx < ARM_PMU_CNTER_NR); - - asm volatile ("mcr p15, 0, %0, c9, c12, 5" : : "r"(idx)); - /* Linux add an isb here, don't know why here. */ - asm volatile ("isb"); -} - -rt_inline void rt_hw_pmu_select_event(int idx, - enum rt_hw_pmu_event_type eve) -{ - RT_ASSERT(idx < ARM_PMU_CNTER_NR); - - rt_hw_pmu_select_counter(idx); - asm volatile ("mcr p15, 0, %0, c9, c13, 1" : : "r"(eve)); -} - -rt_inline unsigned long rt_hw_pmu_read_counter(int idx) -{ - unsigned long reg; - - rt_hw_pmu_select_counter(idx); - asm volatile ("isb"); - asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r"(reg)); - return reg; -} - -rt_inline unsigned long rt_hw_pmu_get_ovsr(void) -{ - unsigned long reg; - asm volatile ("isb"); - asm ("mrc p15, 0, %0, c9, c12, 3" : "=r"(reg)); - return reg; -} - -rt_inline void rt_hw_pmu_clear_ovsr(unsigned long reg) -{ - asm ("mcr p15, 0, %0, c9, c12, 3" : : "r"(reg)); - asm volatile ("isb"); -} - -#endif - -void rt_hw_pmu_dump_feature(void); - -#endif /* end of include guard: __PMU_H__ */ - diff --git a/rt-thread/libcpu/arm/realview-a8-vmm/stack.c b/rt-thread/libcpu/arm/realview-a8-vmm/stack.c deleted file mode 100644 index 8cf73ac..0000000 --- a/rt-thread/libcpu/arm/realview-a8-vmm/stack.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-09-23 Bernard the first version - * 2011-10-05 Bernard add thumb mode - */ -#include -#include - -/** - * @addtogroup AM33xx - */ -/*@{*/ - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - - stack_addr += sizeof(rt_uint32_t); - stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); - stk = (rt_uint32_t *)stack_addr; - *(--stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0xdeadbeef; /* r12 */ - *(--stk) = 0xdeadbeef; /* r11 */ - *(--stk) = 0xdeadbeef; /* r10 */ - *(--stk) = 0xdeadbeef; /* r9 */ - *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = 0xdeadbeef; /* r4 */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = 0xdeadbeef; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/realview-a8-vmm/start_gcc.S b/rt-thread/libcpu/arm/realview-a8-vmm/start_gcc.S deleted file mode 100644 index 2643960..0000000 --- a/rt-thread/libcpu/arm/realview-a8-vmm/start_gcc.S +++ /dev/null @@ -1,353 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - */ - -#include - -#ifdef RT_USING_VMM -#include -.equ orig_irq_isr, LINUX_VECTOR_POS+0x18 -#else -#undef RT_VMM_USING_DOMAIN -#endif - -.equ Mode_USR, 0x10 -.equ Mode_FIQ, 0x11 -.equ Mode_IRQ, 0x12 -.equ Mode_SVC, 0x13 -.equ Mode_ABT, 0x17 -.equ Mode_UND, 0x1B -.equ Mode_SYS, 0x1F - -.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled -.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled - -#ifndef RT_USING_VMM -.equ UND_Stack_Size, 0x00000000 -.equ SVC_Stack_Size, 0x00000100 -.equ ABT_Stack_Size, 0x00000000 -.equ RT_FIQ_STACK_PGSZ, 0x00000000 -.equ RT_IRQ_STACK_PGSZ, 0x00000100 -.equ USR_Stack_Size, 0x00000100 - -#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ) -#else -#define ISR_Stack_Size (RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ) -#endif - -.section .data.share.isr -/* stack */ -.globl stack_start -.globl stack_top - -.align 3 -stack_start: -.rept ISR_Stack_Size -.byte 0 -.endr -stack_top: - -.text -/* reset entry */ -.globl _reset -_reset: -#ifdef RT_USING_VMM - /* save all the parameter and variable registers */ - stmfd sp!, {r0-r12, lr} -#endif - /* set the cpu to SVC32 mode and disable interrupt */ - mrs r0, cpsr - bic r0, r0, #0x1f - orr r0, r0, #0x13 - msr cpsr_c, r0 - - /* setup stack */ - bl stack_setup - - /* clear .bss */ - mov r0,#0 /* get a zero */ - ldr r1,=__bss_start /* bss start */ - ldr r2,=__bss_end /* bss end */ - -bss_loop: - cmp r1,r2 /* check if data to clear */ - strlo r0,[r1],#4 /* clear 4 bytes */ - blo bss_loop /* loop until done */ - -#ifdef RT_USING_VMM - /* clear .bss.share */ - mov r0,#0 /* get a zero */ - ldr r1,=__bss_share_start /* bss start */ - ldr r2,=__bss_share_end /* bss end */ - -bss_share_loop: - cmp r1,r2 /* check if data to clear */ - strlo r0,[r1],#4 /* clear 4 bytes */ - blo bss_share_loop /* loop until done */ -#endif - - /* call C++ constructors of global objects */ - ldr r0, =__ctors_start__ - ldr r1, =__ctors_end__ - -ctor_loop: - cmp r0, r1 - beq ctor_end - ldr r2, [r0], #4 - stmfd sp!, {r0-r1} - mov lr, pc - bx r2 - ldmfd sp!, {r0-r1} - b ctor_loop -ctor_end: - - /* start RT-Thread Kernel */ -#ifdef RT_USING_VMM - /* restore the parameter */ - ldmfd sp!, {r0-r3} - bl vmm_entry - ldmfd sp!, {r4-r12, pc} -#else - ldr pc, _rtthread_startup -_rtthread_startup: - .word rtthread_startup -#endif - -stack_setup: - ldr r0, =stack_top -#ifdef RT_USING_VMM - @ Linux use stmia to save r0, lr and spsr. To align to 8 byte boundary, - @ just allocate 16 bytes for it. - sub r0, r0, #16 -#endif - -#ifndef RT_USING_VMM - @ Set the startup stack for svc - mov sp, r0 -#endif - -#ifndef RT_USING_VMM - @ Enter Undefined Instruction Mode and set its Stack Pointer - msr cpsr_c, #Mode_UND|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #UND_Stack_Size - - @ Enter Abort Mode and set its Stack Pointer - msr cpsr_c, #Mode_ABT|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #ABT_Stack_Size -#endif - - @ Enter FIQ Mode and set its Stack Pointer - msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #RT_FIQ_STACK_PGSZ - - @ Enter IRQ Mode and set its Stack Pointer - msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #RT_IRQ_STACK_PGSZ - - /* come back to SVC mode */ - msr cpsr_c, #Mode_SVC|I_Bit|F_Bit - bx lr - -/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */ -.section .text.isr, "ax" - .align 5 -.globl vector_fiq -vector_fiq: - stmfd sp!,{r0-r7,lr} - bl rt_hw_trap_fiq - ldmfd sp!,{r0-r7,lr} - subs pc, lr, #4 - -.globl rt_interrupt_enter -.globl rt_interrupt_leave -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread - -.globl rt_current_thread -.globl vmm_thread -.globl vmm_virq_check - - .align 5 -.globl vector_irq -vector_irq: - stmfd sp!, {r0-r12,lr} - -#ifdef RT_VMM_USING_DOMAIN - @ save the last domain - mrc p15, 0, r5, c3, c0 - @ switch to vmm domain as we are going to call vmm codes - ldr r1, =vmm_domain_val - ldr r4, [r1] - mcr p15, 0, r4, c3, c0 -#endif - - bl rt_interrupt_enter - bl rt_hw_trap_irq - bl rt_interrupt_leave - -#ifdef RT_VMM_USING_DOMAIN - @ restore the last domain. It do some redundant work but simplify the - @ logic. It might be the guest domain so rt_thread_switch_interrupt_flag - @ should lay in .bss.share - mcr p15, 0, r5, c3, c0 -#endif - - @ if rt_thread_switch_interrupt_flag set, jump to - @ rt_hw_context_switch_interrupt_do and don't return - ldr r0, =rt_thread_switch_interrupt_flag - ldr r1, [r0] - cmp r1, #1 - beq rt_hw_context_switch_interrupt_do - -#ifndef RT_USING_VMM - ldmfd sp!, {r0-r12,lr} - subs pc, lr, #4 -#else -#ifdef RT_VMM_USING_DOMAIN - @ r4 is vmm_domain_val - @ back to vmm domain as we need access rt_current_thread - mcr p15, 0, r4, c3, c0 -#endif - /* check whether we need to do IRQ routing - * ensure the int is disabled. Or there will be an infinite loop. */ - ldr r0, =rt_current_thread - ldr r0, [r0] - ldr r1, =vmm_thread - cmp r0, r1 - beq switch_to_guest - -#ifdef RT_VMM_USING_DOMAIN - @ r5 is domain of interrupted context - @ it might be super_domain_val or vmm_domain_val so we need to restore it. - mcr p15, 0, r5, c3, c0 -#endif - @ switch back if the interrupted thread is not vmm - ldmfd sp!, {r0-r12,lr} - subs pc, lr, #4 - -switch_to_guest: -#ifdef RT_VMM_USING_DOMAIN - @ We are going to execute rt-thread code but accessing the content of the - @ guest. So switch to super domain. - ldr r1, =super_domain_val - ldr r0, [r1] - mcr p15, 0, r0, c3, c0 -#endif - /* check whether there is a pending interrupt for Guest OS */ - bl vmm_virq_check - -#ifdef RT_VMM_USING_DOMAIN - @ All done, restore the guest domain. - mcr p15, 0, r5, c3, c0 -#endif - - cmp r0, #0x0 - beq route_irq_to_guest - - ldmfd sp!, {r0-r12,lr} - subs pc, lr, #4 - -route_irq_to_guest: - ldmfd sp!, {r0-r12,lr} - b orig_irq_isr -#endif /* RT_USING_VMM */ - -rt_hw_context_switch_interrupt_do: - mov r1, #0 @ clear flag - str r1, [r0] - - mov r1, sp @ r1 point to {r0-r3} in stack - add sp, sp, #4*4 - ldmfd sp!, {r4-r12,lr}@ reload saved registers - mrs r0, spsr @ get cpsr of interrupt thread - sub r2, lr, #4 @ save old task's pc to r2 - - @ Switch to SVC mode with no interrupt. If the usr mode guest is - @ interrupted, this will just switch to the stack of kernel space. - @ save the registers in kernel space won't trigger data abort. - msr cpsr_c, #I_Bit|F_Bit|Mode_SVC - - stmfd sp!, {r2} @ push old task's pc - stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4 - ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread - stmfd sp!, {r1-r4} @ push old task's r0-r3 - stmfd sp!, {r0} @ push old task's cpsr - - ldr r4, =rt_interrupt_from_thread - ldr r5, [r4] - str sp, [r5] @ store sp in preempted tasks's TCB - -#ifdef RT_VMM_USING_DOMAIN - @ If a thread is wake up by interrupt, it should be RTT thread. - @ Make sure the domain is correct. - ldr r1, =vmm_domain_val - ldr r2, [r1] - mcr p15, 0, r2, c3, c0 -#endif - ldr r6, =rt_interrupt_to_thread - ldr r6, [r6] - ldr sp, [r6] @ get new task's stack pointer - - ldmfd sp!, {r4} @ pop new task's cpsr to spsr - msr spsr_cxsf, r4 - - ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr - -.macro push_svc_reg - sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ - stmia sp, {r0 - r12} @/* Calling r0-r12 */ - mov r0, sp - mrs r6, spsr @/* Save CPSR */ - str lr, [r0, #15*4] @/* Push PC */ - str r6, [r0, #16*4] @/* Push CPSR */ - cps #Mode_SVC - str sp, [r0, #13*4] @/* Save calling SP */ - str lr, [r0, #14*4] @/* Save calling PC */ -.endm - - .align 5 - .globl vector_swi -vector_swi: - push_svc_reg - bl rt_hw_trap_swi - b . - - .align 5 - .globl vector_undef -vector_undef: - push_svc_reg - bl rt_hw_trap_undef - b . - - .align 5 - .globl vector_pabt -vector_pabt: - push_svc_reg - bl rt_hw_trap_pabt - b . - - .align 5 - .globl vector_dabt -vector_dabt: - push_svc_reg - bl rt_hw_trap_dabt - b . - - .align 5 - .globl vector_resv -vector_resv: - push_svc_reg - bl rt_hw_trap_resv - b . diff --git a/rt-thread/libcpu/arm/realview-a8-vmm/trap.c b/rt-thread/libcpu/arm/realview-a8-vmm/trap.c deleted file mode 100644 index 86eceb3..0000000 --- a/rt-thread/libcpu/arm/realview-a8-vmm/trap.c +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#include -#include -#include - -#include "armv7.h" - -#ifdef RT_USING_VMM -#include -#endif - -#include "gic.h" - -extern struct rt_thread *rt_current_thread; -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) -extern long list_thread(void); -#endif - -/** - * this function will show registers of CPU - * - * @param regs the registers point - */ -void rt_hw_show_register(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); -} - -/** - * When comes across an instruction which it cannot handle, - * it takes the undefined instruction trap. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("undefined instruction:\n"); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * The software interrupt instruction (SWI) is used for entering - * Supervisor mode, usually to request a particular supervisor - * function. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_swi(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("software interrupt:\n"); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during an instruction prefetch. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("prefetch abort:\n"); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during a data access. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("data abort:"); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * Normally, system will never reach here - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("reserved trap:\n"); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -#define GIC_ACK_INTID_MASK 0x000003ff - -void rt_hw_trap_irq(void) -{ - void *param; - unsigned long ir; - unsigned long fullir; - rt_isr_handler_t isr_func; - extern struct rt_irq_desc isr_table[]; - - fullir = arm_gic_get_active_irq(0); - ir = fullir & GIC_ACK_INTID_MASK; - - if (ir == 1023) - { - /* Spurious interrupt */ - return; - } - - /* get interrupt service routine */ - isr_func = isr_table[ir].handler; -#ifdef RT_USING_INTERRUPT_INFO - isr_table[ir].counter++; -#endif - if (isr_func) - { - /* Interrupt for myself. */ - param = isr_table[ir].param; - /* turn to interrupt service routine */ - isr_func(ir, param); - } -#ifdef RT_USING_VMM - else - { - /* We have to EOI before masking the interrupts */ - arm_gic_ack(0, fullir); - vmm_virq_pending(ir); - return; - } -#endif - - /* end of interrupt */ - arm_gic_ack(0, fullir); -} - -void rt_hw_trap_fiq(void) -{ - void *param; - unsigned long ir; - unsigned long fullir; - rt_isr_handler_t isr_func; - extern struct rt_irq_desc isr_table[]; - - fullir = arm_gic_get_active_irq(0); - ir = fullir & GIC_ACK_INTID_MASK; - - /* get interrupt service routine */ - isr_func = isr_table[ir].handler; - param = isr_table[ir].param; - - /* turn to interrupt service routine */ - isr_func(ir, param); - - /* end of interrupt */ - arm_gic_ack(0, fullir); -} - diff --git a/rt-thread/libcpu/arm/realview-a8-vmm/vector_gcc.S b/rt-thread/libcpu/arm/realview-a8-vmm/vector_gcc.S deleted file mode 100644 index 46fdf29..0000000 --- a/rt-thread/libcpu/arm/realview-a8-vmm/vector_gcc.S +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - */ -#include - -.section .vectors, "ax" -.code 32 - -.globl system_vectors -system_vectors: - ldr pc, _vector_reset - ldr pc, _vector_undef - ldr pc, _vector_swi - ldr pc, _vector_pabt - ldr pc, _vector_dabt - ldr pc, _vector_resv - ldr pc, _vector_irq - ldr pc, _vector_fiq - -.globl _reset -.globl vector_undef -.globl vector_swi -.globl vector_pabt -.globl vector_dabt -.globl vector_resv -.globl vector_irq -.globl vector_fiq - -_vector_reset: - .word _reset -_vector_undef: - .word vector_undef -_vector_swi: - .word vector_swi -_vector_pabt: - .word vector_pabt -_vector_dabt: - .word vector_dabt -_vector_resv: - .word vector_resv -_vector_irq: - .word vector_irq -_vector_fiq: - .word vector_fiq - -.balignl 16,0xdeadbeef diff --git a/rt-thread/libcpu/arm/s3c24x0/SConscript b/rt-thread/libcpu/arm/s3c24x0/SConscript deleted file mode 100644 index b259a94..0000000 --- a/rt-thread/libcpu/arm/s3c24x0/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/s3c24x0/context_gcc.S b/rt-thread/libcpu/arm/s3c24x0/context_gcc.S deleted file mode 100644 index c737abe..0000000 --- a/rt-thread/libcpu/arm/s3c24x0/context_gcc.S +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-09-06 XuXinming first version - */ - -/*! - * \addtogroup S3C24X0 - */ -/*@{*/ - -#define NOINT 0xc0 - -/* - * rt_base_t rt_hw_interrupt_disable(); - */ -.globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mrs r0, cpsr - orr r1, r0, #NOINT - msr cpsr_c, r1 - mov pc, lr - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ -.globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - msr cpsr, r0 - mov pc, lr - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to - */ -.globl rt_hw_context_switch -rt_hw_context_switch: - stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) - stmfd sp!, {r0-r12, lr} @ push lr & register file - - mrs r4, cpsr - stmfd sp!, {r4} @ push cpsr - mrs r4, spsr - stmfd sp!, {r4} @ push spsr - - str sp, [r0] @ store sp in preempted tasks TCB - ldr sp, [r1] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - ldmfd sp!, {r4} @ pop new task cpsr - msr spsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to - */ -.globl rt_hw_context_switch_to -rt_hw_context_switch_to: - ldr sp, [r0] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - ldmfd sp!, {r4} @ pop new task cpsr - msr cpsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc} @ pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - */ -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -.globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - ldr r2, =rt_thread_switch_interrupt_flag - ldr r3, [r2] - cmp r3, #1 - beq _reswitch - mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 - str r3, [r2] - ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread - str r0, [r2] -_reswitch: - ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread - str r1, [r2] - mov pc, lr diff --git a/rt-thread/libcpu/arm/s3c24x0/context_rvds.S b/rt-thread/libcpu/arm/s3c24x0/context_rvds.S deleted file mode 100644 index f34f912..0000000 --- a/rt-thread/libcpu/arm/s3c24x0/context_rvds.S +++ /dev/null @@ -1,103 +0,0 @@ -;/* -; * Copyright (c) 2006-2022, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2009-01-20 Bernard first version -; */ - -NOINT EQU 0xc0 ; disable interrupt in psr - - AREA |.text|, CODE, READONLY, ALIGN=2 - ARM - REQUIRE8 - PRESERVE8 - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ -rt_hw_interrupt_disable PROC - EXPORT rt_hw_interrupt_disable - MRS r0, cpsr - ORR r1, r0, #NOINT - MSR cpsr_c, r1 - BX lr - ENDP - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ -rt_hw_interrupt_enable PROC - EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0 - BX lr - ENDP - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ -rt_hw_context_switch PROC - EXPORT rt_hw_context_switch - STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC) - STMFD sp!, {r0-r12, lr} ; push lr & register file - - MRS r4, cpsr - STMFD sp!, {r4} ; push cpsr - MRS r4, spsr - STMFD sp!, {r4} ; push spsr - - STR sp, [r0] ; store sp in preempted tasks TCB - LDR sp, [r1] ; get new task stack pointer - - LDMFD sp!, {r4} ; pop new task spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task cpsr - MSR spsr_cxsf, r4 - - LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc - ENDP - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; */ -rt_hw_context_switch_to PROC - EXPORT rt_hw_context_switch_to - LDR sp, [r0] ; get new task stack pointer - - LDMFD sp!, {r4} ; pop new task spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task cpsr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP - -;/* -; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); -; */ - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -rt_hw_context_switch_interrupt PROC - EXPORT rt_hw_context_switch_interrupt - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1 - STR r3, [r2] - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - BX lr - ENDP - - END diff --git a/rt-thread/libcpu/arm/s3c24x0/cpu.c b/rt-thread/libcpu/arm/s3c24x0/cpu.c deleted file mode 100644 index 06db937..0000000 --- a/rt-thread/libcpu/arm/s3c24x0/cpu.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - */ - -#include -#include -#include "s3c24x0.h" - -/** - * @addtogroup S3C24X0 - */ -/*@{*/ - -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) - -#ifdef __GNUC__ -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); -} -#endif - -#ifdef __CC_ARM -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - __asm - { - mrc p15, 0, i, c1, c0, 0 - } - - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } -} -#endif - -/** - * enable I-Cache - * - */ -void rt_hw_cpu_icache_enable() -{ - cache_enable(ICACHE_MASK); -} - -/** - * disable I-Cache - * - */ -void rt_hw_cpu_icache_disable() -{ - cache_disable(ICACHE_MASK); -} - -/** - * return the status of I-Cache - * - */ -rt_base_t rt_hw_cpu_icache_status() -{ - return (cp15_rd() & ICACHE_MASK); -} - -/** - * enable D-Cache - * - */ -void rt_hw_cpu_dcache_enable() -{ - cache_enable(DCACHE_MASK); -} - -/** - * disable D-Cache - * - */ -void rt_hw_cpu_dcache_disable() -{ - cache_disable(DCACHE_MASK); -} - -/** - * return the status of D-Cache - * - */ -rt_base_t rt_hw_cpu_dcache_status() -{ - return (cp15_rd() & DCACHE_MASK); -} - -/** - * reset cpu by dog's time-out - * - */ -RT_WEAK void rt_hw_cpu_reset() -{ - /* Disable all interrupt except the WDT */ - INTMSK = (~((rt_uint32_t)1 << INTWDT)); - - /* Disable watchdog */ - WTCON = 0x0000; - - /* Initialize watchdog timer count register */ - WTCNT = 0x0001; - - /* Enable watchdog timer; assert reset at timer timeout */ - WTCON = 0x0021; - - while(1); /* loop forever and wait for reset to happen */ - - /* NEVER REACHED */ -} - -/** - * shutdown CPU - * - */ -RT_WEAK void rt_hw_cpu_shutdown() -{ - rt_base_t level; - rt_kprintf("shutdown...\n"); - - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/s3c24x0/interrupt.c b/rt-thread/libcpu/arm/s3c24x0/interrupt.c deleted file mode 100644 index c985fc7..0000000 --- a/rt-thread/libcpu/arm/s3c24x0/interrupt.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - * 2013-03-29 aozima Modify the interrupt interface implementations. - */ - -#include -#include -#include "s3c24x0.h" - -#define MAX_HANDLERS 32 - -extern rt_uint32_t rt_interrupt_nest; - -/* exception and interrupt handler table */ -struct rt_irq_desc isr_table[MAX_HANDLERS]; -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -/** - * @addtogroup S3C24X0 - */ -/*@{*/ - -static void rt_hw_interrupt_handle(int vector, void *param) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - register rt_uint32_t idx; - - /* all clear source pending */ - SRCPND = 0x0; - - /* all clear sub source pending */ - SUBSRCPND = 0x0; - - /* all=IRQ mode */ - INTMOD = 0x0; - - /* all interrupt disabled include global bit */ - INTMSK = BIT_ALLMSK; - - /* all sub interrupt disable */ - INTSUBMSK = BIT_SUB_ALLMSK; - - /* all clear interrupt pending */ - INTPND = BIT_ALLMSK; - - /* init exceptions table */ - rt_memset(isr_table, 0x00, sizeof(isr_table)); - for(idx=0; idx < MAX_HANDLERS; idx++) - { - isr_table[idx].handler = rt_hw_interrupt_handle; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - INTMSK |= 1 << vector; -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - if (vector == INTNOTUSED6) - { - rt_kprintf("Interrupt vec %d is not used!\n", vector); - // while(1); - } - else if (vector == INTGLOBAL) - INTMSK = 0x0; - else - INTMSK &= ~(1 << vector); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param new_handler the interrupt service routine to be installed - * @param old_handler the old interrupt service routine - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if(vector < MAX_HANDLERS) - { - old_handler = isr_table[vector].handler; - - if (handler != RT_NULL) - { -#ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); -#endif /* RT_USING_INTERRUPT_INFO */ - isr_table[vector].handler = handler; - isr_table[vector].param = param; - } - } - - return old_handler; -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/s3c24x0/mmu.c b/rt-thread/libcpu/arm/s3c24x0/mmu.c deleted file mode 100644 index 4e5ef8d..0000000 --- a/rt-thread/libcpu/arm/s3c24x0/mmu.c +++ /dev/null @@ -1,390 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2008-04-25 Yi.qiu first version - * 2009-12-18 Bernard port to armcc - */ - -#include -#include "s3c24x0.h" - -#define _MMUTT_STARTADDRESS 0x33FF0000 - -#define DESC_SEC (0x2|(1<<4)) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO - -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) - -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) - -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) - -#ifdef __GNUC__ -void mmu_setttbase(register rt_uint32_t i) -{ - asm volatile ("mcr p15, 0, %0, c2, c0, 0": :"r" (i)); -} - -void mmu_set_domain(register rt_uint32_t i) -{ - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); -} - -void mmu_enable() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= 0x1; - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~0x1; - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_enable_icache() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= (1 << 12); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_enable_dcache() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= (1 << 2); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable_icache() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~(1 << 12); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable_dcache() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~(1 << 2); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_enable_alignfault() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i |= (1 << 1); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_disable_alignfault() -{ - register rt_uint32_t i; - - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - i &= ~(1 << 1); - - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void mmu_clean_invalidated_cache_index(int index) -{ - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); -} - -void mmu_invalidate_tlb() -{ - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); -} - -void mmu_invalidate_icache() -{ - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); -} -#endif - -#ifdef __CC_ARM -void mmu_setttbase(rt_uint32_t i) -{ - __asm volatile - { - mcr p15, 0, i, c2, c0, 0 - } -} - -void mmu_set_domain(rt_uint32_t i) -{ - __asm volatile - { - mcr p15,0, i, c3, c0, 0 - } -} - -void mmu_enable() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_enable_icache() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_enable_dcache() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable_icache() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable_dcache() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_enable_alignfault() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_disable_alignfault() -{ - register rt_uint32_t value; - - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } -} - -void mmu_clean_invalidated_cache_index(int index) -{ - __asm volatile - { - mcr p15, 0, index, c7, c14, 2 - } -} - -void mmu_invalidate_tlb() -{ - register rt_uint32_t value; - - value = 0; - __asm volatile - { - mcr p15, 0, value, c8, c7, 0 - } -} - -void mmu_invalidate_icache() -{ - register rt_uint32_t value; - - value = 0; - - __asm volatile - { - mcr p15, 0, value, c7, c5, 0 - } -} -#endif - -void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr) -{ - volatile rt_uint32_t *pTT; - volatile int i,nSec; - pTT=(rt_uint32_t *)_MMUTT_STARTADDRESS+(vaddrStart>>20); - nSec=(vaddrEnd>>20)-(vaddrStart>>20); - for(i=0;i<=nSec;i++) - { - *pTT = attr |(((paddrStart>>20)+i)<<20); - pTT++; - } -} - -void rt_hw_mmu_init(void) -{ - int i,j; - //========================== IMPORTANT NOTE ========================= - //The current stack and code area can't be re-mapped in this routine. - //If you want memory map mapped freely, your own sophiscated mmu - //initialization code is needed. - //=================================================================== - - mmu_disable_dcache(); - mmu_disable_icache(); - - //If write-back is used,the DCache should be cleared. - for(i=0;i<64;i++) - for(j=0;j<8;j++) - mmu_clean_invalidated_cache_index((i<<26)|(j<<5)); - - mmu_invalidate_icache(); - - //To complete mmu_Init() fast, Icache may be turned on here. - mmu_enable_icache(); - - mmu_disable(); - mmu_invalidate_tlb(); - - //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr); - mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0 - mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0 - mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0 - mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1 - mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2 - mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3 - //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4 - mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000 - mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5 - //30f00000->30100000, 31000000->30200000 - mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1 - mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2 - - mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3 - mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7 - - mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR - mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR - mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR - mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used - mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR - - mmu_setttbase(_MMUTT_STARTADDRESS); - - /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */ - mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); - - mmu_enable_alignfault(); - - mmu_enable(); - - /* ICache enable */ - mmu_enable_icache(); - /* DCache should be turned on after mmu is turned on. */ - mmu_enable_dcache(); -} - diff --git a/rt-thread/libcpu/arm/s3c24x0/rtc.c b/rt-thread/libcpu/arm/s3c24x0/rtc.c deleted file mode 100644 index b7bbba9..0000000 --- a/rt-thread/libcpu/arm/s3c24x0/rtc.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-04-26 yi.qiu first version - * 2010-03-18 Gary Lee add functions such as GregorianDay - * and rtc_time_to_tm - * 2009-03-20 yi.qiu clean up - */ - -#include -#include -#include -#include - -// #define RTC_DEBUG -#ifdef RT_USING_RTC -#define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */ -#define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */ -#define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F)) -#define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10)) - -/** - * This function get rtc time - */ -void rt_hw_rtc_get(struct tm *ti) -{ - rt_uint8_t sec, min, hour, mday, wday, mon, year; - - /* enable access to RTC registers */ - RTCCON |= RTC_ENABLE; - - /* read RTC registers */ - do - { - sec = BCDSEC; - min = BCDMIN; - hour = BCDHOUR; - mday = BCDDATE; - wday = BCDDAY; - mon = BCDMON; - year = BCDYEAR; - } while (sec != BCDSEC); - -#ifdef RTC_DEBUG - rt_kprintf("sec:%x min:%x hour:%x mday:%x wday:%x mon:%x year:%x\n", - sec, min, hour, mday, wday, mon, year); -#endif - - /* disable access to RTC registers */ - RTC_DISABLE - - ti->tm_sec = BCD2BIN(sec & 0x7F); - ti->tm_min = BCD2BIN(min & 0x7F); - ti->tm_hour = BCD2BIN(hour & 0x3F); - ti->tm_mday = BCD2BIN(mday & 0x3F); - ti->tm_mon = BCD2BIN(mon & 0x1F); - ti->tm_year = BCD2BIN(year); - ti->tm_wday = BCD2BIN(wday & 0x07); - ti->tm_yday = 0; - ti->tm_isdst = 0; -} - -/** - * This function set rtc time - */ -void rt_hw_rtc_set(struct tm *ti) -{ - rt_uint8_t sec, min, hour, mday, wday, mon, year; - - year = BIN2BCD(ti->tm_year); - mon = BIN2BCD(ti->tm_mon); - wday = BIN2BCD(ti->tm_wday); - mday = BIN2BCD(ti->tm_mday); - hour = BIN2BCD(ti->tm_hour); - min = BIN2BCD(ti->tm_min); - sec = BIN2BCD(ti->tm_sec); - - /* enable access to RTC registers */ - RTC_ENABLE - - do{ - /* write RTC registers */ - BCDSEC = sec; - BCDMIN = min; - BCDHOUR = hour; - BCDDATE = mday; - BCDDAY = wday; - BCDMON = mon; - BCDYEAR = year; - }while (sec != BCDSEC); - - /* disable access to RTC registers */ - RTC_DISABLE -} - -/** - * This function reset rtc - */ -void rt_hw_rtc_reset (void) -{ - RTCCON = (RTCCON & ~0x06) | 0x08; - RTCCON &= ~(0x08|0x01); -} - -static struct rt_device rtc; -static rt_err_t rtc_open(rt_device_t dev, rt_uint16_t oflag) -{ - RTC_ENABLE - return RT_EOK; -} - -static rt_err_t rtc_close(rt_device_t dev) -{ - RTC_DISABLE - return RT_EOK; -} - -static rt_size_t rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - return RT_EOK; -} - -static rt_err_t rtc_control(rt_device_t dev, int cmd, void *args) -{ - struct tm tmp; - time_t *time; - RT_ASSERT(dev != RT_NULL); - - time = (time_t *)args; - switch (cmd) - { - case RT_DEVICE_CTRL_RTC_GET_TIME: - /* read device */ - rt_hw_rtc_get(&tmp); - *((rt_time_t *)args) = timegm(&tmp); - break; - - case RT_DEVICE_CTRL_RTC_SET_TIME: - /* write device */ - gmtime_r(time, &tmp); - rt_hw_rtc_set(&tmp); - break; - } - - return RT_EOK; -} - -void rt_hw_rtc_init(void) -{ - rtc.type = RT_Device_Class_RTC; - - /* register rtc device */ - rtc.init = RT_NULL; - rtc.open = rtc_open; - rtc.close = rtc_close; - rtc.read = rtc_read; - rtc.write = RT_NULL; - rtc.control = rtc_control; - - /* no private */ - rtc.user_data = RT_NULL; - - rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); -} - -#ifdef RT_USING_FINSH -#include -void list_date() -{ - time_t time; - rt_device_t device; - - device = rt_device_find("rtc"); - if (device != RT_NULL) - { - rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time); - - rt_kprintf("%d, %s\n", time, ctime(&time)); - } -} -FINSH_FUNCTION_EXPORT(list_date, list date); -#endif -#endif diff --git a/rt-thread/libcpu/arm/s3c24x0/rtc.h b/rt-thread/libcpu/arm/s3c24x0/rtc.h deleted file mode 100644 index 7821932..0000000 --- a/rt-thread/libcpu/arm/s3c24x0/rtc.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-20 yi.qiu the first version - */ - -#ifndef __RTC_H__ -#define __RTC_H__ - -void rt_hw_rtc_init(void); - -#endif - diff --git a/rt-thread/libcpu/arm/s3c24x0/s3c24x0.h b/rt-thread/libcpu/arm/s3c24x0/s3c24x0.h deleted file mode 100644 index 75e1eb0..0000000 --- a/rt-thread/libcpu/arm/s3c24x0/s3c24x0.h +++ /dev/null @@ -1,607 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-12-11 Bernard first version - */ - -#ifndef __S3C24X0_H__ -#define __S3C24X0_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - * @addtogroup S3C24X0 - */ -/*@{*/ - -// Memory control -#define BWSCON (*(volatile unsigned *)0x48000000) //Bus width & wait status -#define BANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control -#define BANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control -#define BANKCON2 (*(volatile unsigned *)0x4800000c) //BANK2 cControl -#define BANKCON3 (*(volatile unsigned *)0x48000010) //BANK3 control -#define BANKCON4 (*(volatile unsigned *)0x48000014) //BANK4 control -#define BANKCON5 (*(volatile unsigned *)0x48000018) //BANK5 control -#define BANKCON6 (*(volatile unsigned *)0x4800001c) //BANK6 control -#define BANKCON7 (*(volatile unsigned *)0x48000020) //BANK7 control -#define REFRESH (*(volatile unsigned *)0x48000024) //DRAM/SDRAM efresh -#define BANKSIZE (*(volatile unsigned *)0x48000028) //Flexible Bank Size -#define MRSRB6 (*(volatile unsigned *)0x4800002c) //Mode egister set for SDRAM -#define MRSRB7 (*(volatile unsigned *)0x48000030) //Mode egister set for SDRAM - - -// USB Host - - -// INTERRUPT -#define SRCPND (*(volatile unsigned *)0x4a000000) //Interrupt request status -#define INTMOD (*(volatile unsigned *)0x4a000004) //Interrupt mode control -#define INTMSK (*(volatile unsigned *)0x4a000008) //Interrupt mask control -#define PRIORITY (*(volatile unsigned *)0x4a00000c) //IRQ priority control -#define INTPND (*(volatile unsigned *)0x4a000010) //Interrupt request status -#define INTOFFSET (*(volatile unsigned *)0x4a000014) //Interruot request source offset -#define SUBSRCPND (*(volatile unsigned *)0x4a000018) //Sub source pending -#define INTSUBMSK (*(volatile unsigned *)0x4a00001c) //Interrupt sub mask - - -// DMA -#define DISRC0 (*(volatile unsigned *)0x4b000000) //DMA 0 Initial source -#define DISRCC0 (*(volatile unsigned *)0x4b000004) //DMA 0 Initial source control -#define DIDST0 (*(volatile unsigned *)0x4b000008) //DMA 0 Initial Destination -#define DIDSTC0 (*(volatile unsigned *)0x4b00000c) //DMA 0 Initial Destination control -#define DCON0 (*(volatile unsigned *)0x4b000010) //DMA 0 Control -#define DSTAT0 (*(volatile unsigned *)0x4b000014) //DMA 0 Status -#define DCSRC0 (*(volatile unsigned *)0x4b000018) //DMA 0 Current source -#define DCDST0 (*(volatile unsigned *)0x4b00001c) //DMA 0 Current destination -#define DMASKTRIG0 (*(volatile unsigned *)0x4b000020) //DMA 0 Mask trigger - -#define DISRC1 (*(volatile unsigned *)0x4b000040) //DMA 1 Initial source -#define DISRCC1 (*(volatile unsigned *)0x4b000044) //DMA 1 Initial source control -#define DIDST1 (*(volatile unsigned *)0x4b000048) //DMA 1 Initial Destination -#define DIDSTC1 (*(volatile unsigned *)0x4b00004c) //DMA 1 Initial Destination control -#define DCON1 (*(volatile unsigned *)0x4b000050) //DMA 1 Control -#define DSTAT1 (*(volatile unsigned *)0x4b000054) //DMA 1 Status -#define DCSRC1 (*(volatile unsigned *)0x4b000058) //DMA 1 Current source -#define DCDST1 (*(volatile unsigned *)0x4b00005c) //DMA 1 Current destination -#define DMASKTRIG1 (*(volatile unsigned *)0x4b000060) //DMA 1 Mask trigger - -#define DISRC2 (*(volatile unsigned *)0x4b000080) //DMA 2 Initial source -#define DISRCC2 (*(volatile unsigned *)0x4b000084) //DMA 2 Initial source control -#define DIDST2 (*(volatile unsigned *)0x4b000088) //DMA 2 Initial Destination -#define DIDSTC2 (*(volatile unsigned *)0x4b00008c) //DMA 2 Initial Destination control -#define DCON2 (*(volatile unsigned *)0x4b000090) //DMA 2 Control -#define DSTAT2 (*(volatile unsigned *)0x4b000094) //DMA 2 Status -#define DCSRC2 (*(volatile unsigned *)0x4b000098) //DMA 2 Current source -#define DCDST2 (*(volatile unsigned *)0x4b00009c) //DMA 2 Current destination -#define DMASKTRIG2 (*(volatile unsigned *)0x4b0000a0) //DMA 2 Mask trigger - -#define DISRC3 (*(volatile unsigned *)0x4b0000c0) //DMA 3 Initial source -#define DISRCC3 (*(volatile unsigned *)0x4b0000c4) //DMA 3 Initial source control -#define DIDST3 (*(volatile unsigned *)0x4b0000c8) //DMA 3 Initial Destination -#define DIDSTC3 (*(volatile unsigned *)0x4b0000cc) //DMA 3 Initial Destination control -#define DCON3 (*(volatile unsigned *)0x4b0000d0) //DMA 3 Control -#define DSTAT3 (*(volatile unsigned *)0x4b0000d4) //DMA 3 Status -#define DCSRC3 (*(volatile unsigned *)0x4b0000d8) //DMA 3 Current source -#define DCDST3 (*(volatile unsigned *)0x4b0000dc) //DMA 3 Current destination -#define DMASKTRIG3 (*(volatile unsigned *)0x4b0000e0) //DMA 3 Mask trigger - - -// CLOCK & POWER MANAGEMENT -#define LOCKTIME (*(volatile unsigned *)0x4c000000) //PLL lock time counter -#define MPLLCON (*(volatile unsigned *)0x4c000004) //MPLL Control -#define UPLLCON (*(volatile unsigned *)0x4c000008) //UPLL Control -#define CLKCON (*(volatile unsigned *)0x4c00000c) //Clock generator control -#define CLKSLOW (*(volatile unsigned *)0x4c000010) //Slow clock control -#define CLKDIVN (*(volatile unsigned *)0x4c000014) //Clock divider control -#define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control - - -// LCD CONTROLLER -#define LCDCON1 (*(volatile unsigned *)0x4d000000) //LCD control 1 -#define LCDCON2 (*(volatile unsigned *)0x4d000004) //LCD control 2 -#define LCDCON3 (*(volatile unsigned *)0x4d000008) //LCD control 3 -#define LCDCON4 (*(volatile unsigned *)0x4d00000c) //LCD control 4 -#define LCDCON5 (*(volatile unsigned *)0x4d000010) //LCD control 5 -#define LCDSADDR1 (*(volatile unsigned *)0x4d000014) //STN/TFT Frame buffer start address 1 -#define LCDSADDR2 (*(volatile unsigned *)0x4d000018) //STN/TFT Frame buffer start address 2 -#define LCDSADDR3 (*(volatile unsigned *)0x4d00001c) //STN/TFT Virtual screen address set -#define REDLUT (*(volatile unsigned *)0x4d000020) //STN Red lookup table -#define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table -#define BLUELUT (*(volatile unsigned *)0x4d000028) //STN Blue lookup table -#define DITHMODE (*(volatile unsigned *)0x4d00004c) //STN Dithering mode -#define TPAL (*(volatile unsigned *)0x4d000050) //TFT Temporary palette -#define LCDINTPND (*(volatile unsigned *)0x4d000054) //LCD Interrupt pending -#define LCDSRCPND (*(volatile unsigned *)0x4d000058) //LCD Interrupt source -#define LCDINTMSK (*(volatile unsigned *)0x4d00005c) //LCD Interrupt mask -#define LPCSEL (*(volatile unsigned *)0x4d000060) //LPC3600 Control -#define PALETTE 0x4d000400 //Palette start address - - -// NAND flash -#define NFCONF (*(volatile unsigned *)0x4e000000) //NAND Flash configuration -#define NFCMD (*(volatile unsigned *)0x4e000004) //NADD Flash command -#define NFADDR (*(volatile unsigned *)0x4e000008) //NAND Flash address -#define NFDATA (*(volatile unsigned *)0x4e00000c) //NAND Flash data -#define NFSTAT (*(volatile unsigned *)0x4e000010) //NAND Flash operation status -#define NFECC (*(volatile unsigned *)0x4e000014) //NAND Flash ECC -#define NFECC0 (*(volatile unsigned *)0x4e000014) -#define NFECC1 (*(volatile unsigned *)0x4e000015) -#define NFECC2 (*(volatile unsigned *)0x4e000016) - -// UART -#define U0BASE (*(volatile unsigned *)0x50000000) //UART 0 Line control -#define ULCON0 (*(volatile unsigned *)0x50000000) //UART 0 Line control -#define UCON0 (*(volatile unsigned *)0x50000004) //UART 0 Control -#define UFCON0 (*(volatile unsigned *)0x50000008) //UART 0 FIFO control -#define UMCON0 (*(volatile unsigned *)0x5000000c) //UART 0 Modem control -#define USTAT0 (*(volatile unsigned *)0x50000010) //UART 0 Tx/Rx status -#define URXB0 (*(volatile unsigned *)0x50000014) //UART 0 Rx error status -#define UFSTAT0 (*(volatile unsigned *)0x50000018) //UART 0 FIFO status -#define UMSTAT0 (*(volatile unsigned *)0x5000001c) //UART 0 Modem status -#define UBRD0 (*(volatile unsigned *)0x50000028) //UART 0 Baud ate divisor - -#define U1BASE (*(volatile unsigned *)0x50004000) //UART 1 Line control -#define ULCON1 (*(volatile unsigned *)0x50004000) //UART 1 Line control -#define UCON1 (*(volatile unsigned *)0x50004004) //UART 1 Control -#define UFCON1 (*(volatile unsigned *)0x50004008) //UART 1 FIFO control -#define UMCON1 (*(volatile unsigned *)0x5000400c) //UART 1 Modem control -#define USTAT1 (*(volatile unsigned *)0x50004010) //UART 1 Tx/Rx status -#define URXB1 (*(volatile unsigned *)0x50004014) //UART 1 Rx error status -#define UFSTAT1 (*(volatile unsigned *)0x50004018) //UART 1 FIFO status -#define UMSTAT1 (*(volatile unsigned *)0x5000401c) //UART 1 Modem status -#define UBRD1 (*(volatile unsigned *)0x50004028) //UART 1 Baud ate divisor - -#define U2BASE *(volatile unsigned *)0x50008000 //UART 2 Line control -#define ULCON2 (*(volatile unsigned *)0x50008000) //UART 2 Line control -#define UCON2 (*(volatile unsigned *)0x50008004) //UART 2 Control -#define UFCON2 (*(volatile unsigned *)0x50008008) //UART 2 FIFO control -#define UMCON2 (*(volatile unsigned *)0x5000800c) //UART 2 Modem control -#define USTAT2 (*(volatile unsigned *)0x50008010) //UART 2 Tx/Rx status -#define URXB2 (*(volatile unsigned *)0x50008014) //UART 2 Rx error status -#define UFSTAT2 (*(volatile unsigned *)0x50008018) //UART 2 FIFO status -#define UMSTAT2 (*(volatile unsigned *)0x5000801c) //UART 2 Modem status -#define UBRD2 (*(volatile unsigned *)0x50008028) //UART 2 Baud ate divisor - -#ifdef __BIG_ENDIAN -#define UTXH0 (*(volatile unsigned char *)0x50000023) //UART 0 Transmission Hold -#define URXH0 (*(volatile unsigned char *)0x50000027) //UART 0 Receive buffer -#define UTXH1 (*(volatile unsigned char *)0x50004023) //UART 1 Transmission Hold -#define URXH1 (*(volatile unsigned char *)0x50004027) //UART 1 Receive buffer -#define UTXH2 (*(volatile unsigned char *)0x50008023) //UART 2 Transmission Hold -#define URXH2 (*(volatile unsigned char *)0x50008027) //UART 2 Receive buffer - -#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch) -#define RdURXH0() (*(volatile unsigned char *)0x50000027) -#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch) -#define RdURXH1() (*(volatile unsigned char *)0x50004027) -#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch) -#define RdURXH2() (*(volatile unsigned char *)0x50008027) - -#else //Little Endian -#define UTXH0 (*(volatile unsigned char *)0x50000020) //UART 0 Transmission Hold -#define URXH0 (*(volatile unsigned char *)0x50000024) //UART 0 Receive buffer -#define UTXH1 (*(volatile unsigned char *)0x50004020) //UART 1 Transmission Hold -#define URXH1 (*(volatile unsigned char *)0x50004024) //UART 1 Receive buffer -#define UTXH2 (*(volatile unsigned char *)0x50008020) //UART 2 Transmission Hold -#define URXH2 (*(volatile unsigned char *)0x50008024) //UART 2 Receive buffer - -#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch) -#define RdURXH0() (*(volatile unsigned char *)0x50000024) -#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch) -#define RdURXH1() (*(volatile unsigned char *)0x50004024) -#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch) -#define RdURXH2() (*(volatile unsigned char *)0x50008024) - -#endif - - -// PWM TIMER -#define TCFG0 (*(volatile unsigned *)0x51000000) //Timer 0 configuration -#define TCFG1 (*(volatile unsigned *)0x51000004) //Timer 1 configuration -#define TCON (*(volatile unsigned *)0x51000008) //Timer control -#define TCNTB0 (*(volatile unsigned *)0x5100000c) //Timer count buffer 0 -#define TCMPB0 (*(volatile unsigned *)0x51000010) //Timer compare buffer 0 -#define TCNTO0 (*(volatile unsigned *)0x51000014) //Timer count observation 0 -#define TCNTB1 (*(volatile unsigned *)0x51000018) //Timer count buffer 1 -#define TCMPB1 (*(volatile unsigned *)0x5100001c) //Timer compare buffer 1 -#define TCNTO1 (*(volatile unsigned *)0x51000020) //Timer count observation 1 -#define TCNTB2 (*(volatile unsigned *)0x51000024) //Timer count buffer 2 -#define TCMPB2 (*(volatile unsigned *)0x51000028) //Timer compare buffer 2 -#define TCNTO2 (*(volatile unsigned *)0x5100002c) //Timer count observation 2 -#define TCNTB3 (*(volatile unsigned *)0x51000030) //Timer count buffer 3 -#define TCMPB3 (*(volatile unsigned *)0x51000034) //Timer compare buffer 3 -#define TCNTO3 (*(volatile unsigned *)0x51000038) //Timer count observation 3 -#define TCNTB4 (*(volatile unsigned *)0x5100003c) //Timer count buffer 4 -#define TCNTO4 (*(volatile unsigned *)0x51000040) //Timer count observation 4 - -// Added for 2440 -#define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only) -#define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0 -#define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1 -#define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register - - -// USB DEVICE -#ifdef __BIG_ENDIAN -#define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000143) //Function address -#define PWR_REG (*(volatile unsigned char *)0x52000147) //Power management -#define EP_INT_REG (*(volatile unsigned char *)0x5200014b) //EP Interrupt pending and clear -#define USB_INT_REG (*(volatile unsigned char *)0x5200015b) //USB Interrupt pending and clear -#define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015f) //Interrupt enable -#define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016f) -#define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000173) //Frame number lower byte -#define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000177) //Frame number higher byte -#define INDEX_REG (*(volatile unsigned char *)0x5200017b) //Register index -#define MAXP_REG (*(volatile unsigned char *)0x52000183) //Endpoint max packet -#define EP0_CSR (*(volatile unsigned char *)0x52000187) //Endpoint 0 status -#define IN_CSR1_REG (*(volatile unsigned char *)0x52000187) //In endpoint control status -#define IN_CSR2_REG (*(volatile unsigned char *)0x5200018b) -#define OUT_CSR1_REG (*(volatile unsigned char *)0x52000193) //Out endpoint control status -#define OUT_CSR2_REG (*(volatile unsigned char *)0x52000197) -#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019b) //Endpoint out write count -#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019f) -#define EP0_FIFO (*(volatile unsigned char *)0x520001c3) //Endpoint 0 FIFO -#define EP1_FIFO (*(volatile unsigned char *)0x520001c7) //Endpoint 1 FIFO -#define EP2_FIFO (*(volatile unsigned char *)0x520001cb) //Endpoint 2 FIFO -#define EP3_FIFO (*(volatile unsigned char *)0x520001cf) //Endpoint 3 FIFO -#define EP4_FIFO (*(volatile unsigned char *)0x520001d3) //Endpoint 4 FIFO -#define EP1_DMA_CON (*(volatile unsigned char *)0x52000203) //EP1 DMA interface control -#define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000207) //EP1 DMA Tx unit counter -#define EP1_DMA_FIFO (*(volatile unsigned char *)0x5200020b) //EP1 DMA Tx FIFO counter -#define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020f) //EP1 DMA total Tx counter -#define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000213) -#define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000217) -#define EP2_DMA_CON (*(volatile unsigned char *)0x5200021b) //EP2 DMA interface control -#define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021f) //EP2 DMA Tx unit counter -#define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000223) //EP2 DMA Tx FIFO counter -#define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000227) //EP2 DMA total Tx counter -#define EP2_DMA_TTC_M (*(volatile unsigned char *)0x5200022b) -#define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022f) -#define EP3_DMA_CON (*(volatile unsigned char *)0x52000243) //EP3 DMA interface control -#define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000247) //EP3 DMA Tx unit counter -#define EP3_DMA_FIFO (*(volatile unsigned char *)0x5200024b) //EP3 DMA Tx FIFO counter -#define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024f) //EP3 DMA total Tx counter -#define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000253) -#define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000257) -#define EP4_DMA_CON (*(volatile unsigned char *)0x5200025b) //EP4 DMA interface control -#define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025f) //EP4 DMA Tx unit counter -#define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000263) //EP4 DMA Tx FIFO counter -#define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000267) //EP4 DMA total Tx counter -#define EP4_DMA_TTC_M (*(volatile unsigned char *)0x5200026b) -#define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026f) - -#else // Little Endian -#define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) //Function address -#define PWR_REG (*(volatile unsigned char *)0x52000144) //Power management -#define EP_INT_REG (*(volatile unsigned char *)0x52000148) //EP Interrupt pending and clear -#define USB_INT_REG (*(volatile unsigned char *)0x52000158) //USB Interrupt pending and clear -#define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015c) //Interrupt enable -#define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016c) -#define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) //Frame number lower byte -#define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) //Frame number higher byte -#define INDEX_REG (*(volatile unsigned char *)0x52000178) //Register index -#define MAXP_REG (*(volatile unsigned char *)0x52000180) //Endpoint max packet -#define EP0_CSR (*(volatile unsigned char *)0x52000184) //Endpoint 0 status -#define IN_CSR1_REG (*(volatile unsigned char *)0x52000184) //In endpoint control status -#define IN_CSR2_REG (*(volatile unsigned char *)0x52000188) -#define OUT_CSR1_REG (*(volatile unsigned char *)0x52000190) //Out endpoint control status -#define OUT_CSR2_REG (*(volatile unsigned char *)0x52000194) -#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) //Endpoint out write count -#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019c) -#define EP0_FIFO (*(volatile unsigned char *)0x520001c0) //Endpoint 0 FIFO -#define EP1_FIFO (*(volatile unsigned char *)0x520001c4) //Endpoint 1 FIFO -#define EP2_FIFO (*(volatile unsigned char *)0x520001c8) //Endpoint 2 FIFO -#define EP3_FIFO (*(volatile unsigned char *)0x520001cc) //Endpoint 3 FIFO -#define EP4_FIFO (*(volatile unsigned char *)0x520001d0) //Endpoint 4 FIFO -#define EP1_DMA_CON (*(volatile unsigned char *)0x52000200) //EP1 DMA interface control -#define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) //EP1 DMA Tx unit counter -#define EP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) //EP1 DMA Tx FIFO counter -#define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020c) //EP1 DMA total Tx counter -#define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000210) -#define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000214) -#define EP2_DMA_CON (*(volatile unsigned char *)0x52000218) //EP2 DMA interface control -#define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021c) //EP2 DMA Tx unit counter -#define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) //EP2 DMA Tx FIFO counter -#define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000224) //EP2 DMA total Tx counter -#define EP2_DMA_TTC_M (*(volatile unsigned char *)0x52000228) -#define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022c) -#define EP3_DMA_CON (*(volatile unsigned char *)0x52000240) //EP3 DMA interface control -#define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) //EP3 DMA Tx unit counter -#define EP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) //EP3 DMA Tx FIFO counter -#define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024c) //EP3 DMA total Tx counter -#define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000250) -#define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000254) -#define EP4_DMA_CON (*(volatile unsigned char *)0x52000258) //EP4 DMA interface control -#define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025c) //EP4 DMA Tx unit counter -#define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) //EP4 DMA Tx FIFO counter -#define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000264) //EP4 DMA total Tx counter -#define EP4_DMA_TTC_M (*(volatile unsigned char *)0x52000268) -#define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026c) -#endif // __BIG_ENDIAN - - -// WATCH DOG TIMER -#define WTCON (*(volatile unsigned *)0x53000000) //Watch-dog timer mode -#define WTDAT (*(volatile unsigned *)0x53000004) //Watch-dog timer data -#define WTCNT (*(volatile unsigned *)0x53000008) //Eatch-dog timer count - - -// IIC -#define IICCON (*(volatile unsigned *)0x54000000) //IIC control -#define IICSTAT (*(volatile unsigned *)0x54000004) //IIC status -#define IICADD (*(volatile unsigned *)0x54000008) //IIC address -#define IICDS (*(volatile unsigned *)0x5400000c) //IIC data shift - - -// IIS -#define IISCON (*(volatile unsigned *)0x55000000) //IIS Control -#define IISMOD (*(volatile unsigned *)0x55000004) //IIS Mode -#define IISPSR (*(volatile unsigned *)0x55000008) //IIS Prescaler -#define IISFCON (*(volatile unsigned *)0x5500000c) //IIS FIFO control - -#ifdef __BIG_ENDIAN -#define IISFIFO ((volatile unsigned short *)0x55000012) //IIS FIFO entry - -#else //Little Endian -#define IISFIFO ((volatile unsigned short *)0x55000010) //IIS FIFO entry - -#endif - - -// I/O PORT -#define GPACON (*(volatile unsigned *)0x56000000) //Port A control -#define GPADAT (*(volatile unsigned *)0x56000004) //Port A data - -#define GPBCON (*(volatile unsigned *)0x56000010) //Port B control -#define GPBDAT (*(volatile unsigned *)0x56000014) //Port B data -#define GPBUP (*(volatile unsigned *)0x56000018) //Pull-up control B - -#define GPCCON (*(volatile unsigned *)0x56000020) //Port C control -#define GPCDAT (*(volatile unsigned *)0x56000024) //Port C data -#define GPCUP (*(volatile unsigned *)0x56000028) //Pull-up control C - -#define GPDCON (*(volatile unsigned *)0x56000030) //Port D control -#define GPDDAT (*(volatile unsigned *)0x56000034) //Port D data -#define GPDUP (*(volatile unsigned *)0x56000038) //Pull-up control D - -#define GPECON (*(volatile unsigned *)0x56000040) //Port E control -#define GPEDAT (*(volatile unsigned *)0x56000044) //Port E data -#define GPEUP (*(volatile unsigned *)0x56000048) //Pull-up control E - -#define GPFCON (*(volatile unsigned *)0x56000050) //Port F control -#define GPFDAT (*(volatile unsigned *)0x56000054) //Port F data -#define GPFUP (*(volatile unsigned *)0x56000058) //Pull-up control F - -#define GPGCON (*(volatile unsigned *)0x56000060) //Port G control -#define GPGDAT (*(volatile unsigned *)0x56000064) //Port G data -#define GPGUP (*(volatile unsigned *)0x56000068) //Pull-up control G - -#define GPHCON (*(volatile unsigned *)0x56000070) //Port H control -#define GPHDAT (*(volatile unsigned *)0x56000074) //Port H data -#define GPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H - -#define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control -#define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data -#define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J - -#define MISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control -#define DCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control -#define EXTINT0 (*(volatile unsigned *)0x56000088) //External interrupt control egister 0 -#define EXTINT1 (*(volatile unsigned *)0x5600008c) //External interrupt control egister 1 -#define EXTINT2 (*(volatile unsigned *)0x56000090) //External interrupt control egister 2 -#define EINTFLT0 (*(volatile unsigned *)0x56000094) //Reserved -#define EINTFLT1 (*(volatile unsigned *)0x56000098) //Reserved -#define EINTFLT2 (*(volatile unsigned *)0x5600009c) //External interrupt filter control egister 2 -#define EINTFLT3 (*(volatile unsigned *)0x560000a0) //External interrupt filter control egister 3 -#define EINTMASK (*(volatile unsigned *)0x560000a4) //External interrupt mask -#define EINTPEND (*(volatile unsigned *)0x560000a8) //External interrupt pending -#define GSTATUS0 (*(volatile unsigned *)0x560000ac) //External pin status -#define GSTATUS1 (*(volatile unsigned *)0x560000b0) //Chip ID(0x32410000) -#define GSTATUS2 (*(volatile unsigned *)0x560000b4) //Reset type -#define GSTATUS3 (*(volatile unsigned *)0x560000b8) //Saved data0(32-bit) before entering POWER_OFF mode -#define GSTATUS4 (*(volatile unsigned *)0x560000bc) //Saved data0(32-bit) before entering POWER_OFF mode - - -// RTC -#ifdef __BIG_ENDIAN -#define RTCCON (*(volatile unsigned char *)0x57000043) //RTC control -#define TICNT (*(volatile unsigned char *)0x57000047) //Tick time count -#define RTCALM (*(volatile unsigned char *)0x57000053) //RTC alarm control -#define ALMSEC (*(volatile unsigned char *)0x57000057) //Alarm second -#define ALMMIN (*(volatile unsigned char *)0x5700005b) //Alarm minute -#define ALMHOUR (*(volatile unsigned char *)0x5700005f) //Alarm Hour -#define ALMDATE (*(volatile unsigned char *)0x57000063) //Alarm day <-- May 06, 2002 SOP -#define ALMMON (*(volatile unsigned char *)0x57000067) //Alarm month -#define ALMYEAR (*(volatile unsigned char *)0x5700006b) //Alarm year -#define RTCRST (*(volatile unsigned char *)0x5700006f) //RTC ound eset -#define BCDSEC (*(volatile unsigned char *)0x57000073) //BCD second -#define BCDMIN (*(volatile unsigned char *)0x57000077) //BCD minute -#define BCDHOUR (*(volatile unsigned char *)0x5700007b) //BCD hour -#define BCDDATE (*(volatile unsigned char *)0x5700007f) //BCD day <-- May 06, 2002 SOP -#define BCDDAY (*(volatile unsigned char *)0x57000083) //BCD date <-- May 06, 2002 SOP -#define BCDMON (*(volatile unsigned char *)0x57000087) //BCD month -#define BCDYEAR (*(volatile unsigned char *)0x5700008b) //BCD year - -#else //Little Endian -#define RTCCON (*(volatile unsigned char *)0x57000040) //RTC control -#define TICNT (*(volatile unsigned char *)0x57000044) //Tick time count -#define RTCALM (*(volatile unsigned char *)0x57000050) //RTC alarm control -#define ALMSEC (*(volatile unsigned char *)0x57000054) //Alarm second -#define ALMMIN (*(volatile unsigned char *)0x57000058) //Alarm minute -#define ALMHOUR (*(volatile unsigned char *)0x5700005c) //Alarm Hour -#define ALMDATE (*(volatile unsigned char *)0x57000060) //Alarm day <-- May 06, 2002 SOP -#define ALMMON (*(volatile unsigned char *)0x57000064) //Alarm month -#define ALMYEAR (*(volatile unsigned char *)0x57000068) //Alarm year -#define RTCRST (*(volatile unsigned char *)0x5700006c) //RTC ound eset -#define BCDSEC (*(volatile unsigned char *)0x57000070) //BCD second -#define BCDMIN (*(volatile unsigned char *)0x57000074) //BCD minute -#define BCDHOUR (*(volatile unsigned char *)0x57000078) //BCD hour -#define BCDDATE (*(volatile unsigned char *)0x5700007c) //BCD day <-- May 06, 2002 SOP -#define BCDDAY (*(volatile unsigned char *)0x57000080) //BCD date <-- May 06, 2002 SOP -#define BCDMON (*(volatile unsigned char *)0x57000084) //BCD month -#define BCDYEAR (*(volatile unsigned char *)0x57000088) //BCD year -#endif //RTC - - -// ADC -#define ADCCON (*(volatile unsigned *)0x58000000) //ADC control -#define ADCTSC (*(volatile unsigned *)0x58000004) //ADC touch screen control -#define ADCDLY (*(volatile unsigned *)0x58000008) //ADC start or Interval Delay -#define ADCDAT0 (*(volatile unsigned *)0x5800000c) //ADC conversion data 0 -#define ADCDAT1 (*(volatile unsigned *)0x58000010) //ADC conversion data 1 - -// SPI -#define SPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control -#define SPSTA0 (*(volatile unsigned *)0x59000004) //SPI0 status -#define SPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control -#define SPPRE0 (*(volatile unsigned *)0x5900000c) //SPI0 baud ate prescaler -#define SPTDAT0 (*(volatile unsigned *)0x59000010) //SPI0 Tx data -#define SPRDAT0 (*(volatile unsigned *)0x59000014) //SPI0 Rx data - -#define SPCON1 (*(volatile unsigned *)0x59000020) //SPI1 control -#define SPSTA1 (*(volatile unsigned *)0x59000024) //SPI1 status -#define SPPIN1 (*(volatile unsigned *)0x59000028) //SPI1 pin control -#define SPPRE1 (*(volatile unsigned *)0x5900002c) //SPI1 baud ate prescaler -#define SPTDAT1 (*(volatile unsigned *)0x59000030) //SPI1 Tx data -#define SPRDAT1 (*(volatile unsigned *)0x59000034) //SPI1 Rx data - - -// SD Interface -#define SDICON (*(volatile unsigned *)0x5a000000) //SDI control -#define SDIPRE (*(volatile unsigned *)0x5a000004) //SDI baud ate prescaler -#define SDICARG (*(volatile unsigned *)0x5a000008) //SDI command argument -#define SDICCON (*(volatile unsigned *)0x5a00000c) //SDI command control -#define SDICSTA (*(volatile unsigned *)0x5a000010) //SDI command status -#define SDIRSP0 (*(volatile unsigned *)0x5a000014) //SDI esponse 0 -#define SDIRSP1 (*(volatile unsigned *)0x5a000018) //SDI esponse 1 -#define SDIRSP2 (*(volatile unsigned *)0x5a00001c) //SDI esponse 2 -#define SDIRSP3 (*(volatile unsigned *)0x5a000020) //SDI esponse 3 -#define SDIDTIMER (*(volatile unsigned *)0x5a000024) //SDI data/busy timer -#define SDIBSIZE (*(volatile unsigned *)0x5a000028) //SDI block size -#define SDIDCON (*(volatile unsigned *)0x5a00002c) //SDI data control -#define SDIDCNT (*(volatile unsigned *)0x5a000030) //SDI data emain counter -#define SDIDSTA (*(volatile unsigned *)0x5a000034) //SDI data status -#define SDIFSTA (*(volatile unsigned *)0x5a000038) //SDI FIFO status -#define SDIIMSK (*(volatile unsigned *)0x5a000040) //SDI interrupt mask - -#ifdef __BIG_ENDIAN /* edited for 2440A */ -#define SDIDAT (*(volatile unsigned *)0x5a00004c) -#else // Little Endian -#define SDIDAT (*(volatile unsigned *)0x5a000040) -#endif //SD Interface - -// PENDING BIT -#define INTEINT0 (0) -#define INTEINT1 (1) -#define INTEINT2 (2) -#define INTEINT3 (3) -#define INTEINT4_7 (4) -#define INTEINT8_23 (5) -#define INTNOTUSED6 (6) -#define INTBAT_FLT (7) -#define INTTICK (8) -#define INTWDT (9) -#define INTTIMER0 (10) -#define INTTIMER1 (11) -#define INTTIMER2 (12) -#define INTTIMER3 (13) -#define INTTIMER4 (14) -#define INTUART2 (15) -#define INTLCD (16) -#define INTDMA0 (17) -#define INTDMA1 (18) -#define INTDMA2 (19) -#define INTDMA3 (20) -#define INTSDI (21) -#define INTSPI0 (22) -#define INTUART1 (23) -//#define INTNOTUSED24 (24) -#define INTNIC (24) -#define INTUSBD (25) -#define INTUSBH (26) -#define INTIIC (27) -#define INTUART0 (28) -#define INTSPI1 (29) -#define INTRTC (30) -#define INTADC (31) -#define BIT_ALLMSK (0xffffffff) - -#define BIT_SUB_ALLMSK (0x7ff) -#define INTSUB_ADC (10) -#define INTSUB_TC (9) -#define INTSUB_ERR2 (8) -#define INTSUB_TXD2 (7) -#define INTSUB_RXD2 (6) -#define INTSUB_ERR1 (5) -#define INTSUB_TXD1 (4) -#define INTSUB_RXD1 (3) -#define INTSUB_ERR0 (2) -#define INTSUB_TXD0 (1) -#define INTSUB_RXD0 (0) - -#define BIT_SUB_ADC (0x1<<10) -#define BIT_SUB_TC (0x1<<9) -#define BIT_SUB_ERR2 (0x1<<8) -#define BIT_SUB_TXD2 (0x1<<7) -#define BIT_SUB_RXD2 (0x1<<6) -#define BIT_SUB_ERR1 (0x1<<5) -#define BIT_SUB_TXD1 (0x1<<4) -#define BIT_SUB_RXD1 (0x1<<3) -#define BIT_SUB_ERR0 (0x1<<2) -#define BIT_SUB_TXD0 (0x1<<1) -#define BIT_SUB_RXD0 (0x1<<0) - -#define ClearPending(bit) {SRCPND = bit;INTPND = bit;INTPND;} -//Wait until INTPND is changed for the case that the ISR is very short. - -#define INTGLOBAL 32 - -/*****************************/ -/* CPU Mode */ -/*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -struct rt_hw_register -{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; -}; - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif diff --git a/rt-thread/libcpu/arm/s3c24x0/stack.c b/rt-thread/libcpu/arm/s3c24x0/stack.c deleted file mode 100644 index 99938e2..0000000 --- a/rt-thread/libcpu/arm/s3c24x0/stack.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard the first version - */ -#include -#include "s3c24x0.h" - -/** - * @addtogroup S3C24X0 - */ -/*@{*/ - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - - stack_addr += sizeof(rt_uint32_t); - stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); - stk = (rt_uint32_t *)stack_addr; - - *(--stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0xdeadbeef; /* r12 */ - *(--stk) = 0xdeadbeef; /* r11 */ - *(--stk) = 0xdeadbeef; /* r10 */ - *(--stk) = 0xdeadbeef; /* r9 */ - *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = 0xdeadbeef; /* r4 */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = 0xdeadbeef; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - *(--stk) = SVCMODE; /* cpsr */ - *(--stk) = SVCMODE; /* spsr */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/s3c24x0/start_gcc.S b/rt-thread/libcpu/arm/s3c24x0/start_gcc.S deleted file mode 100644 index c6c7fa4..0000000 --- a/rt-thread/libcpu/arm/s3c24x0/start_gcc.S +++ /dev/null @@ -1,386 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - * 2006-10-05 Alsor.Z for s3c2440 initialize - * 2008-01-29 Yi.Qiu for QEMU emulator - */ - -#define CONFIG_STACKSIZE 512 -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -.equ USERMODE, 0x10 -.equ FIQMODE, 0x11 -.equ IRQMODE, 0x12 -.equ SVCMODE, 0x13 -.equ ABORTMODE, 0x17 -.equ UNDEFMODE, 0x1b -.equ MODEMASK, 0x1f -.equ NOINT, 0xc0 - -.equ RAM_BASE, 0x00000000 /*Start address of RAM */ -.equ ROM_BASE, 0x30000000 /*Start address of Flash */ - -.equ MPLLCON, 0x4c000004 /*Mpll control register */ -.equ M_MDIV, 0x20 -.equ M_PDIV, 0x4 -.equ M_SDIV, 0x2 - -.equ INTMSK, 0x4a000008 -.equ INTSUBMSK, 0x4a00001c -.equ WTCON, 0x53000000 -.equ LOCKTIME, 0x4c000000 -.equ CLKDIVN, 0x4c000014 /*Clock divider control */ -.equ GPHCON, 0x56000070 /*Port H control */ -.equ GPHUP, 0x56000078 /*Pull-up control H */ -.equ BWSCON, 0x48000000 /*Bus width & wait status */ -.equ BANKCON0, 0x48000004 /*Boot ROM control */ -.equ BANKCON1, 0x48000008 /*BANK1 control */ -.equ BANKCON2, 0x4800000c /*BANK2 cControl */ -.equ BANKCON3, 0x48000010 /*BANK3 control */ -.equ BANKCON4, 0x48000014 /*BANK4 control */ -.equ BANKCON5, 0x48000018 /*BANK5 control */ -.equ BANKCON6, 0x4800001c /*BANK6 control */ -.equ BANKCON7, 0x48000020 /*BANK7 control */ -.equ REFRESH, 0x48000024 /*DRAM/SDRAM efresh */ -.equ BANKSIZE, 0x48000028 /*Flexible Bank Size */ -.equ MRSRB6, 0x4800002c /*Mode egister set for SDRAM*/ -.equ MRSRB7, 0x48000030 /*Mode egister set for SDRAM*/ - -/* - ************************************************************************* - * - * Jump vector table - * - ************************************************************************* - */ - -.section .init, "ax" -.code 32 - -.globl _start -_start: - b reset - ldr pc, _vector_undef - ldr pc, _vector_swi - ldr pc, _vector_pabt - ldr pc, _vector_dabt - ldr pc, _vector_resv - ldr pc, _vector_irq - ldr pc, _vector_fiq - -_vector_undef: .word vector_undef -_vector_swi: .word vector_swi -_vector_pabt: .word vector_pabt -_vector_dabt: .word vector_dabt -_vector_resv: .word vector_resv -_vector_irq: .word vector_irq -_vector_fiq: .word vector_fiq - -.balignl 16,0xdeadbeef - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * relocate armboot to ram - * setup stack - * jump to second stage - * - ************************************************************************* - */ - -_TEXT_BASE: - .word TEXT_BASE - -/* - * rtthread kernel start and end - * which are defined in linker script - */ -.globl _rtthread_start -_rtthread_start: - .word _start - -.globl _rtthread_end -_rtthread_end: - .word _end - -/* - * rtthread bss start and end which are defined in linker script - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word __bss_end - -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word _irq_stack_start + 1024 - -.globl FIQ_STACK_START -FIQ_STACK_START: - .word _fiq_stack_start + 1024 - -.globl UNDEFINED_STACK_START -UNDEFINED_STACK_START: - .word _undefined_stack_start + CONFIG_STACKSIZE - -.globl ABORT_STACK_START -ABORT_STACK_START: - .word _abort_stack_start + CONFIG_STACKSIZE - -.globl _STACK_START -_STACK_START: - .word _svc_stack_start + 4096 - -/* ----------------------------------entry------------------------------*/ -reset: - - /* set the cpu to SVC32 mode */ - mrs r0,cpsr - bic r0,r0,#MODEMASK - orr r0,r0,#SVCMODE - msr cpsr,r0 - - /* watch dog disable */ - ldr r0,=WTCON - ldr r1,=0x0 - str r1,[r0] - - /* mask all IRQs by clearing all bits in the INTMRs */ - ldr r1, =INTMSK - ldr r0, =0xffffffff - str r0, [r1] - ldr r1, =INTSUBMSK - ldr r0, =0x7fff /*all sub interrupt disable */ - str r0, [r1] - - /* set interrupt vector */ - ldr r0, _load_address - mov r1, #0x0 /* target address */ - add r2, r0, #0x20 /* size, 32bytes */ - -copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - ble copy_loop - - /* setup stack */ - bl stack_setup - - /* clear .bss */ - mov r0,#0 /* get a zero */ - ldr r1,=__bss_start /* bss start */ - ldr r2,=__bss_end /* bss end */ - -bss_loop: - cmp r1,r2 /* check if data to clear */ - strlo r0,[r1],#4 /* clear 4 bytes */ - blo bss_loop /* loop until done */ - - /* call C++ constructors of global objects */ - ldr r0, =__ctors_start__ - ldr r1, =__ctors_end__ - -ctor_loop: - cmp r0, r1 - beq ctor_end - ldr r2, [r0], #4 - stmfd sp!, {r0-r1} - mov lr, pc - bx r2 - ldmfd sp!, {r0-r1} - b ctor_loop - -ctor_end: - - /* start RT-Thread Kernel */ - ldr pc, _rtthread_startup - -_rtthread_startup: - .word rtthread_startup -#if defined (__FLASH_BUILD__) -_load_address: - .word ROM_BASE + _TEXT_BASE -#else -_load_address: - .word RAM_BASE + _TEXT_BASE -#endif - -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -/* exception handlers */ - .align 5 -vector_undef: - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ /* Calling SP, LR */ - str lr, [r8, #0] /* Save calling PC */ - mrs r6, spsr - str r6, [r8, #4] /* Save CPSR */ - str r0, [r8, #8] /* Save OLD_R0 */ - mov r0, sp - - bl rt_hw_trap_udef - - .align 5 -vector_swi: - bl rt_hw_trap_swi - - .align 5 -vector_pabt: - bl rt_hw_trap_pabt - - .align 5 -vector_dabt: - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ /* Calling SP, LR */ - str lr, [r8, #0] /* Save calling PC */ - mrs r6, spsr - str r6, [r8, #4] /* Save CPSR */ - str r0, [r8, #8] /* Save OLD_R0 */ - mov r0, sp - - bl rt_hw_trap_dabt - - .align 5 -vector_resv: - bl rt_hw_trap_resv - -.globl rt_interrupt_enter -.globl rt_interrupt_leave -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -vector_irq: - stmfd sp!, {r0-r12,lr} - bl rt_interrupt_enter - bl rt_hw_trap_irq - bl rt_interrupt_leave - - /* if rt_thread_switch_interrupt_flag set, jump to _interrupt_thread_switch and don't return */ - ldr r0, =rt_thread_switch_interrupt_flag - ldr r1, [r0] - cmp r1, #1 - beq _interrupt_thread_switch - - ldmfd sp!, {r0-r12,lr} - subs pc, lr, #4 - - .align 5 -vector_fiq: - stmfd sp!,{r0-r7,lr} - bl rt_hw_trap_fiq - ldmfd sp!,{r0-r7,lr} - subs pc,lr,#4 - -_interrupt_thread_switch: - mov r1, #0 /* clear rt_thread_switch_interrupt_flag*/ - str r1, [r0] - - ldmfd sp!, {r0-r12,lr} /* reload saved registers */ - stmfd sp!, {r0-r3} /* save r0-r3 */ - mov r1, sp - add sp, sp, #16 /* restore sp */ - sub r2, lr, #4 /* save old task's pc to r2 */ - - mrs r3, spsr /* disable interrupt */ - orr r0, r3, #NOINT - msr spsr_c, r0 - - ldr r0, =.+8 /* switch to interrupted task's stack*/ - movs pc, r0 - - stmfd sp!, {r2} /* push old task's pc */ - stmfd sp!, {r4-r12,lr} /* push old task's lr,r12-r4 */ - mov r4, r1 /* Special optimised code below */ - mov r5, r3 - ldmfd r4!, {r0-r3} - stmfd sp!, {r0-r3} /* push old task's r3-r0 */ - stmfd sp!, {r5} /* push old task's psr */ - mrs r4, spsr - stmfd sp!, {r4} /* push old task's spsr */ - - ldr r4, =rt_interrupt_from_thread - ldr r5, [r4] - str sp, [r5] /* store sp in preempted tasks's TCB*/ - - ldr r6, =rt_interrupt_to_thread - ldr r6, [r6] - ldr sp, [r6] /* get new task's stack pointer */ - - ldmfd sp!, {r4} /* pop new task's spsr */ - msr SPSR_cxsf, r4 - ldmfd sp!, {r4} /* pop new task's psr */ - msr CPSR_cxsf, r4 - - ldmfd sp!, {r0-r12,lr,pc} /* pop new task's r0-r12,lr & pc */ - -stack_setup: - mrs r0, cpsr - bic r0, r0, #MODEMASK - orr r1, r0, #UNDEFMODE|NOINT - msr cpsr_cxsf, r1 /* undef mode */ - ldr sp, UNDEFINED_STACK_START - - orr r1,r0,#ABORTMODE|NOINT - msr cpsr_cxsf,r1 /* abort mode */ - ldr sp, ABORT_STACK_START - - orr r1,r0,#IRQMODE|NOINT - msr cpsr_cxsf,r1 /* IRQ mode */ - ldr sp, IRQ_STACK_START - - orr r1,r0,#FIQMODE|NOINT - msr cpsr_cxsf,r1 /* FIQ mode */ - ldr sp, FIQ_STACK_START - - bic r0,r0,#MODEMASK - orr r1,r0,#SVCMODE|NOINT - msr cpsr_cxsf,r1 /* SVC mode */ - - ldr sp, _STACK_START - - /* USER mode is not initialized. */ - mov pc,lr /* The LR register may be not valid for the mode changes.*/ - -/*/*}*/ - diff --git a/rt-thread/libcpu/arm/s3c24x0/start_rvds.S b/rt-thread/libcpu/arm/s3c24x0/start_rvds.S deleted file mode 100644 index bd4478f..0000000 --- a/rt-thread/libcpu/arm/s3c24x0/start_rvds.S +++ /dev/null @@ -1,1190 +0,0 @@ -;/*****************************************************************************/ -;/* S3C2440.S: Startup file for Samsung S3C440 */ -;/*****************************************************************************/ -;/* <<< Use Configuration Wizard in Context Menu >>> */ -;/*****************************************************************************/ -;/* This file is part of the uVision/ARM development tools. */ -;/* Copyright (c) 2005-2008 Keil Software. All rights reserved. */ -;/* This software may only be used under the terms of a valid, current, */ -;/* end user licence from KEIL for a compatible version of KEIL software */ -;/* development tools. Nothing else gives you the right to use this software. */ -;/*****************************************************************************/ - - -;/* -; * The S3C2440.S code is executed after CPU Reset. This file may be -; * translated with the following SET symbols. In uVision these SET -; * symbols are entered under Options - ASM - Define. -; * -; * NO_CLOCK_SETUP: when set the startup code will not initialize Clock -; * (used mostly when clock is already initialized from script .ini -; * file). -; * -; * NO_MC_SETUP: when set the startup code will not initialize Memory -; * Controller (used mostly when clock is already initialized from script -; * .ini file). -; * -; * NO_GP_SETUP: when set the startup code will not initialize General Ports -; * (used mostly when clock is already initialized from script .ini -; * file). -; * -; * RAM_INTVEC: when set the startup code copies exception vectors -; * from execution address to on-chip RAM. -; */ - - -; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled - - -;----------------------- Stack and Heap Definitions ---------------------------- - -;// Stack Configuration (Stack Sizes in Bytes) -;// Undefined Mode <0x0-0xFFFFFFFF:8> -;// Supervisor Mode <0x0-0xFFFFFFFF:8> -;// Abort Mode <0x0-0xFFFFFFFF:8> -;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> -;// Interrupt Mode <0x0-0xFFFFFFFF:8> -;// User/System Mode <0x0-0xFFFFFFFF:8> -;// - -UND_Stack_Size EQU 0x00000000 -SVC_Stack_Size EQU 0x00000100 -ABT_Stack_Size EQU 0x00000000 -FIQ_Stack_Size EQU 0x00000000 -IRQ_Stack_Size EQU 0x00000100 -USR_Stack_Size EQU 0x00000100 - -ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - -Stack_Mem SPACE USR_Stack_Size -__initial_sp SPACE ISR_Stack_Size -Stack_Top - - -;// Heap Configuration -;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> -;// - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - -;----------------------- Memory Definitions ------------------------------------ - -; Internal Memory Base Addresses -IRAM_BASE EQU 0x40000000 - - -;----------------------- Watchdog Timer Definitions ---------------------------- - -WT_BASE EQU 0x53000000 ; Watchdog Timer Base Address -WTCON_OFS EQU 0x00 ; Watchdog Timer Control Register Offset -WTDAT_OFS EQU 0x04 ; Watchdog Timer Data Register Offset -WTCNT_OFS EQU 0x08 ; Watchdog Timer Count Register Offset - -;// Watchdog Timer Setup -;// Watchdog Timer Control Register (WTCON) -;// Prescaler Value <0-255> -;// Watchdog Timer Enable -;// Clock Division Factor -;// <0=> 16 <1=> 32 <2=> 64 <3=> 128 -;// Interrupt Generation Enable -;// Reset Enable -;// -;// Watchdog Timer Data Register (WTDAT) -;// Count Reload Value <0-65535> -;// -;// Watchdog Timer Setup -WT_SETUP EQU 1 -WTCON_Val EQU 0x00000000 -WTDAT_Val EQU 0x00008000 - - -;----------------------- Clock and Power Management Definitions ---------------- - -CLOCK_BASE EQU 0x4C000000 ; Clock Base Address -LOCKTIME_OFS EQU 0x00 ; PLL Lock Time Count Register Offset -MPLLCON_OFS EQU 0x04 ; MPLL Configuration Register Offset -UPLLCON_OFS EQU 0x08 ; UPLL Configuration Register Offset -CLKCON_OFS EQU 0x0C ; Clock Generator Control Reg Offset -CLKSLOW_OFS EQU 0x10 ; Clock Slow Control Register Offset -CLKDIVN_OFS EQU 0x14 ; Clock Divider Control Register Offset -CAMDIVN_OFS EQU 0x18 ; Camera Clock Divider Register Offset - -;// Clock Setup -;// PLL Lock Time Count Register (LOCKTIME) -;// U_LTIME: UPLL Lock Time Count Value for UCLK <0x0-0xFFFF> -;// M_LTIME: MPLL Lock Time Count Value for FCLK, HCLK and PCLK <0x0-0xFFFF> -;// -;// MPLL Configuration Register (MPLLCON) -;// MPLL = (2 * m * Fin) / (p * 2^s) -;// m: Main Divider m Value <9-256><#-8> -;// m = MDIV + 8 -;// p: Pre-divider p Value <3-64><#-2> -;// p = PDIV + 2 -;// s: Post Divider s Value <0-3> -;// s = SDIV -;// -;// UPLL Configuration Register (UPLLCON) -;// UPLL = ( m * Fin) / (p * 2^s) -;// m: Main Divider m Value <8-263><#-8> -;// m = MDIV + 8 -;// p: Pre-divider p Value <2-65><#-2> -;// p = PDIV + 2 -;// s: Post Divider s Value <0-3> -;// s = SDIV -;// -;// Clock Generation Control Register (CLKCON) -;// AC97 Enable -;// Camera Enable -;// SPI Enable -;// IIS Enable -;// IIC Enable -;// ADC + Touch Screen Enable -;// RTC Enable -;// GPIO Enable -;// UART2 Enable -;// UART1 Enable -;// UART0 Enable -;// SDI Enable -;// PWMTIMER Enable -;// USB Device Enable -;// USB Host Enable -;// LCDC Enable -;// NAND FLASH Controller Enable -;// SLEEP Enable -;// IDLE BIT Enable -;// -;// Clock Slow Control Register (CLKSLOW) -;// UCLK_ON: UCLK ON -;// MPLL_OFF: Turn off PLL -;// SLOW_BIT: Slow Mode Enable -;// SLOW_VAL: Slow Clock Divider <0-7> -;// -;// Clock Divider Control Register (CLKDIVN) -;// DIVN_UPLL: UCLK Select -;// <0=> UCLK = UPLL clock -;// <1=> UCLK = UPLL clock / 2 -;// HDIVN: HCLK Select -;// <0=> HCLK = FCLK -;// <1=> HCLK = FCLK / 2 -;// <2=> HCLK = FCLK / 4 if HCLK4_HALF = 0 in CAMDIVN, else HCLK = FCLK / 8 -;// <3=> HCLK = FCLK / 3 if HCLK3_HALF = 0 in CAMDIVN, else HCLK = FCLK / 6 -;// PDIVN: PCLK Select -;// <0=> PCLK = HCLK -;// <1=> PCLK = HCLK / 2 -;// -;// Camera Clock Divider Control Register (CAMDIVN) -;// DVS_EN: ARM Core Clock Select -;// <0=> ARM core runs at FCLK -;// <1=> ARM core runs at HCLK -;// HCLK4_HALF: HDIVN Division Rate Change Bit -;// <0=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 4 -;// <1=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 8 -;// HCLK3_HALF: HDIVN Division Rate Change Bit -;// <0=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 3 -;// <1=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 6 -;// CAMCLK Select -;// <0=> CAMCLK = UPLL -;// <1=> CAMCLK = UPLL / CAMCLK_DIV -;// CAMCLK_DIV: CAMCLK Divider <0-15> -;// Camera Clock = UPLL / (2 * (CAMCLK_DIV + 1)) -;// Divider is used only if CAMCLK_SEL = 1 -;// -;// Clock Setup -CLOCK_SETUP EQU 0 -LOCKTIME_Val EQU 0x0FFF0FFF -MPLLCON_Val EQU 0x00043011 -UPLLCON_Val EQU 0x00038021 -CLKCON_Val EQU 0x001FFFF0 -CLKSLOW_Val EQU 0x00000004 -CLKDIVN_Val EQU 0x0000000F -CAMDIVN_Val EQU 0x00000000 - - -;----------------------- Memory Controller Definitions ------------------------- - -MC_BASE EQU 0x48000000 ; Memory Controller Base Address -BWSCON_OFS EQU 0x00 ; Bus Width and Wait Status Ctrl Offset -BANKCON0_OFS EQU 0x04 ; Bank 0 Control Register Offset -BANKCON1_OFS EQU 0x08 ; Bank 1 Control Register Offset -BANKCON2_OFS EQU 0x0C ; Bank 2 Control Register Offset -BANKCON3_OFS EQU 0x10 ; Bank 3 Control Register Offset -BANKCON4_OFS EQU 0x14 ; Bank 4 Control Register Offset -BANKCON5_OFS EQU 0x18 ; Bank 5 Control Register Offset -BANKCON6_OFS EQU 0x1C ; Bank 6 Control Register Offset -BANKCON7_OFS EQU 0x20 ; Bank 7 Control Register Offset -REFRESH_OFS EQU 0x24 ; SDRAM Refresh Control Register Offset -BANKSIZE_OFS EQU 0x28 ; Flexible Bank Size Register Offset -MRSRB6_OFS EQU 0x2C ; Bank 6 Mode Register Offset -MRSRB7_OFS EQU 0x30 ; Bank 7 Mode Register Offset - -;// Memory Controller Setup -;// Bus Width and Wait Control Register (BWSCON) -;// ST7: Use UB/LB for Bank 7 -;// WS7: Enable Wait Status for Bank 7 -;// DW7: Data Bus Width for Bank 7 -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved -;// ST6: Use UB/LB for Bank 6 -;// WS6: Enable Wait Status for Bank 6 -;// DW6: Data Bus Width for Bank 6 -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved -;// ST5: Use UB/LB for Bank 5 -;// WS5: Enable Wait Status for Bank 5 -;// DW5: Data Bus Width for Bank 5 -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved -;// ST4: Use UB/LB for Bank 4 -;// WS4: Enable Wait Status for Bank 4 -;// DW4: Data Bus Width for Bank 4 -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved -;// ST3: Use UB/LB for Bank 3 -;// WS3: Enable Wait Status for Bank 3 -;// DW3: Data Bus Width for Bank 3 -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved -;// ST2: Use UB/LB for Bank 2 -;// WS2: Enable Wait Status for Bank 2 -;// DW2: Data Bus Width for Bank 2 -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved -;// ST1: Use UB/LB for Bank 1 -;// WS1: Enable Wait Status for Bank 1 -;// DW1: Data Bus Width for Bank 1 -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved -;// DW0: Indicate Data Bus Width for Bank 0 -;// <1=> 16-bit <2=> 32-bit -;// -;// Bank 0 Control Register (BANKCON0) -;// Tacs: Address Set-up Time before nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcos: Chip Selection Set-up Time before nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacc: Access Cycle -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks -;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks -;// Tcoh: Chip Selection Hold Time after nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcah: Address Hold Time after nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacp: Page Mode Access Cycle at Page Mode -;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks -;// PMC: Page Mode Configuration -;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data -;// -;// Bank 1 Control Register (BANKCON1) -;// Tacs: Address Set-up Time before nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcos: Chip Selection Set-up Time before nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacc: Access Cycle -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks -;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks -;// Tcoh: Chip Selection Hold Time after nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcah: Address Hold Time after nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacp: Page Mode Access Cycle at Page Mode -;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks -;// PMC: Page Mode Configuration -;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data -;// -;// Bank 2 Control Register (BANKCON2) -;// Tacs: Address Set-up Time before nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcos: Chip Selection Set-up Time before nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacc: Access Cycle -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks -;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks -;// Tcoh: Chip Selection Hold Time after nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcah: Address Hold Time after nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacp: Page Mode Access Cycle at Page Mode -;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks -;// PMC: Page Mode Configuration -;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data -;// -;// Bank 3 Control Register (BANKCON3) -;// Tacs: Address Set-up Time before nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcos: Chip Selection Set-up Time before nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacc: Access Cycle -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks -;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks -;// Tcoh: Chip Selection Hold Time after nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcah: Address Hold Time after nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacp: Page Mode Access Cycle at Page Mode -;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks -;// PMC: Page Mode Configuration -;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data -;// -;// Bank 4 Control Register (BANKCON4) -;// Tacs: Address Set-up Time before nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcos: Chip Selection Set-up Time before nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacc: Access Cycle -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks -;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks -;// Tcoh: Chip Selection Hold Time after nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcah: Address Hold Time after nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacp: Page Mode Access Cycle at Page Mode -;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks -;// PMC: Page Mode Configuration -;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data -;// -;// Bank 5 Control Register (BANKCON5) -;// Tacs: Address Set-up Time before nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcos: Chip Selection Set-up Time before nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacc: Access Cycle -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks -;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks -;// Tcoh: Chip Selection Hold Time after nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcah: Address Hold Time after nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacp: Page Mode Access Cycle at Page Mode -;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks -;// PMC: Page Mode Configuration -;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data -;// -;// Bank 6 Control Register (BANKCON6) -;// Memory Type Selection -;// <0=> ROM or SRAM <3=> SDRAM -;// Tacs: Address Set-up Time before nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcos: Chip Selection Set-up Time before nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacc: Access Cycle -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks -;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks -;// Tcoh: Chip Selection Hold Time after nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcah: Address Hold Time after nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay -;// Parameter depends on Memory Type: if type SRAM then parameter is Tacp, -;// if type is SDRAM then parameter is Trcd -;// For SDRAM 6 cycles setting is not allowed -;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks -;// PMC/SCAN: Page Mode Configuration / Column Address Number <0-3> -;// Parameter depends on Memory Type: if type SRAM then parameter is PMC, -;// if type is SDRAM then parameter is SCAN -;// -;// Bank 7 Control Register (BANKCON7) -;// Memory Type Selection -;// <0=> ROM or SRAM <3=> SDRAM -;// Tacs: Address Set-up Time before nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcos: Chip Selection Set-up Time before nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacc: Access Cycle -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks -;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks -;// Tcoh: Chip Selection Hold Time after nOE -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tcah: Address Hold Time after nGCS -;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks -;// Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay -;// Parameter depends on Memory Type: if type SRAM then parameter is Tacp, -;// if type is SDRAM then parameter is Trcd -;// For SDRAM 6 cycles setting is not allowed -;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks -;// PMC/SCAN: Page Mode Configuration / Column Address Number <0-3> -;// Parameter depends on Memory Type: if type SRAM then parameter is PMC, -;// if type is SDRAM then parameter is SCAN -;// -;// SDRAM Refresh Control Register (REFRESH) -;// REFEN: SDRAM Refresh Enable -;// TREFMD: SDRAM Refresh Mode -;// <0=> CBR/Auto Refresh <1=> Self Refresh -;// Trp: SDRAM RAS Pre-charge Time -;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> Reserved -;// Tsrc: SDRAM Semi Row Cycle Time -;// SDRAM Row cycle time: Trc = Tsrc + Trp -;// <0=> 4 clocks <1=> 5 clocks <2=> 6 clocks <3=> 7 clocks -;// Refresh Counter <0-1023> -;// Refresh Period = (2048 - Refresh Count + 1) / HCLK -;// -;// Flexible Bank Size Register (BANKSIZE) -;// BURST_EN: ARM Core Burst Operation Enable -;// SCKE_EN: SDRAM Power Down Mode Enable -;// SCLK_EN: SCLK Enabled During SDRAM Access Cycle -;// <0=> SCLK is always active <1=> SCLK is active only during the access -;// BK76MAP: BANK6 and BANK7 Memory Map -;// <0=> 32MB / 32MB <1=> 64MB / 64MB <2=> 128MB / 128MB -;// <4=> 2MB / 2MB <5=> 4MB / 4MB <6=> 8MB / 8MB <7=> 16MB / 16MB -;// Refresh Counter <0-1023> -;// Refresh Period = (2048 - Refresh Count + 1) / HCLK -;// -;// SDRAM Mode Register Set Register 6 (MRSRB6) -;// WBL: Write Burst Length -;// <0=> Burst (Fixed) -;// TM: Test Mode -;// <0=> Mode register set (Fixed) -;// CL: CAS Latency -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks -;// BT: Burst Type -;// <0=> Sequential (Fixed) -;// BL: Burst Length -;// <0=> 1 (Fixed) -;// -;// SDRAM Mode Register Set Register 7 (MRSRB7) -;// WBL: Write Burst Length -;// <0=> Burst (Fixed) -;// TM: Test Mode -;// <0=> Mode register set (Fixed) -;// CL: CAS Latency -;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks -;// BT: Burst Type -;// <0=> Sequential (Fixed) -;// BL: Burst Length -;// <0=> 1 (Fixed) -;// -;// Memory Controller Setup -MC_SETUP EQU 0 -BWSCON_Val EQU 0x22000000 -BANKCON0_Val EQU 0x00000700 -BANKCON1_Val EQU 0x00000700 -BANKCON2_Val EQU 0x00000700 -BANKCON3_Val EQU 0x00000700 -BANKCON4_Val EQU 0x00000700 -BANKCON5_Val EQU 0x00000700 -BANKCON6_Val EQU 0x00018005 -BANKCON7_Val EQU 0x00018005 -REFRESH_Val EQU 0x008404F3 -BANKSIZE_Val EQU 0x00000032 -MRSRB6_Val EQU 0x00000020 -MRSRB7_Val EQU 0x00000020 - - -;----------------------- I/O Port Definitions ---------------------------------- - -GPA_BASE EQU 0x56000000 ; GPA Base Address -GPB_BASE EQU 0x56000010 ; GPB Base Address -GPC_BASE EQU 0x56000020 ; GPC Base Address -GPD_BASE EQU 0x56000030 ; GPD Base Address -GPE_BASE EQU 0x56000040 ; GPE Base Address -GPF_BASE EQU 0x56000050 ; GPF Base Address -GPG_BASE EQU 0x56000060 ; GPG Base Address -GPH_BASE EQU 0x56000070 ; GPH Base Address -GPJ_BASE EQU 0x560000D0 ; GPJ Base Address -GPCON_OFS EQU 0x00 ; Control Register Offset -GPDAT_OFS EQU 0x04 ; Data Register Offset -GPUP_OFS EQU 0x08 ; Pull-up Disable Register Offset - -;// I/O Setup -GP_SETUP EQU 1 - -;// Port A Settings -;// Port A Control Register (GPACON) -;// GPA22 <0=> Output <1=> nFCE -;// GPA21 <0=> Output <1=> nRSTOUT -;// GPA20 <0=> Output <1=> nFRE -;// GPA19 <0=> Output <1=> nFWE -;// GPA18 <0=> Output <1=> ALE -;// GPA17 <0=> Output <1=> CLE -;// GPA16 <0=> Output <1=> nGCS[5] -;// GPA15 <0=> Output <1=> nGCS[4] -;// GPA14 <0=> Output <1=> nGCS[3] -;// GPA13 <0=> Output <1=> nGCS[2] -;// GPA12 <0=> Output <1=> nGCS[1] -;// GPA11 <0=> Output <1=> ADDR26 -;// GPA10 <0=> Output <1=> ADDR25 -;// GPA9 <0=> Output <1=> ADDR24 -;// GPA8 <0=> Output <1=> ADDR23 -;// GPA7 <0=> Output <1=> ADDR22 -;// GPA6 <0=> Output <1=> ADDR21 -;// GPA5 <0=> Output <1=> ADDR20 -;// GPA4 <0=> Output <1=> ADDR19 -;// GPA3 <0=> Output <1=> ADDR18 -;// GPA2 <0=> Output <1=> ADDR17 -;// GPA1 <0=> Output <1=> ADDR16 -;// GPA0 <0=> Output <1=> ADDR0 -;// -;// -GPA_SETUP EQU 0 -GPACON_Val EQU 0x000003FF - -;// Port B Settings -;// Port B Control Register (GPBCON) -;// GPB10 <0=> Input <1=> Output <2=> nXDREQ0 <3=> Reserved -;// GPB9 <0=> Input <1=> Output <2=> nXDACK0 <3=> Reserved -;// GPB8 <0=> Input <1=> Output <2=> nXDREQ1 <3=> Reserved -;// GPB7 <0=> Input <1=> Output <2=> nXDACK1 <3=> Reserved -;// GPB6 <0=> Input <1=> Output <2=> nXBREQ <3=> Reserved -;// GPB5 <0=> Input <1=> Output <2=> nXBACK <3=> Reserved -;// GPB4 <0=> Input <1=> Output <2=> TCLK[0] <3=> Reserved -;// GPB3 <0=> Input <1=> Output <2=> TOUT3 <3=> Reserved -;// GPB2 <0=> Input <1=> Output <2=> TOUT2 <3=> Reserved -;// GPB1 <0=> Input <1=> Output <2=> TOUT1 <3=> Reserved -;// GPB0 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved -;// -;// Port B Pull-up Settings Register (GPBUP) -;// GPB10 Pull-up Disable -;// GPB9 Pull-up Disable -;// GPB8 Pull-up Disable -;// GPB7 Pull-up Disable -;// GPB6 Pull-up Disable -;// GPB5 Pull-up Disable -;// GPB4 Pull-up Disable -;// GPB3 Pull-up Disable -;// GPB2 Pull-up Disable -;// GPB1 Pull-up Disable -;// GPB0 Pull-up Disable -;// -;// -GPB_SETUP EQU 0 -GPBCON_Val EQU 0x00000000 -GPBUP_Val EQU 0x00000000 - -;// Port C Settings -;// Port C Control Register (GPCCON) -;// GPC15 <0=> Input <1=> Output <2=> VD[7] <3=> Reserved -;// GPC14 <0=> Input <1=> Output <2=> VD[6] <3=> Reserved -;// GPC13 <0=> Input <1=> Output <2=> VD[5] <3=> Reserved -;// GPC12 <0=> Input <1=> Output <2=> VD[4] <3=> Reserved -;// GPC11 <0=> Input <1=> Output <2=> VD[3] <3=> Reserved -;// GPC10 <0=> Input <1=> Output <2=> VD[2] <3=> Reserved -;// GPC9 <0=> Input <1=> Output <2=> VD[1] <3=> Reserved -;// GPC8 <0=> Input <1=> Output <2=> VD[0] <3=> Reserved -;// GPC7 <0=> Input <1=> Output <2=> LCD_LPCREVB <3=> Reserved -;// GPC6 <0=> Input <1=> Output <2=> LCD_LPCREV <3=> Reserved -;// GPC5 <0=> Input <1=> Output <2=> LCD_LPCOE <3=> Reserved -;// GPC4 <0=> Input <1=> Output <2=> VM <3=> I2SSDI -;// GPC3 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved -;// GPC2 <0=> Input <1=> Output <2=> VLINE <3=> Reserved -;// GPC1 <0=> Input <1=> Output <2=> VCLK <3=> Reserved -;// GPC0 <0=> Input <1=> Output <2=> LEND <3=> Reserved -;// -;// Port C Pull-up Settings Register (GPCUP) -;// GPC15 Pull-up Disable -;// GPC14 Pull-up Disable -;// GPC13 Pull-up Disable -;// GPC12 Pull-up Disable -;// GPC11 Pull-up Disable -;// GPC10 Pull-up Disable -;// GPC9 Pull-up Disable -;// GPC8 Pull-up Disable -;// GPC7 Pull-up Disable -;// GPC6 Pull-up Disable -;// GPC5 Pull-up Disable -;// GPC4 Pull-up Disable -;// GPC3 Pull-up Disable -;// GPC2 Pull-up Disable -;// GPC1 Pull-up Disable -;// GPC0 Pull-up Disable -;// -;// -GPC_SETUP EQU 0 -GPCCON_Val EQU 0x00000000 -GPCUP_Val EQU 0x00000000 - -;// Port D Settings -;// Port D Control Register (GPDCON) -;// GPD15 <0=> Input <1=> Output <2=> VD[23] <3=> nSS0 -;// GPD14 <0=> Input <1=> Output <2=> VD[22] <3=> nSS1 -;// GPD13 <0=> Input <1=> Output <2=> VD[21] <3=> Reserved -;// GPD12 <0=> Input <1=> Output <2=> VD[20] <3=> Reserved -;// GPD11 <0=> Input <1=> Output <2=> VD[19] <3=> Reserved -;// GPD10 <0=> Input <1=> Output <2=> VD[18] <3=> SPICLK1 -;// GPD9 <0=> Input <1=> Output <2=> VD[17] <3=> SPIMOSI1 -;// GPD8 <0=> Input <1=> Output <2=> VD[16] <3=> SPIMISO1 -;// GPD7 <0=> Input <1=> Output <2=> VD[15] <3=> Reserved -;// GPD6 <0=> Input <1=> Output <2=> VD[14] <3=> Reserved -;// GPD5 <0=> Input <1=> Output <2=> VD[13] <3=> Reserved -;// GPD4 <0=> Input <1=> Output <2=> VD[12] <3=> Reserved -;// GPD3 <0=> Input <1=> Output <2=> VD[11] <3=> Reserved -;// GPD2 <0=> Input <1=> Output <2=> VD[10] <3=> Reserved -;// GPD1 <0=> Input <1=> Output <2=> VD[9] <3=> Reserved -;// GPD0 <0=> Input <1=> Output <2=> VD[8] <3=> Reserved -;// -;// Port D Pull-up Settings Register (GPDUP) -;// GPD15 Pull-up Disable -;// GPD14 Pull-up Disable -;// GPD13 Pull-up Disable -;// GPD12 Pull-up Disable -;// GPD11 Pull-up Disable -;// GPD10 Pull-up Disable -;// GPD9 Pull-up Disable -;// GPD8 Pull-up Disable -;// GPD7 Pull-up Disable -;// GPD6 Pull-up Disable -;// GPD5 Pull-up Disable -;// GPD4 Pull-up Disable -;// GPD3 Pull-up Disable -;// GPD2 Pull-up Disable -;// GPD1 Pull-up Disable -;// GPD0 Pull-up Disable -;// -;// -GPD_SETUP EQU 0 -GPDCON_Val EQU 0x00000000 -GPDUP_Val EQU 0x00000000 - -;// Port E Settings -;// Port E Control Register (GPECON) -;// GPE15 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved -;// This pad is open-drain, and has no pull-up option. -;// GPE14 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved -;// This pad is open-drain, and has no pull-up option. -;// GPE13 <0=> Input <1=> Output <2=> SPICLK0 <3=> Reserved -;// GPE12 <0=> Input <1=> Output <2=> SPIMOSI0 <3=> Reserved -;// GPE11 <0=> Input <1=> Output <2=> SPIMISO0 <3=> Reserved -;// GPE10 <0=> Input <1=> Output <2=> SDDAT3 <3=> Reserved -;// GPE9 <0=> Input <1=> Output <2=> SDDAT2 <3=> Reserved -;// GPE8 <0=> Input <1=> Output <2=> SDDAT1 <3=> Reserved -;// GPE7 <0=> Input <1=> Output <2=> SDDAT0 <3=> Reserved -;// GPE6 <0=> Input <1=> Output <2=> SDCMD <3=> Reserved -;// GPE5 <0=> Input <1=> Output <2=> SDCLK <3=> Reserved -;// GPE4 <0=> Input <1=> Output <2=> I2SDO <3=> AC_SDATA_OUT -;// GPE3 <0=> Input <1=> Output <2=> I2SDI <3=> AC_SDATA_IN -;// GPE2 <0=> Input <1=> Output <2=> CDCLK <3=> AC_nRESET -;// GPE1 <0=> Input <1=> Output <2=> I2SSCLK <3=> AC_BIT_CLK -;// GPE0 <0=> Input <1=> Output <2=> I2SLRCK <3=> AC_SYNC -;// -;// Port E Pull-up Settings Register (GPEUP) -;// GPE13 Pull-up Disable -;// GPE12 Pull-up Disable -;// GPE11 Pull-up Disable -;// GPE10 Pull-up Disable -;// GPE9 Pull-up Disable -;// GPE8 Pull-up Disable -;// GPE7 Pull-up Disable -;// GPE6 Pull-up Disable -;// GPE5 Pull-up Disable -;// GPE4 Pull-up Disable -;// GPE3 Pull-up Disable -;// GPE2 Pull-up Disable -;// GPE1 Pull-up Disable -;// GPE0 Pull-up Disable -;// -;// -GPE_SETUP EQU 0 -GPECON_Val EQU 0x00000000 -GPEUP_Val EQU 0x00000000 - -;// Port F Settings -;// Port F Control Register (GPFCON) -;// GPF7 <0=> Input <1=> Output <2=> EINT[7] <3=> Reserved -;// GPF6 <0=> Input <1=> Output <2=> EINT[6] <3=> Reserved -;// GPF5 <0=> Input <1=> Output <2=> EINT[5] <3=> Reserved -;// GPF4 <0=> Input <1=> Output <2=> EINT[4] <3=> Reserved -;// GPF3 <0=> Input <1=> Output <2=> EINT[3] <3=> Reserved -;// GPF2 <0=> Input <1=> Output <2=> EINT[2] <3=> Reserved -;// GPF1 <0=> Input <1=> Output <2=> EINT[1] <3=> Reserved -;// GPF0 <0=> Input <1=> Output <2=> EINT[0] <3=> Reserved -;// -;// Port F Pull-up Settings Register (GPFUP) -;// GPF7 Pull-up Disable -;// GPF6 Pull-up Disable -;// GPF5 Pull-up Disable -;// GPF4 Pull-up Disable -;// GPF3 Pull-up Disable -;// GPF2 Pull-up Disable -;// GPF1 Pull-up Disable -;// GPF0 Pull-up Disable -;// -;// -GPF_SETUP EQU 1 -GPFCON_Val EQU 0x000000AA -GPFUP_Val EQU 0x0000000F - -;// Port G Settings -;// Port G Control Register (GPGCON) -;// GPG15 <0=> Input <1=> Output <2=> EINT[23] <3=> Reserved -;// GPG14 <0=> Input <1=> Output <2=> EINT[22] <3=> Reserved -;// GPG13 <0=> Input <1=> Output <2=> EINT[21] <3=> Reserved -;// GPG12 <0=> Input <1=> Output <2=> EINT[20] <3=> Reserved -;// GPG11 <0=> Input <1=> Output <2=> EINT[19] <3=> TCLK[1] -;// GPG10 <0=> Input <1=> Output <2=> EINT[18] <3=> nCTS1 -;// GPG9 <0=> Input <1=> Output <2=> EINT[17] <3=> nRTS1 -;// GPG8 <0=> Input <1=> Output <2=> EINT[16] <3=> Reserved -;// GPG7 <0=> Input <1=> Output <2=> EINT[15] <3=> SPICLK1 -;// GPG6 <0=> Input <1=> Output <2=> EINT[14] <3=> SPIMOSI1 -;// GPG5 <0=> Input <1=> Output <2=> EINT[13] <3=> SPIMISO1 -;// GPG4 <0=> Input <1=> Output <2=> EINT[12] <3=> LCD_PWRDN -;// GPG3 <0=> Input <1=> Output <2=> EINT[11] <3=> nSS1 -;// GPG2 <0=> Input <1=> Output <2=> EINT[10] <3=> nSS0 -;// GPG1 <0=> Input <1=> Output <2=> EINT[9] <3=> Reserved -;// GPG0 <0=> Input <1=> Output <2=> EINT[8] <3=> Reserved -;// -;// Port G Pull-up Settings Register (GPGUP) -;// GPG15 Pull-up Disable -;// GPG14 Pull-up Disable -;// GPG13 Pull-up Disable -;// GPG12 Pull-up Disable -;// GPG11 Pull-up Disable -;// GPG10 Pull-up Disable -;// GPG9 Pull-up Disable -;// GPG8 Pull-up Disable -;// GPG7 Pull-up Disable -;// GPG6 Pull-up Disable -;// GPG5 Pull-up Disable -;// GPG4 Pull-up Disable -;// GPG3 Pull-up Disable -;// GPG2 Pull-up Disable -;// GPG1 Pull-up Disable -;// GPG0 Pull-up Disable -;// -;// -GPG_SETUP EQU 0 -GPGCON_Val EQU 0x00000000 -GPGUP_Val EQU 0x00000000 - -;// Port H Settings -;// Port H Control Register (GPHCON) -;// GPH10 <0=> Input <1=> Output <2=> CLKOUT1 <3=> Reserved -;// GPH9 <0=> Input <1=> Output <2=> CLKOUT0 <3=> Reserved -;// GPH8 <0=> Input <1=> Output <2=> UEXTCLK <3=> Reserved -;// GPH7 <0=> Input <1=> Output <2=> RXD[2] <3=> nCTS1 -;// GPH6 <0=> Input <1=> Output <2=> TXD[2] <3=> nRTS1 -;// GPH5 <0=> Input <1=> Output <2=> RXD[1] <3=> Reserved -;// GPH4 <0=> Input <1=> Output <2=> TXD[1] <3=> Reserved -;// GPH3 <0=> Input <1=> Output <2=> RXD[0] <3=> Reserved -;// GPH2 <0=> Input <1=> Output <2=> TXD[0] <3=> Reserved -;// GPH1 <0=> Input <1=> Output <2=> nRTS0 <3=> Reserved -;// GPH0 <0=> Input <1=> Output <2=> nCTS0 <3=> Reserved -;// -;// Port H Pull-up Settings Register (GPHUP) -;// GPH10 Pull-up Disable -;// GPH9 Pull-up Disable -;// GPH8 Pull-up Disable -;// GPH7 Pull-up Disable -;// GPH6 Pull-up Disable -;// GPH5 Pull-up Disable -;// GPH4 Pull-up Disable -;// GPH3 Pull-up Disable -;// GPH2 Pull-up Disable -;// GPH1 Pull-up Disable -;// GPH0 Pull-up Disable -;// -;// -GPH_SETUP EQU 0 -GPHCON_Val EQU 0x00000000 -GPHUP_Val EQU 0x00000000 - -;// Port J Settings -;// Port J Control Register (GPJCON) -;// GPJ12 <0=> Input <1=> Output <2=> CAMRESET <3=> Reserved -;// GPJ11 <0=> Input <1=> Output <2=> CAMCLKOUT <3=> Reserved -;// GPJ10 <0=> Input <1=> Output <2=> CAMHREF <3=> Reserved -;// GPJ9 <0=> Input <1=> Output <2=> CAMVSYNC <3=> Reserved -;// GPJ8 <0=> Input <1=> Output <2=> CAMPCLK <3=> Reserved -;// GPJ7 <0=> Input <1=> Output <2=> CAMDATA[7] <3=> Reserved -;// GPJ6 <0=> Input <1=> Output <2=> CAMDATA[6] <3=> Reserved -;// GPJ5 <0=> Input <1=> Output <2=> CAMDATA[5] <3=> Reserved -;// GPJ4 <0=> Input <1=> Output <2=> CAMDATA[4] <3=> Reserved -;// GPJ3 <0=> Input <1=> Output <2=> CAMDATA[3] <3=> Reserved -;// GPJ2 <0=> Input <1=> Output <2=> CAMDATA[2] <3=> Reserved -;// GPJ1 <0=> Input <1=> Output <2=> CAMDATA[1] <3=> Reserved -;// GPJ0 <0=> Input <1=> Output <2=> CAMDATA[0] <3=> Reserved -;// -;// Port J Pull-up Settings Register (GPJUP) -;// GPJ12 Pull-up Disable -;// GPJ11 Pull-up Disable -;// GPJ10 Pull-up Disable -;// GPJ9 Pull-up Disable -;// GPJ8 Pull-up Disable -;// GPJ7 Pull-up Disable -;// GPJ6 Pull-up Disable -;// GPJ5 Pull-up Disable -;// GPJ4 Pull-up Disable -;// GPJ3 Pull-up Disable -;// GPJ2 Pull-up Disable -;// GPJ1 Pull-up Disable -;// GPJ0 Pull-up Disable -;// -;// -GPJ_SETUP EQU 0 -GPJCON_Val EQU 0x00000000 -GPJUP_Val EQU 0x00000000 - -;// I/O Setup - - -;----------------------- CODE -------------------------------------------------- - - PRESERVE8 - - -; Area Definition and Entry Point -; Startup Code must be linked first at Address at which it expects to run. - - AREA RESET, CODE, READONLY - ARM - -; Exception Vectors -; Mapped to Address 0. -; Absolute addressing mode must be used. -; Dummy Handlers are implemented as infinite loops which can be modified. - - EXPORT Entry_Point -Entry_Point -Vectors LDR PC, Reset_Addr - LDR PC, Undef_Addr - LDR PC, SWI_Addr - LDR PC, PAbt_Addr - LDR PC, DAbt_Addr - NOP - LDR PC, IRQ_Addr - LDR PC, FIQ_Addr - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SWI_Addr DCD SWI_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler - DCD 0 ; Reserved Address -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - -Undef_Handler B Undef_Handler -SWI_Handler B SWI_Handler -PAbt_Handler B PAbt_Handler -;DAbt_Handler B DAbt_Handler -FIQ_Handler B FIQ_Handler - -;* -;************************************************************************* -;* -;* Interrupt handling -;* -;************************************************************************* -;* -; DAbt Handler -DAbt_Handler - IMPORT rt_hw_trap_dabt - - sub sp, sp, #72 - stmia sp, {r0 - r12} ;/* Calling r0-r12 */ - add r8, sp, #60 - stmdb r8, {sp, lr} ;/* Calling SP, LR */ - str lr, [r8, #0] ;/* Save calling PC */ - mrs r6, spsr - str r6, [r8, #4] ;/* Save CPSR */ - str r0, [r8, #8] ;/* Save OLD_R0 */ - mov r0, sp - - bl rt_hw_trap_dabt - - -;########################################## -; Reset Handler - - EXPORT Reset_Handler -Reset_Handler - - -; Watchdog Setup --------------------------------------------------------------- - - IF WT_SETUP != 0 - LDR R0, =WT_BASE - LDR R1, =WTCON_Val - LDR R2, =WTDAT_Val - STR R2, [R0, #WTCNT_OFS] - STR R2, [R0, #WTDAT_OFS] - STR R1, [R0, #WTCON_OFS] - ENDIF - - -; Clock Setup ------------------------------------------------------------------ - - IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0) - LDR R0, =CLOCK_BASE - LDR R1, =LOCKTIME_Val - STR R1, [R0, #LOCKTIME_OFS] - MOV R1, #CLKDIVN_Val - STR R1, [R0, #CLKDIVN_OFS] - LDR R1, =CAMDIVN_Val - STR R1, [R0, #CAMDIVN_OFS] - LDR R1, =MPLLCON_Val - STR R1, [R0, #MPLLCON_OFS] - LDR R1, =UPLLCON_Val - STR R1, [R0, #UPLLCON_OFS] - MOV R1, #CLKSLOW_Val - STR R1, [R0, #CLKSLOW_OFS] - LDR R1, =CLKCON_Val - STR R1, [R0, #CLKCON_OFS] - ENDIF - - -; Memory Controller Setup ------------------------------------------------------ - - IF (:LNOT:(:DEF:NO_MC_SETUP)):LAND:(CLOCK_SETUP != 0) - LDR R0, =MC_BASE - LDR R1, =BWSCON_Val - STR R1, [R0, #BWSCON_OFS] - LDR R1, =BANKCON0_Val - STR R1, [R0, #BANKCON0_OFS] - LDR R1, =BANKCON1_Val - STR R1, [R0, #BANKCON1_OFS] - LDR R1, =BANKCON2_Val - STR R1, [R0, #BANKCON2_OFS] - LDR R1, =BANKCON3_Val - STR R1, [R0, #BANKCON3_OFS] - LDR R1, =BANKCON4_Val - STR R1, [R0, #BANKCON4_OFS] - LDR R1, =BANKCON5_Val - STR R1, [R0, #BANKCON5_OFS] - LDR R1, =BANKCON6_Val - STR R1, [R0, #BANKCON6_OFS] - LDR R1, =BANKCON7_Val - STR R1, [R0, #BANKCON7_OFS] - LDR R1, =REFRESH_Val - STR R1, [R0, #REFRESH_OFS] - MOV R1, #BANKSIZE_Val - STR R1, [R0, #BANKSIZE_OFS] - MOV R1, #MRSRB6_Val - STR R1, [R0, #MRSRB6_OFS] - MOV R1, #MRSRB7_Val - STR R1, [R0, #MRSRB7_OFS] - ENDIF - - -; I/O Pins Setup --------------------------------------------------------------- - - IF (:LNOT:(:DEF:NO_GP_SETUP)):LAND:(GP_SETUP != 0) - - IF GPA_SETUP != 0 - LDR R0, =GPA_BASE - LDR R1, =GPACON_Val - STR R1, [R0, #GPCON_OFS] - ENDIF - - IF GPB_SETUP != 0 - LDR R0, =GPB_BASE - LDR R1, =GPBCON_Val - STR R1, [R0, #GPCON_OFS] - LDR R1, =GPBUP_Val - STR R1, [R0, #GPUP_OFS] - ENDIF - - IF GPC_SETUP != 0 - LDR R0, =GPC_BASE - LDR R1, =GPCCON_Val - STR R1, [R0, #GPCON_OFS] - LDR R1, =GPCUP_Val - STR R1, [R0, #GPUP_OFS] - ENDIF - - IF GPD_SETUP != 0 - LDR R0, =GPD_BASE - LDR R1, =GPDCON_Val - STR R1, [R0, #GPCON_OFS] - LDR R1, =GPDUP_Val - STR R1, [R0, #GPUP_OFS] - ENDIF - - IF GPE_SETUP != 0 - LDR R0, =GPE_BASE - LDR R1, =GPECON_Val - STR R1, [R0, #GPCON_OFS] - LDR R1, =GPEUP_Val - STR R1, [R0, #GPUP_OFS] - ENDIF - - IF GPF_SETUP != 0 - LDR R0, =GPF_BASE - LDR R1, =GPFCON_Val - STR R1, [R0, #GPCON_OFS] - LDR R1, =GPFUP_Val - STR R1, [R0, #GPUP_OFS] - ENDIF - - IF GPG_SETUP != 0 - LDR R0, =GPG_BASE - LDR R1, =GPGCON_Val - STR R1, [R0, #GPCON_OFS] - LDR R1, =GPGUP_Val - STR R1, [R0, #GPUP_OFS] - ENDIF - - IF GPH_SETUP != 0 - LDR R0, =GPH_BASE - LDR R1, =GPHCON_Val - STR R1, [R0, #GPCON_OFS] - LDR R1, =GPHUP_Val - STR R1, [R0, #GPUP_OFS] - ENDIF - - IF GPJ_SETUP != 0 - LDR R0, =GPJ_BASE - LDR R1, =GPJCON_Val - STR R1, [R0, #GPCON_OFS] - LDR R1, =GPJUP_Val - STR R1, [R0, #GPUP_OFS] - ENDIF - - ENDIF - - -; Copy Exception Vectors to Internal RAM --------------------------------------- - - IF :DEF:RAM_INTVEC - ADR R8, Vectors ; Source - LDR R9, =IRAM_BASE ; Destination - LDMIA R8!, {R0-R7} ; Load Vectors - STMIA R9!, {R0-R7} ; Store Vectors - LDMIA R8!, {R0-R7} ; Load Handler Addresses - STMIA R9!, {R0-R7} ; Store Handler Addresses - ENDIF - - -; Setup Stack for each mode ---------------------------------------------------- - - LDR R0, =Stack_Top - -; Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #UND_Stack_Size - -; Enter Abort Mode and set its Stack Pointer - MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #ABT_Stack_Size - -; Enter FIQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #FIQ_Stack_Size - -; Enter IRQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #IRQ_Stack_Size - -; Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #SVC_Stack_Size - -; Enter User Mode and set its Stack Pointer - ; MSR CPSR_c, #Mode_USR - MOV SP, R0 - SUB SL, SP, #USR_Stack_Size - -; Enter the C code ------------------------------------------------------------- - - IMPORT __main - LDR R0, =__main - BX R0 - - IMPORT rt_interrupt_enter - IMPORT rt_interrupt_leave - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - IMPORT rt_hw_trap_irq - -IRQ_Handler PROC - EXPORT IRQ_Handler - STMFD sp!, {r0-r12,lr} - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; if rt_thread_switch_interrupt_flag set, jump to - ; rt_hw_context_switch_interrupt_do and don't return - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD sp!, {r0-r12,lr} - SUBS pc, lr, #4 - ENDP - -; /* -; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) -; */ -rt_hw_context_switch_interrupt_do PROC - EXPORT rt_hw_context_switch_interrupt_do - MOV r1, #0 ; clear flag - STR r1, [r0] - - LDMFD sp!, {r0-r12,lr}; reload saved registers - STMFD sp!, {r0-r3} ; save r0-r3 - MOV r1, sp - ADD sp, sp, #16 ; restore sp - SUB r2, lr, #4 ; save old task's pc to r2 - - MRS r3, spsr ; get cpsr of interrupt thread - - ; switch to SVC mode and no interrupt - MSR cpsr_c, #I_Bit:OR:F_Bit:OR:Mode_SVC - - STMFD sp!, {r2} ; push old task's pc - STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 - MOV r4, r1 ; Special optimised code below - MOV r5, r3 - LDMFD r4!, {r0-r3} - STMFD sp!, {r0-r3} ; push old task's r3-r0 - STMFD sp!, {r5} ; push old task's cpsr - MRS r4, spsr - STMFD sp!, {r4} ; push old task's spsr - - LDR r4, =rt_interrupt_from_thread - LDR r5, [r4] - STR sp, [r5] ; store sp in preempted tasks's TCB - - LDR r6, =rt_interrupt_to_thread - LDR r6, [r6] - LDR sp, [r6] ; get new task's stack pointer - - LDMFD sp!, {r4} ; pop new task's spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task's psr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc - ENDP - - IF :DEF:__MICROLIB - - EXPORT __heap_base - EXPORT __heap_limit - - ELSE -; User Initial Stack & Heap - AREA |.text|, CODE, READONLY - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + USR_Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDIF - - - END - diff --git a/rt-thread/libcpu/arm/s3c24x0/system_clock.c b/rt-thread/libcpu/arm/s3c24x0/system_clock.c deleted file mode 100644 index 235c5e5..0000000 --- a/rt-thread/libcpu/arm/s3c24x0/system_clock.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2008-04-25 Yi.qiu first version - */ - -#include -#include "s3c24x0.h" - -#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz - -#if CONFIG_SYS_CLK_FREQ == 12000000 - /* MPLL=2*12*100/6=400MHz */ - #define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */ - #define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */ - #define MPL_SDIV 0 /* s=MPL_SDIV=0 */ - /* UPLL=12*64/8=96MHz */ - #define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */ - #define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */ - #define UPL_SDIV 1 /* s=UPL_SDIV=1 */ - /* System clock divider FCLK:HCLK:PCLK=1:4:8 */ - #define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */ - #define HDIVN 0x2 /* HCLK = FCLK / 4 */ - #define PDIVN 0x1 /* PCLK = HCLK / 2 */ -#endif - -rt_uint32_t PCLK; -rt_uint32_t FCLK; -rt_uint32_t HCLK; -rt_uint32_t UCLK; - -void rt_hw_get_clock(void) -{ - rt_uint32_t val; - rt_uint8_t m, p, s; - - val = MPLLCON; - m = (val>>12)&0xff; - p = (val>>4)&0x3f; - s = val&3; - - FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<>1)&3; - p = val&1; - - switch (m) { - case 0: - HCLK = FCLK; - break; - case 1: - HCLK = FCLK>>1; - break; - case 2: - if(s&2) - HCLK = FCLK>>3; - else - HCLK = FCLK>>2; - break; - case 3: - if(s&1) - HCLK = FCLK/6; - else - HCLK = FCLK/3; - break; -} - - if(p) - PCLK = HCLK>>1; - else - PCLK = HCLK; -} - -void rt_hw_set_mpll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv) -{ - MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12); -} - -void rt_hw_set_upll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv) -{ - UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv; -} - -void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn) -{ - CLKDIVN = (hdivn<<1) | pdivn; -} - -/** - * @brief System Clock Configuration - */ -void rt_hw_clock_init(void) -{ - LOCKTIME = 0xFFFFFFFF; - rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV); - rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV); - rt_hw_set_divider(HDIVN, PDIVN); -} - diff --git a/rt-thread/libcpu/arm/s3c24x0/trap.c b/rt-thread/libcpu/arm/s3c24x0/trap.c deleted file mode 100644 index c4be806..0000000 --- a/rt-thread/libcpu/arm/s3c24x0/trap.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - * 2006-05-27 Bernard add skyeye support - * 2007-11-19 Yi.Qiu fix rt_hw_trap_irq function - * 2013-03-29 aozima Modify the interrupt interface implementations. - */ - -#include -#include - -#include "s3c24x0.h" - -/** - * @addtogroup S3C24X0 - */ -/*@{*/ - -extern struct rt_thread *rt_current_thread; -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) -extern long list_thread(void); -#endif - -/** - * this function will show registers of CPU - * - * @param regs the registers point - */ - -void rt_hw_show_register (struct rt_hw_register *regs) -{ - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); -} - -/** - * When ARM7TDMI comes across an instruction which it cannot handle, - * it takes the undefined instruction trap. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_udef(struct rt_hw_register *regs) -{ - rt_hw_show_register(regs); - - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * The software interrupt instruction (SWI) is used for entering - * Supervisor mode, usually to request a particular supervisor - * function. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_swi(struct rt_hw_register *regs) -{ - rt_hw_show_register(regs); - - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during an instruction prefetch. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_pabt(struct rt_hw_register *regs) -{ - rt_hw_show_register(regs); - - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during a data access. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_dabt(struct rt_hw_register *regs) -{ - rt_hw_show_register(regs); - - rt_kprintf("data abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * Normally, system will never reach here - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_resv(struct rt_hw_register *regs) -{ - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); -} - -extern struct rt_irq_desc isr_table[]; - -void rt_hw_trap_irq(void) -{ - unsigned long irq; - rt_isr_handler_t isr_func; - void *param; - - irq = INTOFFSET; - - if (irq == INTGLOBAL) return; - - /* get interrupt service routine */ - isr_func = isr_table[irq].handler; - param = isr_table[irq].param; - - /* turn to interrupt service routine */ - isr_func(irq, param); - - /* clear pending register */ - /* note: must be the last, if not, may repeat*/ - ClearPending(1 << irq); - -#ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; -#endif /* RT_USING_INTERRUPT_INFO */ -} - -void rt_hw_trap_fiq(void) -{ - rt_kprintf("fast interrupt request\n"); -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/s3c44b0/SConscript b/rt-thread/libcpu/arm/s3c44b0/SConscript deleted file mode 100644 index b259a94..0000000 --- a/rt-thread/libcpu/arm/s3c44b0/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/s3c44b0/context_gcc.S b/rt-thread/libcpu/arm/s3c44b0/context_gcc.S deleted file mode 100644 index 3fb5e77..0000000 --- a/rt-thread/libcpu/arm/s3c44b0/context_gcc.S +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-09-06 XuXinming first version - */ - -/*! - * \addtogroup S3C44B0 - */ -/*@{*/ - -#define NOINT 0xc0 - -/* - * rt_base_t rt_hw_interrupt_disable(); - */ -.globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mrs r0, cpsr - orr r1, r0, #NOINT - msr cpsr_c, r1 - mov pc, lr - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ -.globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - msr cpsr, r0 - mov pc, lr - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to - */ -.globl rt_hw_context_switch -rt_hw_context_switch: - stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) - stmfd sp!, {r0-r12, lr} @ push lr & register file - - mrs r4, cpsr - stmfd sp!, {r4} @ push cpsr - mrs r4, spsr - stmfd sp!, {r4} @ push spsr - - str sp, [r0] @ store sp in preempted tasks TCB - ldr sp, [r1] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - ldmfd sp!, {r4} @ pop new task cpsr - msr cpsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc} @ pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to - */ -.globl rt_hw_context_switch_to -rt_hw_context_switch_to: - ldr sp, [r0] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - ldmfd sp!, {r4} @ pop new task cpsr - msr cpsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc} @ pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - */ -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -.globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - ldr r2, =rt_thread_switch_interrupt_flag - ldr r3, [r2] - cmp r3, #1 - beq _reswitch - mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 - str r3, [r2] - ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread - str r0, [r2] -_reswitch: - ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread - str r1, [r2] - mov pc, lr diff --git a/rt-thread/libcpu/arm/s3c44b0/context_rvds.S b/rt-thread/libcpu/arm/s3c44b0/context_rvds.S deleted file mode 100644 index 5f61b86..0000000 --- a/rt-thread/libcpu/arm/s3c44b0/context_rvds.S +++ /dev/null @@ -1,103 +0,0 @@ -;/* -; * Copyright (c) 2006-2022, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2009-01-20 Bernard first version -; */ - -NOINT EQU 0xc0 ; disable interrupt in psr - - AREA |.text|, CODE, READONLY, ALIGN=2 - ARM - REQUIRE8 - PRESERVE8 - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ -rt_hw_interrupt_disable PROC - EXPORT rt_hw_interrupt_disable - MRS r0, cpsr - ORR r1, r0, #NOINT - MSR cpsr_c, r1 - BX lr - ENDP - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ -rt_hw_interrupt_enable PROC - EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0 - BX lr - ENDP - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ -rt_hw_context_switch PROC - EXPORT rt_hw_context_switch - STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC) - STMFD sp!, {r0-r12, lr} ; push lr & register file - - MRS r4, cpsr - STMFD sp!, {r4} ; push cpsr - MRS r4, spsr - STMFD sp!, {r4} ; push spsr - - STR sp, [r0] ; store sp in preempted tasks TCB - LDR sp, [r1] ; get new task stack pointer - - LDMFD sp!, {r4} ; pop new task spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task cpsr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; */ -rt_hw_context_switch_to PROC - EXPORT rt_hw_context_switch_to - LDR sp, [r0] ; get new task stack pointer - - LDMFD sp!, {r4} ; pop new task spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task cpsr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP - -;/* -; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); -; */ - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -rt_hw_context_switch_interrupt PROC - EXPORT rt_hw_context_switch_interrupt - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1 - STR r3, [r2] - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - BX lr - ENDP - - END diff --git a/rt-thread/libcpu/arm/s3c44b0/cpu.c b/rt-thread/libcpu/arm/s3c44b0/cpu.c deleted file mode 100644 index d80ca05..0000000 --- a/rt-thread/libcpu/arm/s3c44b0/cpu.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-09-06 XuXinming first version - */ - -#include -#include "s3c44b0.h" - -/** - * @addtogroup S3C44B0 - */ -/*@{*/ - -/** - * This function will enable I-Cache of CPU - * - */ -void rt_hw_cpu_icache_enable() -{ - rt_base_t reg; - - volatile int i; - /* flush cycle */ - for(i = 0x10002000; i < 0x10004800; i+=16) - { - *((int *)i)=0x0; - } - - /* - * Init cache - * Non-cacheable area (everything outside RAM) - * 0x0000:0000 - 0x0C00:0000 - */ - NCACHBE0 = 0xC0000000; - NCACHBE1 = 0x00000000; - - /* - Enable chache - */ - reg = SYSCFG; - reg |= 0x00000006; /* 8kB */ - SYSCFG = reg; -} - -/** - * This function will disable I-Cache of CPU - * - */ -void rt_hw_cpu_icache_disable() -{ - rt_base_t reg; - - reg = SYSCFG; - reg &= ~0x00000006; /* 8kB */ - SYSCFG = reg; -} - -/** - * this function will get the status of I-Cache - * - */ -rt_base_t rt_hw_cpu_icache_status() -{ - return 0; -} - -/** - * this function will enable D-Cache of CPU - * - */ -void rt_hw_cpu_dcache_enable() -{ - rt_hw_cpu_icache_enable(); -} - -/** - * this function will disable D-Cache of CPU - * - */ -void rt_hw_cpu_dcache_disable() -{ - rt_hw_cpu_icache_disable(); -} - -/** - * this function will get the status of D-Cache - * - */ -rt_base_t rt_hw_cpu_dcache_status() -{ - return rt_hw_cpu_icache_status(); -} - -/** - * this function will reset CPU - * - */ -RT_WEAK void rt_hw_cpu_reset() -{ -} - -/** - * this function will shutdown CPU - * - */ -RT_WEAK void rt_hw_cpu_shutdown() -{ - rt_kprintf("shutdown...\n"); - - while (1); -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/s3c44b0/interrupt.c b/rt-thread/libcpu/arm/s3c44b0/interrupt.c deleted file mode 100644 index 5464011..0000000 --- a/rt-thread/libcpu/arm/s3c44b0/interrupt.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-09-06 XuXinming first version - * 2006-09-15 Bernard add interrupt bank 0..3 for more effective - * in irq trap - */ - -#include -#include "s3c44b0.h" - -#define MAX_HANDLERS 26 - -extern rt_uint32_t rt_interrupt_nest; - -/* exception and interrupt handler table */ -rt_isr_handler_t isr_table[MAX_HANDLERS]; -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -unsigned char interrupt_bank0[256]; -unsigned char interrupt_bank1[256]; -unsigned char interrupt_bank2[256]; -unsigned char interrupt_bank3[256]; - -/** - * @addtogroup S3C44B0 - */ -/*@{*/ - -void rt_hw_interrupt_handle(int vector) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init() -{ - register int i; - - /* all interrupt disabled include global bit */ - INTMSK = 0x07ffffff; - - /* clear pending register */ - I_ISPC = 0x03ffffff; - - /* non-vector mode IRQ enable */ - INTCON = 0x5; - - /* all IRQ mode */ - INTMOD = 0x0; - - /* init exceptions table */ - for(i=0; i -#include - -#include "s3c44b0.h" - -void rt_serial_init(void); -void rt_console_puts(const char* str); -void rt_serial_putc(const char c); - -#define USTAT_RCV_READY 0x01 /* receive data ready */ -#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ - -rt_inline void serial_flush_input(void) -{ - volatile unsigned int tmp; - - /* keep on reading as long as the receiver is not empty */ - while(UTRSTAT0 & USTAT_RCV_READY) tmp = URXH0; -} - -rt_inline void serial_flush_output(void) -{ - /* wait until the transmitter is no longer busy */ - while(!(UTRSTAT0 & USTAT_TXB_EMPTY)) ; -} - -/** - * @addtogroup S3C44B0 - */ -/*@{*/ - -/** - * This function is used to display a string on console, normally, it's - * invoked by rt_kprintf - * - * @param str the displayed string - */ -void rt_console_puts(const char* str) -{ - while (*str) - { - rt_serial_putc (*str++); - } -} - -/** - * This function initializes serial - */ -void rt_serial_init() -{ - rt_uint32_t divisor = 0; - - divisor = 0x20; - - serial_flush_output(); - serial_flush_input(); - - /* UART interrupt off */ - UCON0 = 0; - /* FIFO disable */ - UFCON0 =0x0; - UMCON0 =0x0; - /* set baudrate */ - UBRDIV0 = divisor; - - /* word length=8bit, stop bit = 1, no parity, use external clock */ - ULCON0 = 0x03|0x00|0x00; - - UCON0 = 0x5; -} - -/** - * This function read a character from serial without interrupt enable mode - * - * @return the read char - */ -char rt_serial_getc() -{ - while ((UTRSTAT0 & USTAT_RCV_READY) == 0); - - return URXH0; -} - -/** - * This function will write a character to serial without interrupt enable mode - * - * @param c the char to write - */ -void rt_serial_putc(const char c) -{ - /* - to be polite with serial console add a line feed - to the carriage return character - */ - if (c=='\n')rt_serial_putc('\r'); - - /* wait for room in the transmit FIFO */ - while(!(UTRSTAT0 & USTAT_TXB_EMPTY)); - - UTXH0 = (rt_uint8_t)c; -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/s3c44b0/stack.c b/rt-thread/libcpu/arm/s3c44b0/stack.c deleted file mode 100644 index 4ed4693..0000000 --- a/rt-thread/libcpu/arm/s3c44b0/stack.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-09-06 XuXinming first version - */ -#include -#include "s3c44b0.h" - -/** - * @addtogroup S3C44B0 - */ -/*@{*/ - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - - stack_addr += sizeof(rt_uint32_t); - stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); - stk = (rt_uint32_t *)stack_addr; - *(--stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0xdeadbeef; /* r12 */ - *(--stk) = 0xdeadbeef; /* r11 */ - *(--stk) = 0xdeadbeef; /* r10 */ - *(--stk) = 0xdeadbeef; /* r9 */ - *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = 0xdeadbeef; /* r4 */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = 0xdeadbeef; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - *(--stk) = SVCMODE; /* cpsr */ - *(--stk) = SVCMODE; /* spsr */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/s3c44b0/start_gcc.S b/rt-thread/libcpu/arm/s3c44b0/start_gcc.S deleted file mode 100644 index ff7665c..0000000 --- a/rt-thread/libcpu/arm/s3c44b0/start_gcc.S +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-09-06 XuXinming first version - * 2006-09-20 Bernard clean the code - */ - -/** - * @addtogroup S3C44B0 - */ -/*@{*/ - -.section .init, "ax" -.code 32 -.globl _start -_start: - b reset - ldr pc, _vector_undef - ldr pc, _vector_swi - ldr pc, _vector_pabt - ldr pc, _vector_dabt - ldr pc, _vector_resv - ldr pc, _vector_irq - ldr pc, _vector_fiq - -_vector_undef: .word vector_undef -_vector_swi: .word vector_swi -_vector_pabt: .word vector_pabt -_vector_dabt: .word vector_dabt -_vector_resv: .word vector_resv -_vector_irq: .word vector_irq -_vector_fiq: .word vector_fiq - -.text -.code 32 - -/* - * rtthread kernel start and end - * which are defined in linker script - */ -.globl _rtthread_start -_rtthread_start:.word _start -.globl _rtthread_end -_rtthread_end: .word _end - -/* - * rtthread bss start and end - * which are defined in linker script - */ -.globl _bss_start -_bss_start: .word __bss_start -.globl _bss_end -_bss_end: .word __bss_end - -#if defined(__FLASH_BUILD__) -/* - * TEXT_BASE, - * which is defined in macro of make - */ -_TEXT_BASE: .word TEXT_BASE -#endif - - .equ WTCON, 0x1d30000 - .equ INTCON, 0x1e00000 - .equ INTMSK, 0x1e0000c - -/* the system entry */ -reset: - /* enter svc mode */ - msr cpsr_c, #SVCMODE|NOINT - - /*watch dog disable */ - ldr r0,=WTCON - ldr r1,=0x0 - str r1,[r0] - - /* all interrupt disable */ - ldr r0,=INTMSK - ldr r1,=0x07ffffff - str r1,[r0] - - ldr r1, =INTCON - ldr r0, =0x05 - str r0, [r1] - -#if defined(__FLASH_BUILD__) - /* init lowlevel */ - bl lowlevel_init -#endif - - /* setup stack */ - bl stack_setup - -#if defined(__FLASH_BUILD__) - mov r0, #0x0 /* r0 <- flash base address */ - ldr r1, _TEXT_BASE /* r1 <- the taget address */ - - ldr r2, _rtthread_start - ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of rtthread kernel */ - add r2, r0, r2 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - ble copy_loop -#endif - - /* start RT-Thread Kernel */ - ldr pc, _rtthread_startup - -_rtthread_startup: .word rtthread_startup - - .equ USERMODE, 0x10 - .equ FIQMODE, 0x11 - .equ IRQMODE, 0x12 - .equ SVCMODE, 0x13 - .equ ABORTMODE, 0x17 - .equ UNDEFMODE, 0x1b - .equ MODEMASK, 0x1f - .equ NOINT, 0xc0 - -/* exception handlers */ -vector_undef: bl rt_hw_trap_udef -vector_swi: bl rt_hw_trap_swi -vector_pabt: bl rt_hw_trap_pabt -vector_dabt: bl rt_hw_trap_dabt -vector_resv: bl rt_hw_trap_resv - -.globl rt_interrupt_enter -.globl rt_interrupt_leave -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -vector_irq: - stmfd sp!, {r0-r12,lr} - bl led_off - bl rt_interrupt_enter - bl rt_hw_trap_irq - bl rt_interrupt_leave - - /* if rt_thread_switch_interrupt_flag set, jump to _interrupt_thread_switch and don't return */ - ldr r0, =rt_thread_switch_interrupt_flag - ldr r1, [r0] - cmp r1, #1 - beq _interrupt_thread_switch - - ldmfd sp!, {r0-r12,lr} - subs pc, lr, #4 - - .align 5 -vector_fiq: - stmfd sp!,{r0-r7,lr} - bl rt_hw_trap_fiq - ldmfd sp!,{r0-r7,lr} - subs pc,lr,#4 - -_interrupt_thread_switch: - mov r1, #0 @ clear rt_thread_switch_interrupt_flag - str r1, [r0] - - ldmfd sp!, {r0-r12,lr} @ reload saved registers - stmfd sp!, {r0-r3} @ save r0-r3 - mov r1, sp - add sp, sp, #16 @ restore sp - sub r2, lr, #4 @ save old task's pc to r2 - - mrs r3, spsr @ disable interrupt - orr r0, r3, #NOINT - msr spsr_c, r0 - - ldr r0, =.+8 @ switch to interrupted task's stack - movs pc, r0 - - stmfd sp!, {r2} @ push old task's pc - stmfd sp!, {r4-r12,lr} @ push old task's lr,r12-r4 - mov r4, r1 @ Special optimised code below - mov r5, r3 - ldmfd r4!, {r0-r3} - stmfd sp!, {r0-r3} @ push old task's r3-r0 - stmfd sp!, {r5} @ push old task's psr - mrs r4, spsr - stmfd sp!, {r4} @ push old task's spsr - - ldr r4, =rt_interrupt_from_thread - ldr r5, [r4] - str sp, [r5] @ store sp in preempted tasks's TCB - - ldr r6, =rt_interrupt_to_thread - ldr r6, [r6] - ldr sp, [r6] @ get new task's stack pointer - - ldmfd sp!, {r4} @ pop new task's spsr - msr SPSR_cxsf, r4 - ldmfd sp!, {r4} @ pop new task's psr - msr CPSR_cxsf, r4 - - ldmfd sp!, {r0-r12,lr,pc} @ pop new task's r0-r12,lr & pc - -/* each mode stack memory */ -UNDSTACK_START: .word _undefined_stack_start + 128 -ABTSTACK_START: .word _abort_stack_start + 128 -FIQSTACK_START: .word _fiq_stack_start + 1024 -IRQSTACK_START: .word _irq_stack_start + 1024 -SVCSTACK_START: .word _svc_stack_start + 4096 - -stack_setup: - /* undefined instruction mode */ - msr cpsr_c, #UNDEFMODE|NOINT - ldr sp, UNDSTACK_START - - /* abort mode */ - msr cpsr_c, #ABORTMODE|NOINT - ldr sp, ABTSTACK_START - - /* FIQ mode */ - msr cpsr_c, #FIQMODE|NOINT - ldr sp, FIQSTACK_START - - /* IRQ mode */ - msr cpsr_c, #IRQMODE|NOINT - ldr sp, IRQSTACK_START - - /* supervisor mode */ - msr cpsr_c, #SVCMODE|NOINT - ldr sp, SVCSTACK_START - - mov pc,lr @ The LR register may be not valid for the mode changes. - -.globl led_on -led_on: - ldr r1, =0x1d20014 @ r1<-PDATC - ldr r0, [r1] @ r0<-[r1] - orr r0, r0, #0x0e @ r0=r0 or 0x0e - str r0, [r1] @ r0->[r1] - mov pc, lr - -.globl led_off -led_off: - ldr r1, =0x1d20010 @ r1<-PCONC - ldr r0, =0x5f555555 @ r0<-0x5f555555 - str r0, [r1] @ r0->[r1] - - ldr r1, =0x1d20014 @ r1<-PDATC - ldr r0, =0x0 @ r0<-00 - str r0, [r1] @ r0->[r1] - - mov pc, lr diff --git a/rt-thread/libcpu/arm/s3c44b0/start_rvds.S b/rt-thread/libcpu/arm/s3c44b0/start_rvds.S deleted file mode 100644 index b5c9048..0000000 --- a/rt-thread/libcpu/arm/s3c44b0/start_rvds.S +++ /dev/null @@ -1,1072 +0,0 @@ -;/*****************************************************************************/ -;/* S3C44B0X.S: Startup file for Samsung S3C44B0X */ -;/*****************************************************************************/ -;/* <<< Use Configuration Wizard in Context Menu >>> */ -;/*****************************************************************************/ -;/* This file is part of the uVision/ARM development tools. */ -;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ -;/* This software may only be used under the terms of a valid, current, */ -;/* end user licence from KEIL for a compatible version of KEIL software */ -;/* development tools. Nothing else gives you the right to use this software. */ -;/*****************************************************************************/ - - -; *** Startup Code (executed after Reset) *** - - -; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled - - -;// Stack Configuration (Stack Sizes in Bytes) -;// Undefined Mode <0x0-0xFFFFFFFF:8> -;// Supervisor Mode <0x0-0xFFFFFFFF:8> -;// Abort Mode <0x0-0xFFFFFFFF:8> -;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> -;// Interrupt Mode <0x0-0xFFFFFFFF:8> -;// User/System Mode <0x0-0xFFFFFFFF:8> -;// - -UND_Stack_Size EQU 0x00000000 -SVC_Stack_Size EQU 0x00000100 -ABT_Stack_Size EQU 0x00000000 -FIQ_Stack_Size EQU 0x00000000 -IRQ_Stack_Size EQU 0x00000100 -USR_Stack_Size EQU 0x00000100 - -ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - -Stack_Mem SPACE USR_Stack_Size -__initial_sp SPACE ISR_Stack_Size -Stack_Top - - -;// Heap Configuration -;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> -;// - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - -; CPU Wrapper and Bus Priorities definitions -CPUW_BASE EQU 0x01C00000 ; CPU Wrapper Base Address -SYSCFG_OFS EQU 0x00 ; SYSCFG Offset -NCACHBE0_OFS EQU 0x04 ; NCACHBE0 Offset -NCACHBE1_OFS EQU 0x08 ; NCACHBE0 Offset -BUSP_BASE EQU 0x01C40000 ; Bus Priority Base Address -SBUSCON_OFS EQU 0x00 ; SBUSCON Offset - -;// CPU Wrapper and Bus Priorities -;// CPU Wrapper -;// SE: Stall Enable -;// CM: Cache Mode -;// <0=> Disable Cache (8kB SRAM) -;// <1=> Half Cache Enable (4kB Cache, 4kB SRAM) -;// <2=> Reserved -;// <3=> Full Cache Enable (8kB Cache) -;// WE: Write Buffer Enable -;// RSE: Read Stall Enable -;// DA: Data Abort <0=> Enable <1=> Disable -;// Non-cacheable Area 0 -;// Start Address <0x0-0x0FFFF000:0x1000><#/0x1000> -;// SA = (Start Address) / 4k -;// End Address + 1 <0x0-0x10000000:0x1000><#/0x1000> -;// SE = (End Address + 1) / 4k -;// -;// Non-cacheable Area 1 -;// Start Address <0x0-0x0FFFF000:0x1000><#/0x1000> -;// SA = (Start Address) / 4k -;// End Address + 1 <0x0-0x10000000:0x1000><#/0x1000> -;// SE = (End Address + 1) / 4k -;// -;// -;// Bus Priorities -;// FIX: Fixed Priorities -;// LCD_DMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th -;// ZDMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th -;// BDMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th -;// nBREQ <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th -;// -;// -SYS_SETUP EQU 0 -SYSCFG_Val EQU 0x00000001 -NCACHBE0_Val EQU 0x00000000 -NCACHBE1_Val EQU 0x00000000 -SBUSCON_Val EQU 0x80001B1B - - -;// Vectored Interrupt Mode (for IRQ) -;// EINT0 External Interrupt 0 -;// EINT1 External Interrupt 1 -;// EINT2 External Interrupt 2 -;// EINT3 External Interrupt 3 -;// EINT4567 External Interrupt 4/5/6/7 -;// TICK RTC Time Tick Interrupt -;// ZDMA0 General DMA0 Interrupt -;// ZDMA1 General DMA1 Interrupt -;// BDMA0 Bridge DMA0 Interrupt -;// BDMA1 Bridge DMA1 Interrupt -;// WDT Watchdog Timer Interrupt -;// UERR01 UART0/1 Error Interrupt -;// TIMER0 Timer0 Interrupt -;// TIMER1 Timer1 Interrupt -;// TIMER2 Timer2 Interrupt -;// TIMER3 Timer3 Interrupt -;// TIMER4 Timer4 Interrupt -;// TIMER5 Timer5 Interrupt -;// URXD0 UART0 Rx Interrupt -;// URXD1 UART1 Rx Interrupt -;// IIC IIC Interrupt -;// SIO SIO Interrupt -;// UTXD0 UART0 Tx Interrupt -;// UTXD1 UART1 Tx Interrupt -;// RTC RTC Alarm Interrupt -;// ADC ADC EOC Interrupt -;// -VIM_SETUP EQU 0 -VIM_CFG EQU 0x00000000 - - -; Clock Management definitions -CLK_BASE EQU 0x01D80000 ; Clock Base Address -PLLCON_OFS EQU 0x00 ; PLLCON Offset -CLKCON_OFS EQU 0x04 ; CLKCON Offset -CLKSLOW_OFS EQU 0x08 ; CLKSLOW Offset -LOCKTIME_OFS EQU 0x0C ; LOCKTIME Offset - -;// Clock Management -;// PLL Settings -;// Fpllo = (m * Fin) / (p * 2^s), 20MHz < Fpllo < 66MHz -;// MDIV: Main divider <0x0-0xFF> -;// m = MDIV + 8 -;// PDIV: Pre-divider <0x0-0x3F> -;// p = PDIV + 2, 1MHz <= Fin/p < 2MHz -;// SDIV: Post Divider <0x0-0x03> -;// s = SDIV, Fpllo * 2^s < 170MHz -;// LTIME CNT: PLL Lock Time Count <0x0-0x0FFF> -;// -;// Master Clock -;// PLL Clock: Fout = Fpllo -;// Slow Clock: Fout = Fin / (2 * SLOW_VAL), SLOW_VAL > 0 -;// Slow Clock: Fout = Fin, SLOW_VAL = 0 -;// PLL_OFF: PLL Off -;// PLL is turned Off only when SLOW_BIT = 1 -;// SLOW_BIT: Slow Clock -;// SLOW_VAL: Slow Clock divider <0x0-0x0F> -;// -;// Clock Generation -;// IIS <0=> Disable <1=> Enable -;// IIC <0=> Disable <1=> Enable -;// ADC <0=> Disable <1=> Enable -;// RTC <0=> Disable <1=> Enable -;// GPIO <0=> Disable <1=> Enable -;// UART1 <0=> Disable <1=> Enable -;// UART0 <0=> Disable <1=> Enable -;// BDMA0,1 <0=> Disable <1=> Enable -;// LCDC <0=> Disable <1=> Enable -;// SIO <0=> Disable <1=> Enable -;// ZDMA0,1 <0=> Disable <1=> Enable -;// PWMTIMER <0=> Disable <1=> Enable -;// -;// -CLK_SETUP EQU 1 -PLLCON_Val EQU 0x00038080 -CLKCON_Val EQU 0x00007FF8 -CLKSLOW_Val EQU 0x00000009 -LOCKTIME_Val EQU 0x00000FFF - - -; Watchdog Timer definitions -WT_BASE EQU 0x01D30000 ; WT Base Address -WTCON_OFS EQU 0x00 ; WTCON Offset -WTDAT_OFS EQU 0x04 ; WTDAT Offset -WTCNT_OFS EQU 0x08 ; WTCNT Offset - -;// Watchdog Timer -;// Watchdog Timer Enable/Disable -;// Reset Enable/Disable -;// Interrupt Enable/Disable -;// Clock Select -;// <0=> 1/16 <1=> 1/32 <2=> 1/64 <3=> 1/128 -;// Clock Division Factor -;// Prescaler Value <0x0-0xFF> -;// Time-out Value <0x0-0xFFFF> -;// -WT_SETUP EQU 1 -WTCON_Val EQU 0x00008000 -WTDAT_Val EQU 0x00008000 - - -; Memory Controller definitions -MC_BASE EQU 0x01C80000 ; Memory Controller Base Address - -;// Memory Controller -MC_SETUP EQU 1 - -;// Bank 0 -;// PMC: Page Mode Configuration -;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data -;// Tpac: Page Mode Access Cycle -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks -;// Tcah: Address Holding Time after nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Toch: Chip Select Hold on nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacc: Access Cycle -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks -;// Tcos: Chip Select Set-up nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacs: Address Set-up before nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// -;// -;// Bank 1 -;// DW: Data Bus Width -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd -;// WS: WAIT Status -;// <0=> WAIT Disable -;// <1=> WAIT Enable -;// ST: SRAM Type -;// <0=> Not using UB/LB -;// <1=> Using UB/LB -;// PMC: Page Mode Configuration -;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data -;// Tpac: Page Mode Access Cycle -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks -;// Tcah: Address Holding Time after nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Toch: Chip Select Hold on nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacc: Access Cycle -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks -;// Tcos: Chip Select Set-up nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacs: Address Set-up before nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// -;// -;// Bank 2 -;// DW: Data Bus Width -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd -;// WS: WAIT Status -;// <0=> WAIT Disable -;// <1=> WAIT Enable -;// ST: SRAM Type -;// <0=> Not using UB/LB -;// <1=> Using UB/LB -;// PMC: Page Mode Configuration -;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data -;// Tpac: Page Mode Access Cycle -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks -;// Tcah: Address Holding Time after nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Toch: Chip Select Hold on nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacc: Access Cycle -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks -;// Tcos: Chip Select Set-up nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacs: Address Set-up before nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// -;// -;// Bank 3 -;// DW: Data Bus Width -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd -;// WS: WAIT Status -;// <0=> WAIT Disable -;// <1=> WAIT Enable -;// ST: SRAM Type -;// <0=> Not using UB/LB -;// <1=> Using UB/LB -;// PMC: Page Mode Configuration -;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data -;// Tpac: Page Mode Access Cycle -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks -;// Tcah: Address Holding Time after nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Toch: Chip Select Hold on nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacc: Access Cycle -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks -;// Tcos: Chip Select Set-up nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacs: Address Set-up before nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// -;// -;// Bank 4 -;// DW: Data Bus Width -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd -;// WS: WAIT Status -;// <0=> WAIT Disable -;// <1=> WAIT Enable -;// ST: SRAM Type -;// <0=> Not using UB/LB -;// <1=> Using UB/LB -;// PMC: Page Mode Configuration -;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data -;// Tpac: Page Mode Access Cycle -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks -;// Tcah: Address Holding Time after nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Toch: Chip Select Hold on nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacc: Access Cycle -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks -;// Tcos: Chip Select Set-up nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacs: Address Set-up before nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// -;// -;// Bank 5 -;// DW: Data Bus Width -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd -;// WS: WAIT Status -;// <0=> WAIT Disable -;// <1=> WAIT Enable -;// ST: SRAM Type -;// <0=> Not using UB/LB -;// <1=> Using UB/LB -;// PMC: Page Mode Configuration -;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data -;// Tpac: Page Mode Access Cycle -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks -;// Tcah: Address Holding Time after nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Toch: Chip Select Hold on nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacc: Access Cycle -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks -;// Tcos: Chip Select Set-up nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacs: Address Set-up before nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// -;// -;// Bank 6 -;// BK76MAP: Bank 6/7 Memory Map -;// <0=> 32M <4=> 2M <5=> 4M <6=> 8M <7=> 16M -;// DW: Data Bus Width -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd -;// WS: WAIT Status -;// <0=> WAIT Disable -;// <1=> WAIT Enable -;// ST: SRAM Type -;// <0=> Not using UB/LB -;// <1=> Using UB/LB -;// MT: Memory Type -;// <0=> ROM or SRAM -;// <1=> FP DRAMP -;// <2=> EDO DRAM -;// <3=> SDRAM -;// ROM or SRAM -;// PMC: Page Mode Configuration -;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data -;// Tpac: Page Mode Access Cycle -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks -;// Tcah: Address Holding Time after nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Toch: Chip Select Hold on nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacc: Access Cycle -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks -;// Tcos: Chip Select Set-up nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacs: Address Set-up before nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// -;// FP DRAM or EDO DRAM -;// CAN: Columnn Address Number -;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> 11-bit -;// Tcp: CAS Pre-charge -;// <0=> 1 clk <1=> 2 clks -;// Tcas: CAS Pulse Width -;// <0=> 1 clk <1=> 2 clks -;// Trcd: RAS to CAS Delay -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// -;// SDRAM -;// SCAN: Columnn Address Number -;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> Rsrvd -;// Trcd: RAS to CAS Delay -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> Rsrvd -;// SCLKEN: SCLK Selection (Bank 6/7) -;// <0=> Normal -;// <1=> Reduced Power -;// BL: Burst Length -;// <0=> 1 -;// BT: Burst Type -;// <0=> Sequential -;// CL: CAS Latency -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks -;// TM: Test Mode -;// <0=> Mode Register Set -;// WBL: Write Burst Length -;// <0=> 0 -;// -;// -;// -;// Bank 7 -;// BK76MAP: Bank 6/7 Memory Map -;// <0=> 32M <4=> 2M <5=> 4M <6=> 8M <7=> 16M -;// DW: Data Bus Width -;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd -;// WS: WAIT Status -;// <0=> WAIT Disable -;// <1=> WAIT Enable -;// ST: SRAM Type -;// <0=> Not using UB/LB -;// <1=> Using UB/LB -;// MT: Memory Type -;// <0=> ROM or SRAM -;// <1=> FP DRAMP -;// <2=> EDO DRAM -;// <3=> SDRAM -;// ROM or SRAM -;// PMC: Page Mode Configuration -;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data -;// Tpac: Page Mode Access Cycle -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks -;// Tcah: Address Holding Time after nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Toch: Chip Select Hold on nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacc: Access Cycle -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks -;// Tcos: Chip Select Set-up nOE -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// Tacs: Address Set-up before nGCSn -;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks -;// -;// FP DRAM or EDO DRAM -;// CAN: Columnn Address Number -;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> 11-bit -;// Tcp: CAS Pre-charge -;// <0=> 1 clk <1=> 2 clks -;// Tcas: CAS Pulse Width -;// <0=> 1 clk <1=> 2 clks -;// Trcd: RAS to CAS Delay -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// -;// SDRAM -;// SCAN: Columnn Address Number -;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> Rsrvd -;// Trcd: RAS to CAS Delay -;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> Rsrvd -;// SCLKEN: SCLK Selection (Bank 6/7) -;// <0=> Normal -;// <1=> Reduced Power -;// BL: Burst Length -;// <0=> 1 -;// BT: Burst Type -;// <0=> Sequential -;// CL: CAS Latency -;// <0=> 1 clk <1=> 2 clks <2=> 3 clks -;// TM: Test Mode -;// <0=> Mode Register Set -;// WBL: Write Burst Length -;// <0=> 0 -;// -;// -;// -;// Refresh -;// REFEN: DRAM/SDRAM Refresh -;// <0=> Disable <1=> Enable -;// TREFMD: DRAM/SDRAM Refresh Mode -;// <0=> CBR/Auto Refresh -;// <1=> Self Refresh -;// Trp: DRAM/SDRAM RAS Pre-charge Time -;// <0=> 1.5 clks (DRAM) / 2 clks (SDRAM) -;// <1=> 2.5 clks (DRAM) / 3 clks (SDRAM) -;// <2=> 3.5 clks (DRAM) / 4 clks (SDRAM) -;// <3=> 4.5 clks (DRAM) / Rsrvd (SDRAM) -;// Trc: SDRAM RC Min Time -;// <0=> 4 clks <1=> 5 clks <2=> 6 clks <3=> 7 clks -;// Tchr: DRAM CAS Hold Time -;// <0=> 1 clks <1=> 2 clks <2=> 3 clks <3=> 4 clks -;// Refresh Counter <0x0-0x07FF> -;// Refresh Period = (2^11 - Refresh Count + 1) / MCLK -;// -BANKCON0_Val EQU 0x00000700 -BANKCON1_Val EQU 0x00000700 -BANKCON2_Val EQU 0x00000700 -BANKCON3_Val EQU 0x00000700 -BANKCON4_Val EQU 0x00000700 -BANKCON5_Val EQU 0x00000700 -BANKCON6_Val EQU 0x00018008 -BANKCON7_Val EQU 0x00018008 -BWSCON_Val EQU 0x00000000 -REFRESH_Val EQU 0x00AC0000 -BANKSIZE_Val EQU 0x00000000 -MRSRB6_Val EQU 0x00000000 -MRSRB7_Val EQU 0x00000000 - -;// End of MC - - -; I/O Ports definitions -PIO_BASE EQU 0x01D20000 ; PIO Base Address -PCONA_OFS EQU 0x00 ; PCONA Offset -PCONB_OFS EQU 0x08 ; PCONB Offset -PCONC_OFS EQU 0x10 ; PCONC Offset -PCOND_OFS EQU 0x1C ; PCOND Offset -PCONE_OFS EQU 0x28 ; PCONE Offset -PCONF_OFS EQU 0x34 ; PCONF Offset -PCONG_OFS EQU 0x40 ; PCONG Offset -PUPC_OFS EQU 0x18 ; PUPC Offset -PUPD_OFS EQU 0x24 ; PUPD Offset -PUPE_OFS EQU 0x30 ; PUPE Offset -PUPF_OFS EQU 0x3C ; PUPF Offset -PUPG_OFS EQU 0x48 ; PUPG Offset -SPUCR_OFS EQU 0x4C ; SPUCR Offset - -;// I/O Configuration -PIO_SETUP EQU 0 - -;// Port A -;// PA0 <0=> Output <1=> ADDR0 -;// PA1 <0=> Output <1=> ADDR16 -;// PA2 <0=> Output <1=> ADDR17 -;// PA3 <0=> Output <1=> ADDR18 -;// PA4 <0=> Output <1=> ADDR19 -;// PA5 <0=> Output <1=> ADDR20 -;// PA6 <0=> Output <1=> ADDR21 -;// PA7 <0=> Output <1=> ADDR22 -;// PA8 <0=> Output <1=> ADDR23 -;// PA9 <0=> Output <1=> ADDR24 -;// -PIOA_SETUP EQU 1 -PCONA_Val EQU 0x000003FF - -;// Port B -;// PB0 <0=> Output <1=> SCKE -;// PB1 <0=> Output <1=> CKLK -;// PB2 <0=> Output <1=> nSCAS/nCAS2 -;// PB3 <0=> Output <1=> nSRAS/nCAS3 -;// PB4 <0=> Output <1=> nWBE2/nBE2/DQM2 -;// PB5 <0=> Output <1=> nWBE3/nBE3/DQM3 -;// PB6 <0=> Output <1=> nGCS1 -;// PB7 <0=> Output <1=> nGCS2 -;// PB8 <0=> Output <1=> nGCS3 -;// PB9 <0=> Output <1=> nGCS4 -;// PB10 <0=> Output <1=> nGCS5 -;// -PIOB_SETUP EQU 1 -PCONB_Val EQU 0x000007FF - -;// Port C -;// PC0 <0=> Input <1=> Output <2=> DATA16 <3=> IISLRCK -;// PC1 <0=> Input <1=> Output <2=> DATA17 <3=> IISDO -;// PC2 <0=> Input <1=> Output <2=> DATA18 <3=> IISDI -;// PC3 <0=> Input <1=> Output <2=> DATA19 <3=> IISCLK -;// PC4 <0=> Input <1=> Output <2=> DATA20 <3=> VD7 -;// PC5 <0=> Input <1=> Output <2=> DATA21 <3=> VD6 -;// PC6 <0=> Input <1=> Output <2=> DATA22 <3=> VD5 -;// PC7 <0=> Input <1=> Output <2=> DATA23 <3=> VD4 -;// PC8 <0=> Input <1=> Output <2=> DATA24 <3=> nXDACK1 -;// PC9 <0=> Input <1=> Output <2=> DATA25 <3=> nXDREQ1 -;// PC10 <0=> Input <1=> Output <2=> DATA26 <3=> nRTS1 -;// PC11 <0=> Input <1=> Output <2=> DATA27 <3=> nCTS1 -;// PC12 <0=> Input <1=> Output <2=> DATA28 <3=> TxD1 -;// PC13 <0=> Input <1=> Output <2=> DATA29 <3=> RxD1 -;// PC14 <0=> Input <1=> Output <2=> DATA30 <3=> nRTS0 -;// PC15 <0=> Input <1=> Output <2=> DATA31 <3=> nCTS0 -;// Pull-up Resistors -;// PC0 Pull-up <0=> Enabled <1=> Disabled -;// PC1 Pull-up <0=> Enabled <1=> Disabled -;// PC2 Pull-up <0=> Enabled <1=> Disabled -;// PC3 Pull-up <0=> Enabled <1=> Disabled -;// PC4 Pull-up <0=> Enabled <1=> Disabled -;// PC5 Pull-up <0=> Enabled <1=> Disabled -;// PC6 Pull-up <0=> Enabled <1=> Disabled -;// PC7 Pull-up <0=> Enabled <1=> Disabled -;// PC8 Pull-up <0=> Enabled <1=> Disabled -;// PC9 Pull-up <0=> Enabled <1=> Disabled -;// PC10 Pull-up <0=> Enabled <1=> Disabled -;// PC11 Pull-up <0=> Enabled <1=> Disabled -;// PC12 Pull-up <0=> Enabled <1=> Disabled -;// PC13 Pull-up <0=> Enabled <1=> Disabled -;// PC14 Pull-up <0=> Enabled <1=> Disabled -;// PC15 Pull-up <0=> Enabled <1=> Disabled -;// -;// -PIOC_SETUP EQU 1 -PCONC_Val EQU 0xAAAAAAAA -PUPC_Val EQU 0x00000000 - -;// Port D -;// PD0 <0=> Input <1=> Output <2=> VD0 <3=> Reserved -;// PD1 <0=> Input <1=> Output <2=> VD1 <3=> Reserved -;// PD2 <0=> Input <1=> Output <2=> VD2 <3=> Reserved -;// PD3 <0=> Input <1=> Output <2=> VD3 <3=> Reserved -;// PD4 <0=> Input <1=> Output <2=> VCLK <3=> Reserved -;// PD5 <0=> Input <1=> Output <2=> VLINE <3=> Reserved -;// PD6 <0=> Input <1=> Output <2=> VM <3=> Reserved -;// PD7 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved -;// Pull-up Resistors -;// PD0 Pull-up <0=> Enabled <1=> Disabled -;// PD1 Pull-up <0=> Enabled <1=> Disabled -;// PD2 Pull-up <0=> Enabled <1=> Disabled -;// PD3 Pull-up <0=> Enabled <1=> Disabled -;// PD4 Pull-up <0=> Enabled <1=> Disabled -;// PD5 Pull-up <0=> Enabled <1=> Disabled -;// PD6 Pull-up <0=> Enabled <1=> Disabled -;// PD7 Pull-up <0=> Enabled <1=> Disabled -;// -;// -PIOD_SETUP EQU 1 -PCOND_Val EQU 0x00000000 -PUPD_Val EQU 0x00000000 - -;// Port E -;// PE0 <0=> Input <1=> Output <2=> Fpllo <3=> Fout -;// PE1 <0=> Input <1=> Output <2=> TxD0 <3=> Reserved -;// PE2 <0=> Input <1=> Output <2=> RxD0 <3=> Reserved -;// PE3 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved -;// PE4 <0=> Input <1=> Output <2=> TOUT1 <3=> TCLK -;// PE5 <0=> Input <1=> Output <2=> TOUT2 <3=> TCLK -;// PE6 <0=> Input <1=> Output <2=> TOUT3 <3=> VD6 -;// PE7 <0=> Input <1=> Output <2=> TOUT4 <3=> VD7 -;// PE8 <0=> Input <1=> Output <2=> CODECLK <3=> Reserved -;// Pull-up Resistors -;// PE0 Pull-up <0=> Enabled <1=> Disabled -;// PE1 Pull-up <0=> Enabled <1=> Disabled -;// PE2 Pull-up <0=> Enabled <1=> Disabled -;// PE3 Pull-up <0=> Enabled <1=> Disabled -;// PE4 Pull-up <0=> Enabled <1=> Disabled -;// PE5 Pull-up <0=> Enabled <1=> Disabled -;// PE6 Pull-up <0=> Enabled <1=> Disabled -;// PE7 Pull-up <0=> Enabled <1=> Disabled -;// PE8 Pull-up <0=> Enabled <1=> Disabled -;// -;// -PIOE_SETUP EQU 1 -PCONE_Val EQU 0x00000000 -PUPE_Val EQU 0x00000000 - -;// Port F -;// PF0 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved -;// PF1 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved -;// PF2 <0=> Input <1=> Output <2=> nWAIT <3=> Reserved -;// PF3 <0=> Input <1=> Output <2=> nXBACK <3=> nXDACK0 -;// PF4 <0=> Input <1=> Output <2=> nXBREQ <3=> nXDREQ0 -;// PF5 <0=> Input <1=> Output <2=> nRTS1 <3=> SIOTxD -;// <4=> IISLRCK <5=> Reserved <6=> Reserved <7=> Reserved -;// PF6 <0=> Input <1=> Output <2=> TxD1 <3=> SIORDY -;// <4=> IISDO <5=> Reserved <6=> Reserved <7=> Reserved -;// PF7 <0=> Input <1=> Output <2=> RxD1 <3=> SIORxD -;// <4=> IISDI <5=> Reserved <6=> Reserved <7=> Reserved -;// PF8 <0=> Input <1=> Output <2=> nCTS1 <3=> SIOCLK -;// <4=> IISCLK <5=> Reserved <6=> Reserved <7=> Reserved -;// Pull-up Resistors -;// PF0 Pull-up <0=> Enabled <1=> Disabled -;// PF1 Pull-up <0=> Enabled <1=> Disabled -;// PF2 Pull-up <0=> Enabled <1=> Disabled -;// PF3 Pull-up <0=> Enabled <1=> Disabled -;// PF4 Pull-up <0=> Enabled <1=> Disabled -;// PF5 Pull-up <0=> Enabled <1=> Disabled -;// PF6 Pull-up <0=> Enabled <1=> Disabled -;// PF7 Pull-up <0=> Enabled <1=> Disabled -;// PF8 Pull-up <0=> Enabled <1=> Disabled -;// -;// -PIOF_SETUP EQU 1 -PCONF_Val EQU 0x00000000 -PUPF_Val EQU 0x00000000 - -;// Port G -;// PG0 <0=> Input <1=> Output <2=> VD4 <3=> EINT0 -;// PG1 <0=> Input <1=> Output <2=> VD5 <3=> EINT1 -;// PG2 <0=> Input <1=> Output <2=> nCTS0 <3=> EINT2 -;// PG3 <0=> Input <1=> Output <2=> nRTS0 <3=> EINT3 -;// PG4 <0=> Input <1=> Output <2=> IISCLK <3=> EINT4 -;// PG5 <0=> Input <1=> Output <2=> IISDI <3=> EINT5 -;// PG6 <0=> Input <1=> Output <2=> IISDO <3=> EINT6 -;// PG7 <0=> Input <1=> Output <2=> IISLRCK <3=> EINT7 -;// Pull-up Resistors -;// PG0 Pull-up <0=> Enabled <1=> Disabled -;// PG1 Pull-up <0=> Enabled <1=> Disabled -;// PG2 Pull-up <0=> Enabled <1=> Disabled -;// PG3 Pull-up <0=> Enabled <1=> Disabled -;// PG4 Pull-up <0=> Enabled <1=> Disabled -;// PG5 Pull-up <0=> Enabled <1=> Disabled -;// PG6 Pull-up <0=> Enabled <1=> Disabled -;// PG7 Pull-up <0=> Enabled <1=> Disabled -;// -;// -PIOG_SETUP EQU 1 -PCONG_Val EQU 0x00000000 -PUPG_Val EQU 0x00000000 - -;// Special Pull-up -;// SPUCR0: DATA[7:0] Pull-up Resistor -;// <0=> Enabled <1=> Disabled -;// SPUCR1: DATA[15:8] Pull-up Resistor -;// <0=> Enabled <1=> Disabled -;// HZ@STOP -;// <0=> Prevoius state of PAD -;// <1=> HZ @ Stop -;// -PSPU_SETUP EQU 1 -SPUCR_Val EQU 0x00000004 - -;// - - - PRESERVE8 - - -; Area Definition and Entry Point -; Startup Code must be linked first at Address at which it expects to run. - - AREA RESET, CODE, READONLY - ARM - - -; Exception Vectors -; Mapped to Address 0. -; Absolute addressing mode must be used. -; Dummy Handlers are implemented as infinite loops which can be modified. - -Vectors LDR PC, Reset_Addr - LDR PC, Undef_Addr - LDR PC, SWI_Addr - LDR PC, PAbt_Addr - LDR PC, DAbt_Addr - NOP ; Reserved Vector - LDR PC, IRQ_Addr - LDR PC, FIQ_Addr - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SWI_Addr DCD SWI_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler - DCD 0 ; Reserved Address -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - -Undef_Handler B Undef_Handler -SWI_Handler B SWI_Handler -PAbt_Handler B PAbt_Handler -DAbt_Handler B DAbt_Handler -FIQ_Handler B FIQ_Handler - - -; CPU Wrapper and Bus Priorities Configuration - IF SYS_SETUP <> 0 -SYS_CFG - DCD CPUW_BASE - DCD BUSP_BASE - DCD SYSCFG_Val - DCD NCACHBE0_Val - DCD NCACHBE1_Val - DCD SBUSCON_Val - ENDIF - - -; Memory Controller Configuration - IF MC_SETUP <> 0 -MC_CFG - DCD BWSCON_Val - DCD BANKCON0_Val - DCD BANKCON1_Val - DCD BANKCON2_Val - DCD BANKCON3_Val - DCD BANKCON4_Val - DCD BANKCON5_Val - DCD BANKCON6_Val - DCD BANKCON7_Val - DCD REFRESH_Val - DCD BANKSIZE_Val - DCD MRSRB6_Val - DCD MRSRB7_Val - ENDIF - - -; Clock Management Configuration - IF CLK_SETUP <> 0 -CLK_CFG - DCD CLK_BASE - DCD PLLCON_Val - DCD CLKCON_Val - DCD CLKSLOW_Val - DCD LOCKTIME_Val - ENDIF - - -; I/O Configuration - IF PIO_SETUP <> 0 -PIO_CFG - DCD PCONA_Val - DCD PCONB_Val - DCD PCONC_Val - DCD PCOND_Val - DCD PCONE_Val - DCD PCONF_Val - DCD PCONG_Val - DCD PUPC_Val - DCD PUPD_Val - DCD PUPE_Val - DCD PUPF_Val - DCD PUPG_Val - DCD SPUCR_Val - ENDIF - - -; Reset Handler - - EXPORT Reset_Handler -Reset_Handler - - - IF SYS_SETUP <> 0 - ADR R8, SYS_CFG - LDMIA R8, {R0-R5} - STMIA R0, {R2-R4} - STR R5, [R1] - ENDIF - - - IF MC_SETUP <> 0 - ADR R14, MC_CFG - LDMIA R14, {R0-R12} - LDR R14, =MC_BASE - STMIA R14, {R0-R12} - ENDIF - - - IF CLK_SETUP <> 0 - ADR R8, CLK_CFG - LDMIA R8, {R0-R4} - STR R4, [R0, #LOCKTIME_OFS] - STR R1, [R0, #PLLCON_OFS] - STR R3, [R0, #CLKSLOW_OFS] - STR R2, [R0, #CLKCON_OFS] - ENDIF - - - IF WT_SETUP <> 0 - LDR R0, =WT_BASE - LDR R1, =WTCON_Val - LDR R2, =WTDAT_Val - STR R2, [R0, #WTCNT_OFS] - STR R2, [R0, #WTDAT_OFS] - STR R1, [R0, #WTCON_OFS] - ENDIF - - - IF PIO_SETUP <> 0 - ADR R14, PIO_CFG - LDMIA R14, {R0-R12} - LDR R14, =PIO_BASE - - IF PIOA_SETUP <> 0 - STR R0, [R14, #PCONA_OFS] - ENDIF - - IF PIOB_SETUP <> 0 - STR R1, [R14, #PCONB_OFS] - ENDIF - - IF PIOC_SETUP <> 0 - STR R2, [R14, #PCONC_OFS] - STR R7, [R14, #PUPC_OFS] - ENDIF - - IF PIOD_SETUP <> 0 - STR R3, [R14, #PCOND_OFS] - STR R8, [R14, #PUPD_OFS] - ENDIF - - IF PIOE_SETUP <> 0 - STR R4, [R14, #PCONE_OFS] - STR R9, [R14, #PUPE_OFS] - ENDIF - - IF PIOF_SETUP <> 0 - STR R5, [R14, #PCONF_OFS] - STR R10,[R14, #PUPF_OFS] - ENDIF - - IF PIOG_SETUP <> 0 - STR R6, [R14, #PCONG_OFS] - STR R11,[R14, #PUPG_OFS] - ENDIF - - IF PSPU_SETUP <> 0 - STR R12,[R14, #SPUCR_OFS] - ENDIF - - ENDIF - - -; Setup Stack for each mode - - LDR R0, =Stack_Top - -; Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #UND_Stack_Size - -; Enter Abort Mode and set its Stack Pointer - MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #ABT_Stack_Size - -; Enter FIQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #FIQ_Stack_Size - -; Enter IRQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #IRQ_Stack_Size - -; Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #SVC_Stack_Size - -; Enter User Mode and set its Stack Pointer - ; MSR CPSR_c, #Mode_USR - IF :DEF:__MICROLIB - - EXPORT __initial_sp - - ELSE - - ; MOV SP, R0 - ; SUB SL, SP, #USR_Stack_Size - - ENDIF - - -; Enter the C code - - IMPORT __main - LDR R0, =__main - BX R0 - - IMPORT rt_interrupt_enter - IMPORT rt_interrupt_leave - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - IMPORT rt_hw_trap_irq - -IRQ_Handler PROC - EXPORT IRQ_Handler - STMFD sp!, {r0-r12,lr} - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; if rt_thread_switch_interrupt_flag set, jump to - ; rt_hw_context_switch_interrupt_do and don't return - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD sp!, {r0-r12,lr} - SUBS pc, lr, #4 - ENDP - -; /* -; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) -; */ -rt_hw_context_switch_interrupt_do PROC - EXPORT rt_hw_context_switch_interrupt_do - MOV r1, #0 ; clear flag - STR r1, [r0] - - LDMFD sp!, {r0-r12,lr}; reload saved registers - STMFD sp!, {r0-r3} ; save r0-r3 - MOV r1, sp - ADD sp, sp, #16 ; restore sp - SUB r2, lr, #4 ; save old task's pc to r2 - - MRS r3, spsr ; get cpsr of interrupt thread - - ; switch to SVC mode and no interrupt - MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC - - STMFD sp!, {r2} ; push old task's pc - STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 - MOV r4, r1 ; Special optimised code below - MOV r5, r3 - LDMFD r4!, {r0-r3} - STMFD sp!, {r0-r3} ; push old task's r3-r0 - STMFD sp!, {r5} ; push old task's cpsr - MRS r4, spsr - STMFD sp!, {r4} ; push old task's spsr - - LDR r4, =rt_interrupt_from_thread - LDR r5, [r4] - STR sp, [r5] ; store sp in preempted tasks's TCB - - LDR r6, =rt_interrupt_to_thread - LDR r6, [r6] - LDR sp, [r6] ; get new task's stack pointer - - LDMFD sp!, {r4} ; pop new task's spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task's psr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc - ENDP - - IF :DEF:__MICROLIB - - EXPORT __heap_base - EXPORT __heap_limit - - ELSE -; User Initial Stack & Heap - AREA |.text|, CODE, READONLY - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + USR_Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDIF - - - END diff --git a/rt-thread/libcpu/arm/s3c44b0/trap.c b/rt-thread/libcpu/arm/s3c44b0/trap.c deleted file mode 100644 index 106a990..0000000 --- a/rt-thread/libcpu/arm/s3c44b0/trap.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-09-06 XuXinming first version - * 2006-09-15 Bernard modify rt_hw_trap_irq for more effective - */ - -#include -#include - -#include "s3c44b0.h" - -extern unsigned char interrupt_bank0[256]; -extern unsigned char interrupt_bank1[256]; -extern unsigned char interrupt_bank2[256]; -extern unsigned char interrupt_bank3[256]; - -extern struct rt_thread *rt_current_thread; - -/** - * @addtogroup S3C44B0 - */ -/*@{*/ - -/** - * this function will show registers of CPU - * - * @param regs the registers point - */ -void rt_hw_show_register (struct rt_hw_register *regs) -{ - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); -} - -/** - * When ARM7TDMI comes across an instruction which it cannot handle, - * it takes the undefined instruction trap. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_udef(struct rt_hw_register *regs) -{ - rt_hw_show_register(regs); - - rt_kprintf("undefined instruction\n"); - rt_hw_cpu_shutdown(); -} - -/** - * The software interrupt instruction (SWI) is used for entering - * Supervisor mode, usually to request a particular supervisor - * function. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_swi(struct rt_hw_register *regs) -{ - rt_kprintf("software interrupt\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during an instruction prefetch. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_pabt(struct rt_hw_register *regs) -{ - rt_hw_show_register(regs); - - rt_kprintf("prefetch abort\n"); - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during a data access. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_dabt(struct rt_hw_register *regs) -{ - rt_hw_show_register(regs); - - rt_kprintf("data abort\n"); - rt_hw_cpu_shutdown(); -} - -/** - * Normally, system will never reach here - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_resv(struct rt_hw_register *regs) -{ - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); -} - -extern rt_isr_handler_t isr_table[]; -void rt_hw_trap_irq() -{ - register unsigned long ispr, intstat; - register rt_isr_handler_t isr_func; - -#ifdef BSP_INT_DEBUG - rt_kprintf("irq coming, "); -#endif - intstat = I_ISPR & 0x7ffffff; -#ifdef BSP_INT_DEBUG - rt_kprintf("I_ISPR: %d\n", intstat); -#endif - - ispr = intstat; - - /* to find interrupt */ - if ( intstat & 0xff ) /* lowest 8bits */ - { - intstat = interrupt_bank0[intstat & 0xff]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else if ( intstat & 0xff00 ) /* low 8bits */ - { - intstat = interrupt_bank1[(intstat & 0xff00) >> 8]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else if ( intstat & 0xff0000 ) /* high 8bits */ - { - intstat = interrupt_bank2[(intstat & 0xff0000) >> 16]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else if ( intstat & 0xff000000 ) /* highest 8bits */ - { - intstat = interrupt_bank3[(intstat & 0xff000000) >> 24]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else return; - -#ifdef BSP_INT_DEBUG - rt_kprintf("irq: %d happen\n", intstat); -#endif - - /* turn to interrupt service routine */ - isr_func(intstat); - - I_ISPC = ispr; /* clear interrupt */ -} - -void rt_hw_trap_fiq() -{ - rt_kprintf("fast interrupt request\n"); -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/sep4020/SConscript b/rt-thread/libcpu/arm/sep4020/SConscript deleted file mode 100644 index b259a94..0000000 --- a/rt-thread/libcpu/arm/sep4020/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/sep4020/clk.c b/rt-thread/libcpu/arm/sep4020/clk.c deleted file mode 100644 index 031d310..0000000 --- a/rt-thread/libcpu/arm/sep4020/clk.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-20 zchong first version - */ - -#include -#include "sep4020.h" - -#define CLK_IN 4000000 /* Fin = 4.00MHz */ -#define SYSCLK 72000000 /* system clock we want */ - -#define CLK_ESRAM 0 -#define CLK_LCDC 1 -#define CLK_PWM 2 -#define CLK_DMAC 3 -#define CLK_EMI 4 -#define CLK_MMCSD 5 -#define CLK_SSI 7 -#define CLK_UART0 8 -#define CLK_UART1 9 -#define CLK_UART2 10 -#define CLK_UART3 11 -#define CLK_USB 12 -#define CLK_MAC 13 -#define CLK_SMC 14 -#define CLK_I2C 15 -#define CLK_GPT 16 - -static void rt_hw_set_system_clock(void) -{ - rt_uint8_t pv; - - /* pv value*/ - pv = SYSCLK/2/CLK_IN; - /* go to normal mode*/ - *(RP)PMU_PMDR = 0x01; - /* set the clock */ - *(RP)PMU_PMCR = 0x4000 | pv; - /* trige configurate*/ - *(RP)PMU_PMCR = 0xc000 | pv; -} - -static void rt_hw_set_usb_clock(void) -{ - /* set the clock */ - *(RP)PMU_PUCR = 0x000c; - /* trige configurate*/ - *(RP)PMU_PMCR = 0x800c; - -} - -/** - * @brief System Clock Configuration - */ -void rt_hw_clock_init(void) -{ - /* set system clock */ - rt_hw_set_system_clock(); - /* set usb clock */ - rt_hw_set_usb_clock(); -} - -/** - * @brief Get system clock - */ -rt_uint32_t rt_hw_get_clock(void) -{ - rt_uint32_t val; - rt_uint8_t pv, pd, npd; - - /* get PMCR value */ - val =*(RP) PMU_PMCR; - /* get NPD */ - npd = (val >> 14) & 0x01; - /* get PD */ - pd = (val >> 10) & 0x0f; - /* get PV */ - pv = val & 0x7f; - /* caculate the system clock */ - if(npd) - val = 2 * CLK_IN * pv; - else - val = CLK_IN * pv / (pd + 1); - - return(val); -} - -/** - * @brief Enable module clock - */ - void rt_hw_enable_module_clock(rt_uint8_t module) - { - - } - -/** - * @brief Disable module clock - */ - void rt_hw_disable_module_clock(rt_uint8_t module) - { - - } - diff --git a/rt-thread/libcpu/arm/sep4020/context_rvds.S b/rt-thread/libcpu/arm/sep4020/context_rvds.S deleted file mode 100644 index 5f61b86..0000000 --- a/rt-thread/libcpu/arm/sep4020/context_rvds.S +++ /dev/null @@ -1,103 +0,0 @@ -;/* -; * Copyright (c) 2006-2022, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2009-01-20 Bernard first version -; */ - -NOINT EQU 0xc0 ; disable interrupt in psr - - AREA |.text|, CODE, READONLY, ALIGN=2 - ARM - REQUIRE8 - PRESERVE8 - -;/* -; * rt_base_t rt_hw_interrupt_disable(); -; */ -rt_hw_interrupt_disable PROC - EXPORT rt_hw_interrupt_disable - MRS r0, cpsr - ORR r1, r0, #NOINT - MSR cpsr_c, r1 - BX lr - ENDP - -;/* -; * void rt_hw_interrupt_enable(rt_base_t level); -; */ -rt_hw_interrupt_enable PROC - EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0 - BX lr - ENDP - -;/* -; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); -; * r0 --> from -; * r1 --> to -; */ -rt_hw_context_switch PROC - EXPORT rt_hw_context_switch - STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC) - STMFD sp!, {r0-r12, lr} ; push lr & register file - - MRS r4, cpsr - STMFD sp!, {r4} ; push cpsr - MRS r4, spsr - STMFD sp!, {r4} ; push spsr - - STR sp, [r0] ; store sp in preempted tasks TCB - LDR sp, [r1] ; get new task stack pointer - - LDMFD sp!, {r4} ; pop new task spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task cpsr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP - -;/* -; * void rt_hw_context_switch_to(rt_uint32 to); -; * r0 --> to -; */ -rt_hw_context_switch_to PROC - EXPORT rt_hw_context_switch_to - LDR sp, [r0] ; get new task stack pointer - - LDMFD sp!, {r4} ; pop new task spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task cpsr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP - -;/* -; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); -; */ - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - -rt_hw_context_switch_interrupt PROC - EXPORT rt_hw_context_switch_interrupt - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1 - STR r3, [r2] - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] -_reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - BX lr - ENDP - - END diff --git a/rt-thread/libcpu/arm/sep4020/cpu.c b/rt-thread/libcpu/arm/sep4020/cpu.c deleted file mode 100644 index 2977f38..0000000 --- a/rt-thread/libcpu/arm/sep4020/cpu.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - */ - -#include -#include - -extern rt_base_t rt_hw_interrupt_disable(void); - -//TODO -#warning I DON'T KNOW IF THE MMU OPERATION WORKS ON SEP4020 - -/** - * @addtogroup S3C24X0 - */ -/*@{*/ - -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) - -#ifdef __GNUC__ -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); -} -#endif - -#ifdef __CC_ARM -rt_inline rt_uint32_t cp15_rd(void) -{ - rt_uint32_t i; - - __asm - { - mrc p15, 0, i, c1, c0, 0 - } - - return i; -} - -rt_inline void cache_enable(rt_uint32_t bit) -{ - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } -} - -rt_inline void cache_disable(rt_uint32_t bit) -{ - rt_uint32_t value; - - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } -} -#endif - -/** - * enable I-Cache - * - */ -void rt_hw_cpu_icache_enable() -{ - cache_enable(ICACHE_MASK); -} - -/** - * disable I-Cache - * - */ -void rt_hw_cpu_icache_disable() -{ - cache_disable(ICACHE_MASK); -} - -/** - * return the status of I-Cache - * - */ -rt_base_t rt_hw_cpu_icache_status() -{ - return (cp15_rd() & ICACHE_MASK); -} - -/** - * enable D-Cache - * - */ -void rt_hw_cpu_dcache_enable() -{ - cache_enable(DCACHE_MASK); -} - -/** - * disable D-Cache - * - */ -void rt_hw_cpu_dcache_disable() -{ - cache_disable(DCACHE_MASK); -} - -/** - * return the status of D-Cache - * - */ -rt_base_t rt_hw_cpu_dcache_status() -{ - return (cp15_rd() & DCACHE_MASK); -} - -/** - * reset cpu by dog's time-out - * - */ -RT_WEAK void rt_hw_cpu_reset() -{ - - /* enable watchdog */ - *(RP)(RTC_CTR) = 0x02; - - /*Enable watchdog reset*/ - *(RP)(RTC_INT_EN) = 0x20; - - /* Initialize watchdog timer count register */ - *(RP)(RTC_WD_CNT) = 0x0001; - - while(1); /* loop forever and wait for reset to happen */ - - /* NEVER REACHED */ -} - -/** - * shutdown CPU - * - */ -RT_WEAK void rt_hw_cpu_shutdown() -{ - rt_base_t level; - rt_kprintf("shutdown...\n"); - - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(RT_NULL); - } -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/sep4020/interrupt.c b/rt-thread/libcpu/arm/sep4020/interrupt.c deleted file mode 100644 index 24907c1..0000000 --- a/rt-thread/libcpu/arm/sep4020/interrupt.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - * 2013-03-29 aozima Modify the interrupt interface implementations. - */ - -#include -#include -#include - -#define MAX_HANDLERS 32 - -extern rt_uint32_t rt_interrupt_nest; - -/* exception and interrupt handler table */ -struct rt_irq_desc isr_table[MAX_HANDLERS]; -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -/** - * @addtogroup S3C24X0 - */ -/*@{*/ - -static void rt_hw_interrupt_handle(int vector, void *param) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - register rt_uint32_t idx; - - /*Make sure all intc registers in proper state*/ - - /*mask all the irq*/ - *(RP)(INTC_IMR) = 0xFFFFFFFF; - - /*enable all the irq*/ - *(RP)(INTC_IER) = 0XFFFFFFFF; - - /*Dont use any forced irq*/ - *(RP)(INTC_IFR) = 0x0; - - /*Disable all the fiq*/ - *(RP)(INTC_FIER) = 0x0; - - /*Mask all the fiq*/ - *(RP)(INTC_FIMR) = 0x0F; - - /*Dont use forced fiq*/ - *(RP)(INTC_FIFR) = 0x0; - - /*Intrrupt priority register*/ - *(RP)(INTC_IPLR) = 0x0; - - /* init exceptions table */ - rt_memset(isr_table, 0x00, sizeof(isr_table)); - for(idx=0; idx < MAX_HANDLERS; idx++) - { - isr_table[idx].handler = rt_hw_interrupt_handle; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - *(RP)(INTC_IMR) |= 1 << vector; -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - if(vector == 16) - { - rt_kprintf("Interrupt vec %d is not used!\n", vector); - } - else - *(RP)(INTC_IMR) &= ~(1 << vector); -} - - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param new_handler the interrupt service routine to be installed - * @param old_handler the old interrupt service routine - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if(vector < MAX_HANDLERS) - { - old_handler = isr_table[vector].handler; - - if (handler != RT_NULL) - { -#ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); -#endif /* RT_USING_INTERRUPT_INFO */ - isr_table[vector].handler = handler; - isr_table[vector].param = param; - } - } - - return old_handler; -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/sep4020/sep4020.h b/rt-thread/libcpu/arm/sep4020/sep4020.h deleted file mode 100644 index bb8effb..0000000 --- a/rt-thread/libcpu/arm/sep4020/sep4020.h +++ /dev/null @@ -1,875 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ -#ifndef __SEP4020_H -#define __SEP4020_H - -#include - -/*Core definations*/ -#define SVCMODE -#define Mode_USR 0x10 -#define Mode_FIQ 0x11 -#define Mode_IRQ 0x12 -#define Mode_SVC 0x13 -#define Mode_ABT 0x17 -#define Mode_UND 0x1B -#define Mode_SYS 0x1F - - - -/* - * å„模å—寄存器基值 - */ - -#define ESRAM_BASE 0x04000000 -#define INTC_BASE 0x10000000 -#define PMU_BASE 0x10001000 -#define RTC_BASE 0x10002000 -#define WD_BASE 0x10002000 -#define TIMER_BASE 0x10003000 -#define PWM_BASE 0x10004000 -#define UART0_BASE 0X10005000 -#define UART1_BASE 0X10006000 -#define UART2_BASE 0X10007000 -#define UART3_BASE 0X10008000 -#define SSI_BASE 0X10009000 -#define I2S_BASE 0x1000A000 -#define MMC_BASE 0x1000B000 -#define SD_BASE 0x1000B000 -#define SMC0_BASE 0x1000C000 -#define SMC1_BASE 0x1000D000 -#define USBD_BASE 0x1000E000 -#define GPIO_BASE 0x1000F000 -#define EMI_BASE 0x11000000 -#define DMAC_BASE 0x11001000 -#define LCDC_BASE 0x11002000 -#define MAC_BASE 0x11003000 -#define AMBA_BASE 0x11005000 - - -/* - * INTCæ¨¡å— - * 基å€: 0x10000000 - */ - -#define INTC_IER (INTC_BASE+0X000) /* IRQ中断å…许寄存器 */ -#define INTC_IMR (INTC_BASE+0X008) /* IRQ中断å±è”½å¯„存器 */ -#define INTC_IFR (INTC_BASE+0X010) /* IRQ软件强制中断寄存器 */ -#define INTC_IRSR (INTC_BASE+0X018) /* IRQ未处ç†ä¸­æ–­çŠ¶æ€å¯„存器 */ -#define INTC_ISR (INTC_BASE+0X020) /* IRQ中断状æ€å¯„存器 */ -#define INTC_IMSR (INTC_BASE+0X028) /* IRQå±è”½ä¸­æ–­çŠ¶æ€å¯„存器 */ -#define INTC_IFSR (INTC_BASE+0X030) /* IRQ中断最终状æ€å¯„存器 */ -#define INTC_FIER (INTC_BASE+0X0C0) /* FIQ中断å…许寄存器 */ -#define INTC_FIMR (INTC_BASE+0X0C4) /* FIQ中断å±è”½å¯„存器 */ -#define INTC_FIFR (INTC_BASE+0X0C8) /* FIQ软件强制中断寄存器 */ -#define INTC_FIRSR (INTC_BASE+0X0CC) /* FIQ未处ç†ä¸­æ–­çŠ¶æ€å¯„存器 */ -#define INTC_FISR (INTC_BASE+0X0D0) /* FIQ中断状æ€å¯„存器 */ -#define INTC_FIFSR (INTC_BASE+0X0D4) /* FIQ中断最终状æ€å¯„存器 */ -#define INTC_IPLR (INTC_BASE+0X0D8) /* IRQ中断优先级寄存器 */ -#define INTC_ICR1 (INTC_BASE+0X0DC) /* IRQ内部中断优先级控制寄存器1 */ -#define INTC_ICR2 (INTC_BASE+0X0E0) /* IRQ内部中断优先级控制寄存器2 */ -#define INTC_EXICR1 (INTC_BASE+0X0E4) /* IRQ外部中断优先级控制寄存器1 */ -#define INTC_EXICR2 (INTC_BASE+0X0E8) /* IRQ外部中断优先级控制寄存器2 */ - - -/* - * PMUæ¨¡å— - * 基å€: 0x10001000 - */ - -#define PMU_PLTR (PMU_BASE+0X000) /* PLL的稳定过渡时间 */ -#define PMU_PMCR (PMU_BASE+0X004) /* 系统主时钟PLL的控制寄存器 */ -#define PMU_PUCR (PMU_BASE+0X008) /* USB时钟PLL的控制寄存器 */ -#define PMU_PCSR (PMU_BASE+0X00C) /* 内部模å—时钟æºä¾›ç»™çš„控制寄存器 */ -#define PMU_PDSLOW (PMU_BASE+0X010) /* SLOW状æ€ä¸‹æ—¶é’Ÿçš„åˆ†é¢‘å› å­ */ -#define PMU_PMDR (PMU_BASE+0X014) /* 芯片工作模å¼å¯„存器 */ -#define PMU_RCTR (PMU_BASE+0X018) /* Reset控制寄存器 */ -#define PMU_CLRWAKUP (PMU_BASE+0X01C) /* WakeUp清除寄存器 */ - - -/* - * RTCæ¨¡å— - * 基å€: 0x10002000 - */ - -#define RTC_STA_YMD (RTC_BASE+0X000) /* å¹´, 月, 日计数寄存器 */ -#define RTC_STA_HMS (RTC_BASE+0X004) /* å°æ—¶, 分钟, 秒寄存器 */ -#define RTC_ALARM_ALL (RTC_BASE+0X008) /* 定时月, æ—¥, æ—¶, 分寄存器 */ -#define RTC_CTR (RTC_BASE+0X00C) /* 控制寄存器 */ -#define RTC_INT_EN (RTC_BASE+0X010) /* 中断使能寄存器 */ -#define RTC_INT_STS (RTC_BASE+0X014) /* 中断状æ€å¯„存器 */ -#define RTC_SAMP (RTC_BASE+0X018) /* 采样周期寄存器 */ -#define RTC_WD_CNT (RTC_BASE+0X01C) /* Watch-Dog计数值寄存器 */ -#define RTC_WD_SEV (RTC_BASE+0X020) /* Watch-DogæœåŠ¡å¯„存器 */ -#define RTC_CONFIG_CHECK (RTC_BASE+0X024) /* é…置时间确认寄存器 (在é…置时间之å‰å…ˆå†™0xaaaaaaaa) */ -#define RTC_KEY0 (RTC_BASE+0X02C) /* 密钥寄存器 */ - -/* - * TIMERæ¨¡å— - * 基å€: 0x10003000 - */ - -#define TIMER_T1LCR (TIMER_BASE+0X000) /* 通é“1加载计数寄存器 */ -#define TIMER_T1CCR (TIMER_BASE+0X004) /* 通é“1当å‰è®¡æ•°å€¼å¯„存器 */ -#define TIMER_T1CR (TIMER_BASE+0X008) /* 通é“1控制寄存器 */ -#define TIMER_T1ISCR (TIMER_BASE+0X00C) /* 通é“1中断状æ€æ¸…除寄存器 */ -#define TIMER_T1IMSR (TIMER_BASE+0X010) /* 通é“1中断å±è”½çŠ¶æ€å¯„存器 */ -#define TIMER_T2LCR (TIMER_BASE+0X020) /* 通é“2加载计数寄存器 */ -#define TIMER_T2CCR (TIMER_BASE+0X024) /* 通é“2当å‰è®¡æ•°å€¼å¯„存器 */ -#define TIMER_T2CR (TIMER_BASE+0X028) /* 通é“2控制寄存器 */ -#define TIMER_T2ISCR (TIMER_BASE+0X02C) /* 通é“2中断状æ€æ¸…除寄存器 */ -#define TIMER_T2IMSR (TIMER_BASE+0X030) /* 通é“2中断å±è”½çŠ¶æ€å¯„存器 */ -#define TIMER_T3LCR (TIMER_BASE+0X040) /* 通é“3加载计数寄存器 */ -#define TIMER_T3CCR (TIMER_BASE+0X044) /* 通é“3当å‰è®¡æ•°å€¼å¯„存器 */ -#define TIMER_T3CR (TIMER_BASE+0X048) /* 通é“3控制寄存器 */ -#define TIMER_T3ISCR (TIMER_BASE+0X04C) /* 通é“3中断状æ€æ¸…除寄存器 */ -#define TIMER_T3IMSR (TIMER_BASE+0X050) /* 通é“3中断å±è”½çŠ¶æ€å¯„存器 */ -#define TIMER_T3CAPR (TIMER_BASE+0X054) /* 通é“3æ•èŽ·å¯„存器 */ -#define TIMER_T4LCR (TIMER_BASE+0X060) /* 通é“4加载计数寄存器 */ -#define TIMER_T4CCR (TIMER_BASE+0X064) /* 通é“4当å‰è®¡æ•°å€¼å¯„存器 */ -#define TIMER_T4CR (TIMER_BASE+0X068) /* 通é“4控制寄存器 */ -#define TIMER_T4ISCR (TIMER_BASE+0X06C) /* 通é“4中断状æ€æ¸…除寄存器 */ -#define TIMER_T4IMSR (TIMER_BASE+0X070) /* 通é“4中断å±è”½çŠ¶æ€å¯„存器 */ -#define TIMER_T4CAPR (TIMER_BASE+0X074) /* 通é“4æ•èŽ·å¯„存器 */ -#define TIMER_T5LCR (TIMER_BASE+0X080) /* 通é“5加载计数寄存器 */ -#define TIMER_T5CCR (TIMER_BASE+0X084) /* 通é“5当å‰è®¡æ•°å€¼å¯„存器 */ -#define TIMER_T5CR (TIMER_BASE+0X088) /* 通é“5控制寄存器 */ -#define TIMER_T5ISCR (TIMER_BASE+0X08C) /* 通é“5中断状æ€æ¸…除寄存器 */ -#define TIMER_T5IMSR (TIMER_BASE+0X090) /* 通é“5中断å±è”½çŠ¶æ€å¯„存器 */ -#define TIMER_T5CAPR (TIMER_BASE+0X094) /* 通é“5æ•èŽ·å¯„存器 */ -#define TIMER_T6LCR (TIMER_BASE+0X0A0) /* 通é“6加载计数寄存器 */ -#define TIMER_T6CCR (TIMER_BASE+0X0A4) /* 通é“6当å‰è®¡æ•°å€¼å¯„存器 */ -#define TIMER_T6CR (TIMER_BASE+0X0A8) /* 通é“6控制寄存器 */ -#define TIMER_T6ISCR (TIMER_BASE+0X0AC) /* 通é“6中断状æ€æ¸…除寄存器 */ -#define TIMER_T6IMSR (TIMER_BASE+0X0B0) /* 通é“6中断å±è”½çŠ¶æ€å¯„存器 */ -#define TIMER_T6CAPR (TIMER_BASE+0X0B4) /* 通é“6æ•èŽ·å¯„存器 */ -#define TIMER_T7LCR (TIMER_BASE+0X0C0) /* 通é“7加载计数寄存器 */ -#define TIMER_T7CCR (TIMER_BASE+0X0C4) /* 通é“7当å‰è®¡æ•°å€¼å¯„存器 */ -#define TIMER_T7CR (TIMER_BASE+0X0C8) /* 通é“7控制寄存器 */ -#define TIMER_T7ISCR (TIMER_BASE+0X0CC) /* 通é“7中断状æ€æ¸…除寄存器 */ -#define TIMER_T7IMSR (TIMER_BASE+0X0D0) /* 通é“7中断å±è”½çŠ¶æ€å¯„存器 */ -#define TIMER_T8LCR (TIMER_BASE+0X0E0) /* 通é“8加载计数寄存器 */ -#define TIMER_T8CCR (TIMER_BASE+0X0E4) /* 通é“8当å‰è®¡æ•°å€¼å¯„存器 */ -#define TIMER_T8CR (TIMER_BASE+0X0E8) /* 通é“8控制寄存器 */ -#define TIMER_T8ISCR (TIMER_BASE+0X0EC) /* 通é“8中断状æ€æ¸…除寄存器 */ -#define TIMER_T8IMSR (TIMER_BASE+0X0F0) /* 通é“8中断å±è”½çŠ¶æ€å¯„存器 */ -#define TIMER_T9LCR (TIMER_BASE+0X100) /* 通é“9加载计数寄存器 */ -#define TIMER_T9CCR (TIMER_BASE+0X104) /* 通é“9当å‰è®¡æ•°å€¼å¯„存器 */ -#define TIMER_T9CR (TIMER_BASE+0X108) /* 通é“9控制寄存器 */ -#define TIMER_T9ISCR (TIMER_BASE+0X10C) /* 通é“9中断状æ€æ¸…除寄存器 */ -#define TIMER_T9IMSR (TIMER_BASE+0X110) /* 通é“9中断å±è”½çŠ¶æ€å¯„存器 */ -#define TIMER_T10LCR (TIMER_BASE+0X120) /* 通é“10加载计数寄存器 */ -#define TIMER_T10CCR (TIMER_BASE+0X124) /* 通é“10当å‰è®¡æ•°å€¼å¯„存器 */ -#define TIMER_T10CR (TIMER_BASE+0X128) /* 通é“10控制寄存器 */ -#define TIMER_T10ISCR (TIMER_BASE+0X12C) /* 通é“10中断状æ€æ¸…除寄存器 */ -#define TIMER_T10IMSR (TIMER_BASE+0X130) /* 通é“10中断å±è”½çŠ¶æ€å¯„存器 */ -#define TIMER_TIMSR (TIMER_BASE+0X140) /* TIMER中断å±è”½çŠ¶æ€å¯„存器 */ -#define TIMER_TISCR (TIMER_BASE+0X144) /* TIMER中断状æ€æ¸…除寄存器 */ -#define TIMER_TISR (TIMER_BASE+0X148) /* TIMER中断状æ€å¯„存器 */ - - - -/* - * PWMæ¨¡å— - * 基å€: 0x10004000 - */ - -#define PWM0_CTRL (PWM_BASE+0X000) /* PWM0控制寄存器 */ -#define PWM0_DIV (PWM_BASE+0X004) /* PWM0分频寄存器 */ -#define PWM0_PERIOD (PWM_BASE+0X008) /* PWM0周期寄存器 */ -#define PWM0_DATA (PWM_BASE+0X00C) /* PWM0æ•°æ®å¯„存器 */ -#define PWM0_CNT (PWM_BASE+0X010) /* PWM0计数寄存器 */ -#define PWM0_STATUS (PWM_BASE+0X014) /* PWM0状æ€å¯„存器 */ -#define PWM1_CTRL (PWM_BASE+0X020) /* PWM1控制寄存器 */ -#define PWM1_DIV (PWM_BASE+0X024) /* PWM1分频寄存器 */ -#define PWM1_PERIOD (PWM_BASE+0X028) /* PWM1周期寄存器 */ -#define PWM1_DATA (PWM_BASE+0X02C) /* PWM1æ•°æ®å¯„存器 */ -#define PWM1_CNT (PWM_BASE+0X030) /* PWM1计数寄存器 */ -#define PWM1_STATUS (PWM_BASE+0X034) /* PWM1状æ€å¯„存器 */ -#define PWM2_CTRL (PWM_BASE+0X040) /* PWM2控制寄存器 */ -#define PWM2_DIV (PWM_BASE+0X044) /* PWM2分频寄存器 */ -#define PWM2_PERIOD (PWM_BASE+0X048) /* PWM2周期寄存器 */ -#define PWM2_DATA (PWM_BASE+0X04C) /* PWM2æ•°æ®å¯„存器 */ -#define PWM2_CNT (PWM_BASE+0X050) /* PWM2计数寄存器 */ -#define PWM2_STATUS (PWM_BASE+0X054) /* PWM2状æ€å¯„存器 */ -#define PWM3_CTRL (PWM_BASE+0X060) /* PWM3控制寄存器 */ -#define PWM3_DIV (PWM_BASE+0X064) /* PWM3分频寄存器 */ -#define PWM3_PERIOD (PWM_BASE+0X068) /* PWM3周期寄存器 */ -#define PWM3_DATA (PWM_BASE+0X06C) /* PWM3æ•°æ®å¯„存器 */ -#define PWM3_CNT (PWM_BASE+0X070) /* PWM3计数寄存器 */ -#define PWM3_STATUS (PWM_BASE+0X074) /* PWM3状æ€å¯„存器 */ -#define PWM_INTMASK (PWM_BASE+0X080) /* PWM中断å±è”½å¯„存器 */ -#define PWM_INT (PWM_BASE+0X084) /* PWM中断寄存器 */ -#define PWM_ENABLE (PWM_BASE+0X088) /* PWM使能寄存器 */ - - -/* - * UART0æ¨¡å— - * 基å€: 0x10005000 - */ - -#define UART0_DLBL (UART0_BASE+0X000) /* 波特率设置低八ä½å¯„存器 */ -#define UART0_RXFIFO (UART0_BASE+0X000) /* 接收FIFO */ -#define UART0_TXFIFO (UART0_BASE+0X000) /* å‘é€FIFO */ -#define UART0_DLBH (UART0_BASE+0X004) /* 波特率设置高八ä½å¯„存器 */ -#define UART0_IER (UART0_BASE+0X004) /* 中断使能寄存器 */ -#define UART0_IIR (UART0_BASE+0X008) /* 中断识别寄存器 */ -#define UART0_FCR (UART0_BASE+0X008) /* FIFO控制寄存器 */ -#define UART0_LCR (UART0_BASE+0X00C) /* 行控制寄存器 */ -#define UART0_MCR (UART0_BASE+0X010) /* Modem控制寄存器 */ -#define UART0_LSR (UART0_BASE+0X014) /* 行状æ€å¯„存器 */ -#define UART0_MSR (UART0_BASE+0X018) /* Modem状æ€å¯„存器 */ - - -/* - * UART1æ¨¡å— - * 基å€: 0x10006000 - */ - -#define UART1_DLBL (UART1_BASE+0X000) /* 波特率设置低八ä½å¯„存器 */ -#define UART1_RXFIFO (UART1_BASE+0X000) /* 接收FIFO */ -#define UART1_TXFIFO (UART1_BASE+0X000) /* å‘é€FIFO */ -#define UART1_DLBH (UART1_BASE+0X004) /* 波特率设置高八ä½å¯„存器 */ -#define UART1_IER (UART1_BASE+0X004) /* 中断使能寄存器 */ -#define UART1_IIR (UART1_BASE+0X008) /* 中断识别寄存器 */ -#define UART1_FCR (UART1_BASE+0X008) /* FIFO控制寄存器 */ -#define UART1_LCR (UART1_BASE+0X00C) /* 行控制寄存器 */ -#define UART1_MCR (UART1_BASE+0X010) /* Modem控制寄存器 */ -#define UART1_LSR (UART1_BASE+0X014) /* 行状æ€å¯„存器 */ -#define UART1_MSR (UART1_BASE+0X018) /* Modem状æ€å¯„存器 */ - - -/* - * UART2æ¨¡å— - * 基å€: 0x10007000 - */ - -#define UART2_DLBL (UART2_BASE+0X000) /* 波特率设置低八ä½å¯„存器 */ -#define UART2_RXFIFO (UART2_BASE+0X000) /* 接收FIFO */ -#define UART2_TXFIFO (UART2_BASE+0X000) /* å‘é€FIFO */ -#define UART2_DLBH (UART2_BASE+0X004) /* 波特率设置高八ä½å¯„存器 */ -#define UART2_IER (UART2_BASE+0X004) /* 中断使能寄存器 */ -#define UART2_IIR (UART2_BASE+0X008) /* 中断识别寄存器 */ -#define UART2_FCR (UART2_BASE+0X008) /* FIFO控制寄存器 */ -#define UART2_LCR (UART2_BASE+0X00C) /* 行控制寄存器 */ -#define UART2_MCR (UART2_BASE+0X010) /* Modem控制寄存器 */ -#define UART2_LSR (UART2_BASE+0X014) /* 行状æ€å¯„存器 */ -#define UART2_MSR (UART2_BASE+0X018) /* Modem状æ€å¯„存器 */ - - -/* - * UART3æ¨¡å— - * 基å€: 0x10008000 - */ - -#define UART3_DLBL (UART3_BASE+0X000) /* 波特率设置低八ä½å¯„存器 */ -#define UART3_RXFIFO (UART3_BASE+0X000) /* 接收FIFO */ -#define UART3_TXFIFO (UART3_BASE+0X000) /* å‘é€FIFO */ -#define UART3_DLBH (UART3_BASE+0X004) /* 波特率设置高八ä½å¯„存器 */ -#define UART3_IER (UART3_BASE+0X004) /* 中断使能寄存器 */ -#define UART3_IIR (UART3_BASE+0X008) /* 中断识别寄存器 */ -#define UART3_FCR (UART3_BASE+0X008) /* FIFO控制寄存器 */ -#define UART3_LCR (UART3_BASE+0X00C) /* 行控制寄存器 */ -#define UART3_MCR (UART3_BASE+0X010) /* Modem控制寄存器 */ -#define UART3_LSR (UART3_BASE+0X014) /* 行状æ€å¯„存器 */ -#define UART3_MSR (UART3_BASE+0X018) /* Modem状æ€å¯„存器 */ - - -/* - * SSIæ¨¡å— - * 基å€: 0x10009000 - */ - -#define SSI_CONTROL0 (SSI_BASE+0X000) /* 控制寄存器0 */ -#define SSI_CONTROL1 (SSI_BASE+0X004) /* 控制寄存器1 */ -#define SSI_SSIENR (SSI_BASE+0X008) /* SSI使能寄存器 */ -#define SSI_MWCR (SSI_BASE+0X00C) /* Microwire控制寄存器 */ -#define SSI_SER (SSI_BASE+0X010) /* 从设备使能寄存器 */ -#define SSI_BAUDR (SSI_BASE+0X014) /* 波特率设置寄存器 */ -#define SSI_TXFTLR (SSI_BASE+0X018) /* å‘é€FIFO阈值寄存器 */ -#define SSI_RXFTLR (SSI_BASE+0X01C) /* 接收FIFO阈值寄存器 */ -#define SSI_TXFLR (SSI_BASE+0X020) /* å‘é€FIFO状æ€å¯„存器 */ -#define SSI_RXFLR (SSI_BASE+0X024) /* 接收FIFO状æ€å¯„存器 */ -#define SSI_SR (SSI_BASE+0X028) /* 状æ€å¯„存器 */ -#define SSI_IMR (SSI_BASE+0X02C) /* 中断å±è”½å¯„存器 */ -#define SSI_ISR (SSI_BASE+0X030) /* 中断最终状æ€å¯„存器 */ -#define SSI_RISR (SSI_BASE+0X034) /* 中断原始状æ€å¯„存器 */ -#define SSI_TXOICR (SSI_BASE+0X038) /* å‘é€FIFO上溢中断清除寄存器 */ -#define SSI_RXOICR (SSI_BASE+0X03C) /* 接收FIFO上溢中断清除寄存器 */ -#define SSI_RXUICR (SSI_BASE+0X040) /* 接收FIFO下溢中断清除寄存器 */ -#define SSI_ICR (SSI_BASE+0X02C) /* 中断清除寄存器 */ -#define SSI_DMACR (SSI_BASE+0X04C) /* DMA控制寄存器 */ -#define SSI_DMATDLR (SSI_BASE+0X050) /* DMAå‘é€çŠ¶æ€å¯„存器 */ -#define SSI_DMARDLR (SSI_BASE+0X054) /* DMA接收状æ€å¯„存器 */ -#define SSI_DR (SSI_BASE+0X060) /* æ•°æ®å¯„存器 */ - - -/* - * I2Sæ¨¡å— - * 基å€: 0x1000A000 - */ - -#define I2S_CTRL (I2S_BASE+0X000) /* I2S控制寄存器 */ -#define I2S_DATA (I2S_BASE+0X004) /* I2Sæ•°æ®å¯„存器 */ -#define I2S_INT (I2S_BASE+0X008) /* I2S中断寄存器 */ -#define I2S_STATUS (I2S_BASE+0X00C) /* I2S状æ€å¯„存器 */ - - -/* - * SDæ¨¡å— - * 基å€: 0x1000B000 - */ - -#define SDC_CLOCK_CONTROL (SD_BASE+0x00) /* SDIO时钟控制寄存器 */ -#define SDC_SOFTWARE_RESET (SD_BASE+0X04) /* SDIO软件å¤ä½å¯„存器 */ -#define SDC_ARGUMENT (SD_BASE+0X08) /* SDIO命令å‚数寄存器 */ -#define SDC_COMMAND (SD_BASE+0X0C) /* SDIO命令控制寄存器 */ -#define SDC_BLOCK_SIZE (SD_BASE+0X10) /* SDIOæ•°æ®å—长度寄存器 */ -#define SDC_BLOCK_COUNT (SD_BASE+0X14) /* SDIOæ•°æ®å—数目寄存器 */ -#define SDC_TRANSFER_MODE (SD_BASE+0X18) /* SDIO传输模å¼é€‰æ‹©å¯„存器 */ -#define SDC_RESPONSE0 (SD_BASE+0X1c) /* SDIOå“应寄存器0 */ -#define SDC_RESPONSE1 (SD_BASE+0X20) /* SDIOå“应寄存器1 */ -#define SDC_RESPONSE2 (SD_BASE+0X24) /* SDIOå“应寄存器2 */ -#define SDC_RESPONSE3 (SD_BASE+0X28) /* SDIOå“应寄存器3 */ -#define SDC_READ_TIMEOUT_CONTROL (SD_BASE+0X2c) /* SDIO读超时控制寄存器 */ -#define SDC_INTERRUPT_STATUS (SD_BASE+0X30) /* SDIO中断状æ€å¯„存器 */ -#define SDC_INTERRUPT_STATUS_MASK (SD_BASE+0X34) /* SDIO中断状æ€å±è”½å¯„存器 */ -#define SDC_READ_BUFER_ACCESS (SD_BASE+0X38) /* SDIO接收FIFO */ -#define SDC_WRITE_BUFER_ACCESS (SD_BASE+0X3c) /* SDIOå‘é€FIFO */ - - - -/* - * SMC0æ¨¡å— - * 基å€: 0x1000C000 - */ - -#define SMC0_CTRL (SMC0_BASE+0X000) /* SMC0控制寄存器 */ -#define SMC0_INT (SMC0_BASE+0X004) /* SMC0中断寄存器 */ -#define SMC0_FD (SMC0_BASE+0X008) /* SMC0基本å•å…ƒæ—¶é—´å¯„存器 */ -#define SMC0_CT (SMC0_BASE+0X00C) /* SMC0字符传输时间寄存器 */ -#define SMC0_BT (SMC0_BASE+0X010) /* SMC0å—传输时间寄存器 */ - - - -/* - * SMC1æ¨¡å— - * 基å€: 0x1000D000 - */ - -#define SMC1_CTRL (SMC1_BASE+0X000) /* SMC1控制寄存器 */ -#define SMC1_INT (SMC1_BASE+0X004) /* SMC1中断寄存器 */ -#define SMC1_FD (SMC1_BASE+0X008) /* SMC1基本å•å…ƒæ—¶é—´å¯„存器 */ -#define SMC1_CT (SMC1_BASE+0X00C) /* SMC1字符传输时间寄存器 */ -#define SMC1_BT (SMC1_BASE+0X010) /* SMC1å—传输时间寄存器 */ - - - -/* - * USBDæ¨¡å— - * 基å€: 0x1000E000 - */ - -#define USBD_PROTOCOLINTR (USBD_BASE+0X000) /* USBå议中断寄存器 */ -#define USBD_INTRMASK (USBD_BASE+0X004) /* USB中断å±è”½å¯„存器 */ -#define USBD_INTRCTRL (USBD_BASE+0X008) /* USB中断类型控制寄存器 */ -#define USBD_EPINFO (USBD_BASE+0X00C) /* USB活动端点状æ€å¯„存器 */ -#define USBD_BCONFIGURATIONVALUE (USBD_BASE+0X010) /* SET_CCONFIGURATION记录 */ -#define USBD_BMATTRIBUTES (USBD_BASE+0X014) /* 当å‰é…置属性寄存器 */ -#define USBD_DEVSPEED (USBD_BASE+0X018) /* 当å‰è®¾å¤‡å·¥ä½œé€Ÿåº¦å¯„存器 */ -#define USBD_FRAMENUMBER (USBD_BASE+0X01C) /* 记录当å‰SOFåŒ…å†…çš„å¸§å· */ -#define USBD_EPTRANSACTIONS0 (USBD_BASE+0X020) /* 记录下次è¦æ±‚的传输次数 */ -#define USBD_EPTRANSACTIONS1 (USBD_BASE+0X024) /* 记录下次è¦æ±‚的传输次数 */ -#define USBD_APPIFUPDATE (USBD_BASE+0X028) /* 接å£å·å¿«é€Ÿæ›´æ–°å¯„存器 */ -#define USBD_CFGINTERFACE0 (USBD_BASE+0X02C) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE1 (USBD_BASE+0X030) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE2 (USBD_BASE+0X034) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE3 (USBD_BASE+0X038) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE4 (USBD_BASE+0X03C) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE5 (USBD_BASE+0X040) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE6 (USBD_BASE+0X044) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE7 (USBD_BASE+0X048) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE8 (USBD_BASE+0X04C) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE9 (USBD_BASE+0X050) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE10 (USBD_BASE+0X054) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE11 (USBD_BASE+0X058) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE12 (USBD_BASE+0X05C) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE13 (USBD_BASE+0X060) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE14 (USBD_BASE+0X064) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE15 (USBD_BASE+0X068) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE16 (USBD_BASE+0X06C) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE17 (USBD_BASE+0X070) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE18 (USBD_BASE+0X074) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE19 (USBD_BASE+0X078) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE20 (USBD_BASE+0X07C) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE21 (USBD_BASE+0X080) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE22 (USBD_BASE+0X084) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE23 (USBD_BASE+0X088) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE24 (USBD_BASE+0X08C) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE25 (USBD_BASE+0X090) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE26 (USBD_BASE+0X094) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE27 (USBD_BASE+0X098) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE28 (USBD_BASE+0X09C) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE29 (USBD_BASE+0X0A0) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE30 (USBD_BASE+0X0A4) /* 记录接å£çš„值 */ -#define USBD_CFGINTERFACE31 (USBD_BASE+0X0A8) /* 记录接å£çš„值 */ -#define USBD_PKTPASSEDCTRL (USBD_BASE+0X0AC) /* 记录æˆåŠŸæŽ¥æ”¶çš„包数 */ -#define USBD_PKTDROPPEDCTRL (USBD_BASE+0X0B0) /* 记录丢失的包数 */ -#define USBD_CRCERRCTRL (USBD_BASE+0X0B4) /* 记录CRC错误的包数 */ -#define USBD_BITSTUFFERRCTRL (USBD_BASE+0X0B8) /* 记录ä½å¡«å……错误的包数 */ -#define USBD_PIDERRCTRL (USBD_BASE+0X0BC) /* 记录PID错误的包数 */ -#define USBD_FRAMINGERRCTL (USBD_BASE+0X0C0) /* 记录有SYNCå’ŒEOP的包数 */ -#define USBD_TXPKTCTRL (USBD_BASE+0X0C4) /* 记录å‘é€åŒ…çš„æ•°é‡ */ -#define USBD_STATCTRLOV (USBD_BASE+0X0C8) /* 记录统计寄存器溢出情况 */ -#define USBD_TXLENGTH (USBD_BASE+0X0CC) /* 记录æ¯æ¬¡IN传输事务包长度 */ -#define USBD_RXLENGTH (USBD_BASE+0X0D0) /* 记录OUT传输事务包长度 */ -#define USBD_RESUME (USBD_BASE+0X0D4) /* USB唤醒寄存器 */ -#define USBD_READFLAG (USBD_BASE+0X0D8) /* 读异步状æ€å¯„存器标志 */ -#define USBD_RECEIVETYPE (USBD_BASE+0X0DC) /* 传输状æ€å¯„存器 */ -#define USBD_APPLOCK (USBD_BASE+0X0E0) /* é”ä¿¡å·å¯„存器 */ -#define USBD_EP0OUTADDR (USBD_BASE+0X100) /* 端点0端点å·å’Œæ–¹å‘ */ -#define USBD_EP0OUTBMATTR (USBD_BASE+0X104) /* 端点0类型寄存器 */ -#define USBD_EP0OUTMAXPKTSIZE (USBD_BASE+0X108) /* 端点0最大包尺寸寄存器 */ -#define USBD_EP0OUTIFNUM (USBD_BASE+0X10C) /* 端点0接å£å·å¯„存器 */ -#define USBD_EP0OUTSTAT (USBD_BASE+0X110) /* 端点0状æ€å¯„存器 */ -#define USBD_EP0OUTBMREQTYPE (USBD_BASE+0X114) /* 端点0 SETUP事务请求类 */ -#define USBD_EP0OUTBREQUEST (USBD_BASE+0X118) /* 端点0 SETUP事务请求内容 */ -#define USBD_EP0OUTWVALUE (USBD_BASE+0X11C) /* 端点0 SETUP事务请求值 */ -#define USBD_EP0OUTWINDEX (USBD_BASE+0X120) /* 端点0 SETUP事务请求索引 */ -#define USBD_EP0OUTWLENGTH (USBD_BASE+0X120) /* 端点0 SETUP事务请求长度 */ -#define USBD_EP0OUTSYNCHFRAME (USBD_BASE+0X128) /* 端点0åŒæ­¥åŒ…å¸§å· */ -#define USBD_EP1OUTADDR (USBD_BASE+0X12C) /* 端点1输出端点å·å’Œæ–¹å‘ */ -#define USBD_EP1OUTBMATTR (USBD_BASE+0X130) /* 端点1输出类型寄存器 */ -#define USBD_EP1OUTMAXPKTSIZE (USBD_BASE+0X134) /* 端点1输出最大包尺寸寄存器 */ -#define USBD_EP1OUTIFNUM (USBD_BASE+0X138) /* 端点1输出接å£å·å¯„存器 */ -#define USBD_EP1OUTSTAT (USBD_BASE+0X13C) /* 端点1输出状æ€å¯„存器 */ -#define USBD_EP1OUTBMREQTYPE (USBD_BASE+0X140) /* 端点1输出SETUP事务请求类型 */ -#define USBD_EP1OUTBREQUEST (USBD_BASE+0X144) /* 端点1输出SETUP事务请求内容 */ -#define USBD_EP1OUTWVALUE (USBD_BASE+0X148) /* 端点1输出SETUP事务请求值 */ -#define USBD_EP1OUTWINDX (USBD_BASE+0X14C) /* 端点1输出SETUP事务请求索引 */ -#define USBD_EP1OUTWLENGH (USBD_BASE+0X150) /* 端点1输出SETUP事务请求域长度 */ -#define USBD_EP1OUTSYNCHFRAME (USBD_BASE+0X154) /* 端点1输出åŒæ­¥åŒ…å¸§å· */ -#define USBD_EP1INADDR (USBD_BASE+0X158) /* 端点1输入端点å·å’Œæ–¹å‘ */ -#define USBD_EP1INBMATTR (USBD_BASE+0X15C) /* 端点1输入类型寄存器 */ -#define USBD_EP1INMAXPKTSIZE (USBD_BASE+0X160) /* 端点1输入最大包尺寸寄存器 */ -#define USBD_EP1INIFNUM (USBD_BASE+0X164) /* 端点1输入接å£å·å¯„存器 */ -#define USBD_EP1INSTAT (USBD_BASE+0X168) /* 端点1输入状æ€å¯„存器 */ -#define USBD_EP1INBMREQTYPE (USBD_BASE+0X16C) /* 端点1输入SETUP事务请求类型 */ -#define USBD_EP1INBREQUEST (USBD_BASE+0X170) /* 端点1输入SETUP事务请求内容 */ -#define USBD_EP1INWVALUE (USBD_BASE+0X174) /* 端点1输入SETUP事务请求值 */ -#define USBD_EP1INWINDEX (USBD_BASE+0X178) /* 端点1输入SETUP事务请求索引 */ -#define USBD_EP1INWLENGTH (USBD_BASE+0X17C) /* 端点1输入SETUP事务请求域长度 */ -#define USBD_EP1INSYNCHFRAME (USBD_BASE+0X180) /* 端点1输入åŒæ­¥åŒ…å¸§å· */ -#define USBD_EP2OUTADDR (USBD_BASE+0X184) /* 端点2输出端点å·å’Œæ–¹å‘ */ -#define USBD_EP2OUTBMATTR (USBD_BASE+0X188) /* 端点2输出类型寄存器 */ -#define USBD_EP2OUTMAXPKTSIZE (USBD_BASE+0X18C) /* 端点2输出最大包尺寸寄存器 */ -#define USBD_EP2OUTIFNUM (USBD_BASE+0X190) /* 端点2输出接å£å·å¯„存器 */ -#define USBD_EP2OUTSTAT (USBD_BASE+0X194) /* 端点2输出状æ€å¯„存器 */ -#define USBD_EP2OUTBMREQTYPE (USBD_BASE+0X198) /* 端点2输出SETUP事务请求类型 */ -#define USBD_EP2OUTBREQUEST (USBD_BASE+0X19C) /* 端点2输出SETUP事务请求内容 */ -#define USBD_EP2OUTWVALUE (USBD_BASE+0X1A0) /* 端点2输出SETUP事务请求值 */ -#define USBD_EP2OUTWINDEX (USBD_BASE+0X1A4) /* 端点2输出SETUP事务请求索引 */ -#define USBD_EP2OUTWLENGTH (USBD_BASE+0X1A8) /* 端点2输出SETUP事务请求域长度 */ -#define USBD_EP2OUTSYNCHFRAME (USBD_BASE+0X1AC) /* 端点2输出åŒæ­¥åŒ…å¸§å· */ -#define USBD_EP2INADDR (USBD_BASE+0X1B0) /* 端点2输入端点å·å’Œæ–¹å‘ */ -#define USBD_EP2INBMATTR (USBD_BASE+0X1B4) /* 端点2输入类型寄存器 */ -#define USBD_EP2INMAXPKTSIZE (USBD_BASE+0X1B8) /* 端点2输入最大包尺寸寄存器 */ -#define USBD_EP2INIFNUM (USBD_BASE+0X1BC) /* 端点2输入接å£å·å¯„存器 */ -#define USBD_EP2INSTAT (USBD_BASE+0X1C0) /* 端点2输入状æ€å¯„存器 */ -#define USBD_EP2INBMREQTYPE (USBD_BASE+0X1C4) /* 端点2输入SETUP事务请求类型 */ -#define USBD_EP2INBREQUEST (USBD_BASE+0X1C8) /* 端点2输入SETUP事务请求内容 */ -#define USBD_EP2INWVALUE (USBD_BASE+0X1CC) /* 端点2输入SETUP事务请求值 */ -#define USBD_EP2INWINDEX (USBD_BASE+0X1D0) /* 端点2输入SETUP事务请求索引 */ -#define USBD_EP2INWLENGTH (USBD_BASE+0X1D4) /* 端点2输入SETUP事务请求域长度 */ -#define USBD_EP2INSYNCHFRAME (USBD_BASE+0X1D8) /* 端点2输入åŒæ­¥åŒ…å¸§å· */ -#define USBD_RXFIFO (USBD_BASE+0X200) /* 接å—FIFO */ -#define USBD_TXFIFO (USBD_BASE+0X300) /* å‘é€FIFO */ - - -/* - * GPIOæ¨¡å— - * 基å€: 0x1000F000 - */ - -#define GPIO_DBCLK_DIV (GPIO_BASE+0X000) /* 去毛刺采用时钟分频比é…置寄存器 */ -#define GPIO_PORTA_DIR (GPIO_BASE+0X004) /* A组端å£è¾“入输出方å‘é…置寄存器 */ -#define GPIO_PORTA_SEL (GPIO_BASE+0X008) /* A组端å£é€šç”¨ç”¨é€”选择é…置寄存器 */ -#define GPIO_PORTA_INCTL (GPIO_BASE+0X00C) /* A组端å£é€šç”¨ç”¨é€”输入时类型é…置寄存器 */ -#define GPIO_PORTA_INTRCTL (GPIO_BASE+0X010) /* A组端å£ä¸­æ–­è§¦å‘类型é…置寄存器 */ -#define GPIO_PORTA_INTRCLR (GPIO_BASE+0X014) /* A组端å£é€šç”¨ç”¨é€”中断清除é…置寄存器 */ -#define GPIO_PORTA_DATA (GPIO_BASE+0X018) /* A组端å£é€šç”¨ç”¨é€”æ•°æ®é…置寄存器 */ -#define GPIO_PORTB_DIR (GPIO_BASE+0X01C) /* B组端å£è¾“入输出方å‘é…置寄存器 */ -#define GPIO_PORTB_SEL (GPIO_BASE+0X020) /* B组端å£é€šç”¨ç”¨é€”选择é…置寄存器 */ -#define GPIO_PORTB_DATA (GPIO_BASE+0X024) /* B组端å£é€šç”¨ç”¨é€”æ•°æ®é…置寄存器 */ -#define GPIO_PORTC_DIR (GPIO_BASE+0X028) /* C组端å£è¾“入输出方å‘é…置寄存器 */ -#define GPIO_PORTC_SEL (GPIO_BASE+0X02C) /* C组端å£é€šç”¨ç”¨é€”选择é…置寄存器 */ -#define GPIO_PORTC_DATA (GPIO_BASE+0X030) /* C组端å£é€šç”¨ç”¨é€”æ•°æ®é…置寄存器 */ -#define GPIO_PORTD_DIR (GPIO_BASE+0X034) /* D组端å£è¾“入输出方å‘é…置寄存器 */ -#define GPIO_PORTD_SEL (GPIO_BASE+0X038) /* D组端å£é€šç”¨ç”¨é€”选择é…置寄存器 */ -#define GPIO_PORTD_SPECII (GPIO_BASE+0X03C) /* D组端å£ä¸“用用途2选择é…置寄存器 */ -#define GPIO_PORTD_DATA (GPIO_BASE+0X040) /* D组端å£é€šç”¨ç”¨é€”æ•°æ®é…置寄存器 */ -#define GPIO_PORTE_DIR (GPIO_BASE+0X044) /* E组端å£è¾“入输出方å‘é…置寄存器 */ -#define GPIO_PORTE_SEL (GPIO_BASE+0X048) /* E组端å£é€šç”¨ç”¨é€”选择é…置寄存器 */ -#define GPIO_PORTE_DATA (GPIO_BASE+0X04C) /* E组端å£é€šç”¨ç”¨é€”æ•°æ®é…置寄存器 */ -#define GPIO_PORTF_DIR (GPIO_BASE+0X050) /* F组端å£è¾“入输出方å‘é…置寄存器 */ -#define GPIO_PORTF_SEL (GPIO_BASE+0X054) /* F组端å£é€šç”¨ç”¨é€”选择é…置寄存器 */ -#define GPIO_PORTF_INCTL (GPIO_BASE+0X058) /* F组端å£é€šç”¨ç”¨é€”输入时类型é…置寄存器 */ -#define GPIO_PORTF_INTRCTL (GPIO_BASE+0X05C) /* F组端å£ä¸­æ–­è§¦å‘类型é…置寄存器 */ -#define GPIO_PORTF_INTRCLR (GPIO_BASE+0X060) /* F组端å£é€šç”¨ç”¨é€”中断清除é…置寄存器 */ -#define GPIO_PORTF_DATA (GPIO_BASE+0X064) /* F组端å£é€šç”¨ç”¨é€”æ•°æ®é…置寄存器 */ -#define GPIO_PORTG_DIR (GPIO_BASE+0X068) /* G组端å£è¾“入输出方å‘é…置寄存器 */ -#define GPIO_PORTG_SEL (GPIO_BASE+0X06C) /* G组端å£é€šç”¨ç”¨é€”选择é…置寄存器 */ -#define GPIO_PORTG_DATA (GPIO_BASE+0X070) /* G组端å£é€šç”¨ç”¨é€”æ•°æ®é…置寄存器 */ -#define GPIO_PORTH_DIR (GPIO_BASE+0X07C) /* H组端å£è¾“入输出方å‘é…置寄存器 */ -#define GPIO_PORTH_SEL (GPIO_BASE+0X078) /* H组端å£é€šç”¨ç”¨é€”选择é…置寄存器 */ -#define GPIO_PORTH_DATA (GPIO_BASE+0X07C) /* H组端å£é€šç”¨ç”¨é€”æ•°æ®é…置寄存器 */ -#define GPIO_PORTI_DIR (GPIO_BASE+0X080) /* I组端å£è¾“入输出方å‘é…置寄存器 */ -#define GPIO_PORTI_SEL (GPIO_BASE+0X084) /* I组端å£é€šç”¨ç”¨é€”选择é…置寄存器 */ -#define GPIO_PORTI_DATA (GPIO_BASE+0X088) /* I组端å£é€šç”¨ç”¨é€”æ•°æ®é…置寄存器 */ - - - -/* - * EMIæ¨¡å— - * 基å€: 0x11000000 - */ - -#define EMI_CSACONF (EMI_BASE+0X000) /* CSAå‚æ•°é…置寄存器 */ -#define EMI_CSBCONF (EMI_BASE+0X004) /* CSBå‚æ•°é…置寄存器 */ -#define EMI_CSCCONF (EMI_BASE+0X008) /* CSCå‚æ•°é…置寄存器 */ -#define EMI_CSDCONF (EMI_BASE+0X00C) /* CSDå‚æ•°é…置寄存器 */ -#define EMI_CSECONF (EMI_BASE+0X010) /* CSEå‚æ•°é…置寄存器 */ -#define EMI_CSFCONF (EMI_BASE+0X014) /* CSFå‚æ•°é…置寄存器 */ -#define EMI_SDCONF1 (EMI_BASE+0X018) /* SDRAMæ—¶åºé…置寄存器1 */ -#define EMI_SDCONF2 (EMI_BASE+0X01C) /* SDRAMæ—¶åºé…置寄存器2, SDRAMåˆå§‹åŒ–用到的é…ç½®ä¿¡æ¯ */ -#define EMI_REMAPCONF (EMI_BASE+0X020) /* 片选空间åŠåœ°å€æ˜ å°„REMAPé…置寄存器 */ -#define EMI_NAND_ADDR1 (EMI_BASE+0X100) /* NAND FLASH的地å€å¯„存器1 */ -#define EMI_NAND_COM (EMI_BASE+0X104) /* NAND FLASH的控制字寄存器 */ -#define EMI_NAND_STA (EMI_BASE+0X10C) /* NAND FLASH的状æ€å¯„存器 */ -#define EMI_ERR_ADDR1 (EMI_BASE+0X110) /* 读æ“作出错的地å€å¯„存器1 */ -#define EMI_ERR_ADDR2 (EMI_BASE+0X114) /* 读æ“作出错的地å€å¯„存器2 */ -#define EMI_NAND_CONF1 (EMI_BASE+0X118) /* NAND FLASHçš„é…置器存器1 */ -#define EMI_NAND_INTR (EMI_BASE+0X11C) /* NAND FLASH中断寄存器 */ -#define EMI_NAND_ECC (EMI_BASE+0X120) /* ECC校验完æˆå¯„存器 */ -#define EMI_NAND_IDLE (EMI_BASE+0X124) /* NAND FLASH空闲寄存器 */ -#define EMI_NAND_CONF2 (EMI_BASE+0X128) /* NAND FLASHçš„é…置器存器2 */ -#define EMI_NAND_ADDR2 (EMI_BASE+0X12C) /* NAND FLASH的地å€å¯„存器2 */ -#define EMI_NAND_DATA (EMI_BASE+0X200) /* NAND FLASHçš„æ•°æ®å¯„存器 */ - - -/* - * DMACæ¨¡å— - * 基å€: 0x11001000 - */ - -#define DMAC_INTSTATUS (DMAC_BASE+0X020) /* DAMC中断状æ€å¯„存器。 */ -#define DMAC_INTTCSTATUS (DMAC_BASE+0X050) /* DMAC传输完æˆä¸­æ–­çŠ¶æ€å¯„存器 */ -#define DMAC_INTTCCLEAR (DMAC_BASE+0X060) /* DMAC传输完æˆä¸­æ–­çŠ¶æ€æ¸…除寄存器 */ -#define DMAC_INTERRORSTATUS (DMAC_BASE+0X080) /* DMAC传输错误中断状æ€å¯„存器 */ -#define DMAC_INTINTERRCLR (DMAC_BASE+0X090) /* DMAC传输错误中断状æ€æ¸…除寄存器 */ -#define DMAC_ENBLDCHNS (DMAC_BASE+0X0B0) /* DMAC通é“使能状æ€å¯„存器 */ -#define DMAC_C0SRCADDR (DMAC_BASE+0X000) /* DMACé“0æºåœ°å€å¯„存器 */ -#define DMAC_C0DESTADD (DMAC_BASE+0X004) /* DMACé“0目的地å€å¯„存器 */ -#define DMAC_C0CONTROL (DMAC_BASE+0X00C) /* DMACé“0控制寄存器 */ -#define DMAC_C0CONFIGURATION (DMAC_BASE+0X010) /* DMACé“0é…置寄存器 */ -#define DMAC_C0DESCRIPTOR (DMAC_BASE+0X01C) /* DMACé“0链表地å€å¯„存器 */ -#define DMAC_C1SRCADDR (DMAC_BASE+0X100) /* DMACé“1æºåœ°å€å¯„存器 */ -#define DMAC_C1DESTADDR (DMAC_BASE+0X104) /* DMACé“1目的地å€å¯„存器 */ -#define DMAC_C1CONTROL (DMAC_BASE+0X10C) /* DMACé“1控制寄存器 */ -#define DMAC_C1CONFIGURATION (DMAC_BASE+0X110) /* DMACé“1é…置寄存器 */ -#define DMAC_C1DESCRIPTOR (DMAC_BASE+0X114) /* DMACé“1链表地å€å¯„存器 */ -#define DMAC_C2SRCADDR (DMAC_BASE+0X200) /* DMACé“2æºåœ°å€å¯„存器 */ -#define DMAC_C2DESTADDR (DMAC_BASE+0X204) /* DMACé“2目的地å€å¯„存器 */ -#define DMAC_C2CONTROL (DMAC_BASE+0X20C) /* DMACé“2控制寄存器 */ -#define DMAC_C2CONFIGURATION (DMAC_BASE+0X210) /* DMACé“2é…置寄存器 */ -#define DMAC_C2DESCRIPTOR (DMAC_BASE+0X214) /* DMACé“2链表地å€å¯„存器 */ -#define DMAC_C3SRCADDR (DMAC_BASE+0X300) /* DMACé“3æºåœ°å€å¯„存器 */ -#define DMAC_C3DESTADDR (DMAC_BASE+0X304) /* DMACé“3目的地å€å¯„存器 */ -#define DMAC_C3CONTROL (DMAC_BASE+0X30C) /* DMACé“3控制寄存器 */ -#define DMAC_C3CONFIGURATION (DMAC_BASE+0X310) /* DMACé“3é…置寄存器 */ -#define DMAC_C3DESCRIPTOR (DMAC_BASE+0X314) /* DMACé“3链表地å€å¯„存器 */ -#define DMAC_C4SRCADDR (DMAC_BASE+0X400) /* DMACé“4æºåœ°å€å¯„存器 */ -#define DMAC_C4DESTADDR (DMAC_BASE+0X404) /* DMACé“4目的地å€å¯„存器 */ -#define DMAC_C4CONTROL (DMAC_BASE+0X40C) /* DMACé“4控制寄存器 */ -#define DMAC_C4CONFIGURATION (DMAC_BASE+0X410) /* DMACé“4é…置寄存器 */ -#define DMAC_C4DESCRIPTOR (DMAC_BASE+0X414) /* DMACé“4链表地å€å¯„存器 */ -#define DMAC_C5SRCADDR (DMAC_BASE+0X500) /* DMACé“5æºåœ°å€å¯„存器 */ -#define DMAC_C5DESTADDR (DMAC_BASE+0X504) /* DMACé“5目的地å€å¯„存器 */ -#define DMAC_C5CONTROL (DMAC_BASE+0X50C) /* DMACé“5控制寄存器 */ -#define DMAC_C5CONFIGURATION (DMAC_BASE+0X510) /* DMACé“5é…置寄存器 */ -#define DMAC_C5DESCRIPTOR (DMAC_BASE+0X514) /* DMACé“5链表地å€å¯„存器 */ - - -/* - * LCDCæ¨¡å— - * 基å€: 0x11002000 - */ - -#define LCDC_SSA (LCDC_BASE+0X000) /* å±å¹•èµ·å§‹åœ°å€å¯„存器 */ -#define LCDC_SIZE (LCDC_BASE+0X004) /* å±å¹•å°ºå¯¸å¯„存器 */ -#define LCDC_PCR (LCDC_BASE+0X008) /* é¢æ¿é…置寄存器 */ -#define LCDC_HCR (LCDC_BASE+0X00C) /* æ°´å¹³é…置寄存器 */ -#define LCDC_VCR (LCDC_BASE+0X010) /* åž‚ç›´é…置寄存器 */ -#define LCDC_PWMR (LCDC_BASE+0X014) /* PWM对比度控制寄存器 */ -#define LCDC_LECR (LCDC_BASE+0X018) /* 使能控制寄存器 */ -#define LCDC_DMACR (LCDC_BASE+0X01C) /* DMA控制寄存器 */ -#define LCDC_LCDISREN (LCDC_BASE+0X020) /* 中断使能寄存器 */ -#define LCDC_LCDISR (LCDC_BASE+0X024) /* 中断状æ€å¯„存器 */ -#define LCDC_LGPMR (LCDC_BASE+0X040) /* ç°åº¦è°ƒè‰²æ˜ å°„寄存器组 (16个32bit寄存器) */ - - -/* - * MACæ¨¡å— - * 基å€: 0x11003000 - */ - -#define MAC_CTRL (MAC_BASE+0X000) /* MAC控制寄存器 */ -#define MAC_INTSRC (MAC_BASE+0X004) /* MAC中断æºå¯„存器 */ -#define MAC_INTMASK (MAC_BASE+0X008) /* MAC中断å±è”½å¯„存器 */ -#define MAC_IPGT (MAC_BASE+0X00C) /* 连续帧间隔寄存器 */ -#define MAC_IPGR1 (MAC_BASE+0X010) /* 等待窗å£å¯„存器 */ -#define MAC_IPGR2 (MAC_BASE+0X014) /* 等待窗å£å¯„存器 */ -#define MAC_PACKETLEN (MAC_BASE+0X018) /* 帧长度寄存器 */ -#define MAC_COLLCONF (MAC_BASE+0X01C) /* 碰撞é‡å‘寄存器 */ -#define MAC_TXBD_NUM (MAC_BASE+0X020) /* å‘é€æ述符寄存器 */ -#define MAC_FLOWCTRL (MAC_BASE+0X024) /* æµæŽ§å¯„存器 */ -#define MAC_MII_CTRL (MAC_BASE+0X028) /* PHY控制寄存器 */ -#define MAC_MII_CMD (MAC_BASE+0X02C) /* PHY命令寄存器 */ -#define MAC_MII_ADDRESS (MAC_BASE+0X030) /* PHY地å€å¯„存器 */ -#define MAC_MII_TXDATA (MAC_BASE+0X034) /* PHY写数æ®å¯„存器 */ -#define MAC_MII_RXDATA (MAC_BASE+0X038) /* PHY读数æ®å¯„存器 */ -#define MAC_MII_STATUS (MAC_BASE+0X03C) /* PHY状æ€å¯„存器 */ -#define MAC_ADDR0 (MAC_BASE+0X040) /* MAC地å€å¯„存器 */ -#define MAC_ADDR1 (MAC_BASE+0X044) /* MAC地å€å¯„存器 */ -#define MAC_HASH0 (MAC_BASE+0X048) /* MAC HASH寄存器 */ -#define MAC_HASH1 (MAC_BASE+0X04C) /* MAC HASH寄存器 */ -#define MAC_TXPAUSE (MAC_BASE+0X050) /* MAC控制帧寄存器 */ -#define MAC_TX_BD (MAC_BASE+0X400) -#define MAC_RX_BD (MAC_BASE+0X600) - - -/* - ************************************** - * Error Codes: - * IF SUCCESS RETURN 0, ELSE RETURN OTHER ERROR CODE, - * parameter error return (-33)/E_PAR, - * hardware error reture (-99)/E_HA - ************************************** - */ - -#define E_OK 0 /* Normal completion */ -#define E_SYS (-5) /* System error */ -#define E_NOMEM (-10) /* Insufficient memory */ -#define E_NOSPT (-17) /* Feature not supported */ -#define E_INOSPT (-18) /* Feature not supported by ITRON/FILE specification */ -#define E_RSFN (-20) /* Reserved function code number */ -#define E_RSATR (-24) /* Reserved attribute */ -#define E_PAR (-33) /* Parameter error */ -#define E_ID (-35) /* Invalid ID number */ -#define E_NOEXS (-52) /* Object does not exist */ -#define E_OBJ (-63) /* Invalid object state */ -#define E_MACV (-65) /* Memory access disabled or memory access violation */ -#define E_OACV (-66) /* Object access violation */ -#define E_CTX (-69) /* Context error */ -#define E_QOVR (-73) /* Queuing or nesting overflow */ -#define E_DLT (-81) /* Object being waited for was deleted */ -#define E_TMOUT (-85) /* Polling failure or timeout exceeded */ -#define E_RLWAI (-86) /* WAIT state was forcibly released */ - -#define E_HA (-99) /* HARD WARE ERROR */ - - -/* - ************************************** - * PMU 模å—时钟 - ************************************** - */ - -#define CLK_SGPT (1 << 16) -#define CLK_SI2S (1 << 15) -#define CLK_SSMC (1 << 14) -#define CLK_SMAC (1 << 13) -#define CLK_SUSB (1 << 12) -#define CLK_SUART3 (1 << 11) -#define CLK_SUART2 (1 << 10) -#define CLK_SUART1 (1 << 9) -#define CLK_SUART0 (1 << 8) -#define CLK_SSSI (1 << 7) -#define CLK_SAC97 (1 << 6) -#define CLK_SMMCSD (1 << 5) -#define CLK_SEMI (1 << 4) -#define CLK_SDMAC (1 << 3) -#define CLK_SPWM (1 << 2) -#define CLK_SLCDC (1 << 1) -#define CLK_SESRAM (1) - - -/*Interrupt Sources*/ - - -#define INTSRC_RTC 31 -#define INTSRC_DMAC 30 -#define INTSRC_EMI 29 -#define INTSRC_MAC 28 -#define INTSRC_TIMER1 27 -#define INTSRC_TIMER2 26 -#define INTSRC_TIMER3 25 -#define INTSRC_UART0 24 -#define INTSRC_UART1 23 -#define INTSRC_UART2 22 -#define INTSRC_UART3 21 -#define INTSRC_PWM 20 -#define INTSRC_LCDC 19 -#define INTSRC_I2S 18 -#define INTSRC_SSI 17 - -#define INTSRC_USB 15 -#define INTSRC_SMC0 14 -#define INTSRC_SMC1 13 -#define INTSRC_SDIO 12 -#define INTSRC_EXINT10 11 -#define INTSRC_EXINT9 10 -#define INTSRC_EXINT8 9 -#define INTSRC_EXINT7 8 -#define INTSRC_EXINT6 7 -#define INTSRC_EXINT5 6 -#define INTSRC_EXINT4 5 -#define INTSRC_EXINT3 4 -#define INTSRC_EXINT2 3 -#define INTSRC_EXINT1 2 -#define INTSRC_EXINT0 1 -#define INTSRC_NULL 0 - - -/*Sereral useful macros*/ -#define set_plevel(plevel) *(RP)INTC_IPLR = plevel //设置普通中断的优先级门é™ï¼Œåªæœ‰ä¼˜å…ˆçº§å¤§äºŽæ­¤å€¼çš„中断æ‰èƒ½é€šè¿‡ -#define set_int_force(intnum) *(RP)INTC_IFR = (1 << intnum) //ç½®1åŽï¼Œè½¯ä»¶å¼ºåˆ¶è¯¥ä½å¯¹åº”的中断æºå‘å‡ºä¸­æ–­ä¿¡å· -#define enable_irq(intnum) *(RP)INTC_IER |= (1 << intnum) //ç½®1åŽï¼Œå…许中断æºçš„IRQ ä¸­æ–­ä¿¡å· -#define disable_irq( intnum) *(RP)INTC_IER &= ~(1<< intnum) //ç½®0åŽï¼Œä¸å…许中断æºçš„IRQ ä¸­æ–­ä¿¡å· -#define mask_irq(intnum) *(RP)INTC_IMR |= (1 << intnum) //ç½®1åŽï¼Œå±è”½å¯¹åº”çš„IRQ ä¸­æ–­ä¿¡å· -#define unmask_irq(intnum) *(RP)INTC_IMR &= ~(1 << intnum) //ç½®0åŽï¼Œé€šè¿‡å¯¹åº”çš„IRQ ä¸­æ–­ä¿¡å· -#define mask_all_irq() *(RP)INTC_IMR = 0xFFFFFFFF //å±è”½å¯¹åº”çš„IRQ ä¸­æ–­ä¿¡å· -#define unmask_all_irq() *(RP)INTC_IMR = 0x00000000 //通过对应的IRQ ä¸­æ–­ä¿¡å· -#define enable_all_irq() *(RP)INTC_IER = 0XFFFFFFFF //å…许中断æºçš„IRQ ä¸­æ–­ä¿¡å· -#define disable_all_irq() *(RP)INTC_IER = 0X00000000 //ä¸å…许中断æºçš„IRQ ä¸­æ–­ä¿¡å· -#define InitInt() do{mask_all_irq(); enable_all_irq();}while(0) - -/* - ************************************** - * 所有程åºä¸­ç”¨åˆ°çš„Typedef - ************************************** - */ - -typedef char S8; /* signed 8-bit integer */ -typedef short S16; /* signed 16-bit integer */ -typedef long S32; /* signed 32-bit integer */ -typedef unsigned char U8; /* unsigned 8-bit integer */ -typedef unsigned short U16; /* unsigned 16-bit integer */ -typedef unsigned long U32; /* unsigned 32-bit integer */ - -typedef volatile U32 * RP; -typedef volatile U16 * RP16; -typedef volatile U8 * RP8; - -typedef void *VP; /* pointer to an unpredictable data type */ -typedef void (*FP)(); /* program start address */ - -#ifndef _BOOL_TYPE_ -#define _BOOL_TYPE_ -typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ -#endif - -typedef int ER; /* Error code. A signed integer. */ - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#define __I volatile const /*!< defines 'read only' permissions */ -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ -#define __iomem volatile - - -/*Macros for debug*/ - -#define EOUT(fmt,...) \ - do \ - { \ - rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ - rt_kprintf(fmt,##__VA_ARGS__); \ - }while(0) - -#define RT_DEBUG -#ifdef RT_DEBUG - #define DBOUT(fmt,...) \ - do \ - { \ - rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ - rt_kprintf(fmt,##__VA_ARGS__); \ - }while(0) -#else - #define DBOUT(fmt,...) \ - do{}while(0) -#endif - -#ifdef RT_DEBUG - #define ASSERT(arg) \ - if((arg) == 0) \ - { \ - while(1) \ - { \ - rt_kprintf("have a assert failure\n"); \ - } \ - } -#else - #define ASSERT(arg) \ - do \ - { \ - }while(0) -#endif - - -#define write_reg(reg,value) \ - do \ - { \ - *(RP)(reg) = value; \ - }while(0) - -#define read_reg(reg) (*(RP)reg) - - -struct rt_hw_register -{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; -}; - - -/*@}*/ - -#endif diff --git a/rt-thread/libcpu/arm/sep4020/serial.c b/rt-thread/libcpu/arm/sep4020/serial.c deleted file mode 100644 index 9bf1546..0000000 --- a/rt-thread/libcpu/arm/sep4020/serial.c +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - * 2009-04-20 yi.qiu modified according bernard's stm32 version - * 2010-10-6 wangmeng added sep4020 surpport - */ -#include -#include -#include "serial.h" - -/** - * @addtogroup SEP4020 - */ -/*@{*/ - -/* RT-Thread Device Interface */ -/** - * This function initializes serial - */ -static rt_err_t rt_serial_init (rt_device_t dev) -{ - struct serial_device* uart = (struct serial_device*) dev->user_data; - - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, - sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = uart->int_rx->save_index = 0; - } - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - rt_memset(uart->int_tx->tx_buffer, 0, - sizeof(uart->int_tx->tx_buffer)); - uart->int_tx->write_index = uart->int_tx->save_index = 0; - } - - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } - - return RT_EOK; -} - -/* save a char to serial buffer */ -static void rt_serial_savechar(struct serial_device* uart, char ch) -{ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); -} - -static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) -{ - RT_ASSERT(dev != RT_NULL); - return RT_EOK; -} - -static rt_err_t rt_serial_close(rt_device_t dev) -{ - RT_ASSERT(dev != RT_NULL); - return RT_EOK; -} - -static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - ptr = buffer; - err_code = RT_EOK; - uart = (struct serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_base_t level; - - /* interrupt mode Rx */ - while (size) - { - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size --; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - break; - } - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (uart->uart_device->lsr & USTAT_RCV_READY) - { - *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff; - ptr ++; - } - } - } - - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; -} - -static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx */ - while (uart->int_tx->save_index != uart->int_tx->write_index) - { - /* save on tx buffer */ - uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; - - -- size; - - /* move to next position */ - uart->int_tx->save_index ++; - - /* wrap save index */ - if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) - uart->int_tx->save_index = 0; - } - - /* set error code */ - if (size > 0) - err_code = -RT_EFULL; - } - else - { - /* polling mode */ - while (size) - { - /* - * to be polite with serial console add a line feed - * to the carriage return character - */ - if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) - { - while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); - uart->uart_device->dlbl_fifo.txfifo = '\r'; - } - - while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); - uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF); - - ++ptr; --size; - } - } - - /* set error code */ - rt_set_errno(err_code); - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; -} - -static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) -{ - RT_ASSERT(dev != RT_NULL); - - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; - - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } - - return RT_EOK; -} - -/* - * serial register - */ -rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial) -{ - RT_ASSERT(device != RT_NULL); - - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; - - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); -} - -/* ISR for serial interrupt */ -void rt_hw_serial_isr(rt_device_t device) -{ - struct serial_device* uart = (struct serial_device*) device->user_data; - - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); - - /* save on rx buffer */ - while (uart->uart_device->lsr & USTAT_RCV_READY) - { - rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff); - } - - /* invoke callback */ - if (device->rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; - - device->rx_indicate(device, rx_length); - } -} - -/*@}*/ - diff --git a/rt-thread/libcpu/arm/sep4020/serial.h b/rt-thread/libcpu/arm/sep4020/serial.h deleted file mode 100644 index 26ec0f6..0000000 --- a/rt-thread/libcpu/arm/sep4020/serial.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - * 2009-04-20 yi.qiu modified according bernard's stm32 version - * 2010-10-6 wangmeng added sep4020 surpport - */ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - -#include - -#define USTAT_RCV_READY 0x01 /* receive data ready */ -#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */ -#define BPS 115200 /* serial baudrate */ - -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 - -/*For sep4020's uart have several secondary function*/ -/*we use union to decribe it*/ - -union dlbl_fifo -{ - rt_uint32_t dlbl; - rt_uint32_t rxfifo; - rt_uint32_t txfifo; -}; - -union dlbh_ier -{ - rt_uint32_t dlbh; - rt_uint32_t ier; -}; - -union iir_fcr -{ - rt_uint32_t iir; - rt_uint32_t fcr; -}; - -struct serial_int_rx -{ - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; -}; - -struct serial_int_tx -{ - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; -}; - -typedef struct uartport -{ - union dlbl_fifo dlbl_fifo; - union dlbh_ier dlbh_ier; - union iir_fcr iir_fcr; - rt_uint32_t lcr; - rt_uint32_t mcr; - rt_uint32_t lsr; - rt_uint32_t msr; -}uartport; - -struct serial_device -{ - uartport* uart_device; - - /* rx structure */ - struct serial_int_rx* int_rx; - - /* tx structure */ - struct serial_int_tx* int_tx; -}; - -rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); - -void rt_hw_serial_isr(rt_device_t device); - - -#endif diff --git a/rt-thread/libcpu/arm/sep4020/stack.c b/rt-thread/libcpu/arm/sep4020/stack.c deleted file mode 100644 index 3a7b5fd..0000000 --- a/rt-thread/libcpu/arm/sep4020/stack.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard the first version - */ -#include -#include -/** - * @addtogroup S3C24X0 - */ -/*@{*/ - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - - stack_addr += sizeof(rt_uint32_t); - stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); - stk = (rt_uint32_t *)stack_addr; - *(--stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0xdeadbeef; /* r12 */ - *(--stk) = 0xdeadbeef; /* r11 */ - *(--stk) = 0xdeadbeef; /* r10 */ - *(--stk) = 0xdeadbeef; /* r9 */ - *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = 0xdeadbeef; /* r4 */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = 0xdeadbeef; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - *(--stk) = Mode_SVC; /* cpsr */ - *(--stk) = Mode_SVC; /* spsr */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/sep4020/start_rvds.S b/rt-thread/libcpu/arm/sep4020/start_rvds.S deleted file mode 100644 index bf5431e..0000000 --- a/rt-thread/libcpu/arm/sep4020/start_rvds.S +++ /dev/null @@ -1,385 +0,0 @@ -;============================================================================================== -; star_rvds.s for Keil MDK 4.10 -; -; SEP4020 start up code -; -; Change Logs: -; Date Author Notes -; 2010-03-17 zchong -;============================================================================================= - -PMU_PLTR EQU 0x10001000 ; PLLµÄÎȶ¨¹ý¶Éʱ¼ä -PMU_PMCR EQU 0x10001004 ; ϵͳÖ÷ʱÖÓPLLµÄ¿ØÖƼĴæÆ÷ -PMU_PUCR EQU 0x10001008 ; USBʱÖÓPLLµÄ¿ØÖƼĴæÆ÷ -PMU_PCSR EQU 0x1000100C ; ÄÚ²¿Ä£¿éʱÖÓÔ´¹©¸øµÄ¿ØÖƼĴæÆ÷ -PMU_PDSLOW EQU 0x10001010 ; SLOW״̬ÏÂʱÖӵķÖƵÒò×Ó -PMU_PMDR EQU 0x10001014 ; оƬ¹¤×÷ģʽ¼Ä´æÆ÷ -PMU_RCTR EQU 0x10001018 ; Reset¿ØÖƼĴæÆ÷ -PMU_CLRWAKUP EQU 0x1000101C ; WakeUpÇå³ý¼Ä´æÆ÷ - -RTC_CTR EQU 0x1000200C ; RTC¿ØÖƼĴæÆ÷ - -INTC_IER EQU 0x10000000 ; IRQÖжÏÔÊÐí¼Ä´æÆ÷ -INTC_IMR EQU 0x10000008 ; IRQÖжÏÆÁ±Î¼Ä´æÆ÷ -INTC_IFSR EQU 0x10000030 ; IRQÖжÏ×îÖÕ״̬¼Ä´æÆ÷ -INTC_FIER EQU 0x100000C0 ; FIQÖжÏÔÊÐí¼Ä´æÆ÷ -INTC_FIMR EQU 0x100000C4 ; FIQÖжÏÆÁ±Î¼Ä´æÆ÷ - -EMI_CSACONF EQU 0x11000000 ; CSA²ÎÊýÅäÖüĴæÆ÷ -EMI_CSECONF EQU 0x11000010 ; CSE²ÎÊýÅäÖüĴæÆ÷ -EMI_CSFCONF EQU 0x11000014 ; CSF²ÎÊýÅäÖüĴæÆ÷ -EMI_SDCONF1 EQU 0x11000018 ; SDRAMʱÐòÅäÖüĴæÆ÷1 -EMI_SDCONF2 EQU 0x1100001C ; SDRAMʱÐòÅäÖüĴæÆ÷2, SDRAM³õʼ»¯Óõ½µÄÅäÖÃÐÅÏ¢ -EMI_REMAPCONF EQU 0x11000020 ; Ƭѡ¿Õ¼ä¼°µØÖ·Ó³ÉäREMAPÅäÖüĴæÆ÷ - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled -NOINT EQU 0xc0 -MASK_MODE EQU 0x0000003F -MODE_SVC32 EQU 0x00000013 - -; Internal Memory Base Addresses -FLASH_BASE EQU 0x20000000 -RAM_BASE EQU 0x04000000 -SDRAM_BASE EQU 0x30000000 - -; Stack -Unused_Stack_Size EQU 0x00000100 -Svc_Stack_Size EQU 0x00001000 -Abt_Stack_Size EQU 0x00000000 -Fiq_Stack_Size EQU 0x00000000 -Irq_Stack_Size EQU 0x00001000 -Usr_Stack_Size EQU 0x00000000 - -;SVC STACK - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Svc_Stack SPACE Svc_Stack_Size -__initial_sp -Svc_Stack_Top - -;IRQ STACK - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Irq_Stack SPACE Irq_Stack_Size -Irq_Stack_Top - -;UNUSED STACK - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Unused_Stack SPACE Unused_Stack_Size -Unused_Stack_Top - - -; Heap -Heap_Size EQU 0x0000100 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT Heap_Mem -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - -; Area Definition and Entry Point -; Startup Code must be linked first at Address at which it expects to run. - - AREA RESET, CODE, READONLY - ARM - -; Exception Vectors -; Mapped to Address 0. -; Absolute addressing mode must be used. -; Dummy Handlers are implemented as infinite loops which can be modified. - EXPORT Entry_Point -Entry_Point -Vectors LDR PC,Reset_Addr - LDR PC,Undef_Addr - LDR PC,SWI_Addr - LDR PC,PAbt_Addr - LDR PC,DAbt_Addr - NOP ; Reserved Vector - LDR PC,IRQ_Addr - LDR PC,FIQ_Addr - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SWI_Addr DCD SWI_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler - DCD 0 ; Reserved Address -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - -Undef_Handler B Undef_Handler -SWI_Handler B SWI_Handler -PAbt_Handler B Abort_Handler -DAbt_Handler B Abort_Handler -FIQ_Handler B FIQ_Handler - -Abort_Handler PROC - ARM - EXPORT Abort_Handler -DeadLoop BHI DeadLoop ; Abort happened in irq mode, halt system. - ENDP - - -; Reset Handler - ;IMPORT __user_initial_stackheap - EXPORT Reset_Handler -Reset_Handler - -;**************************************************************** -;* Shutdown watchdog -;**************************************************************** - LDR R0,=RTC_CTR - LDR R1,=0x0 - STR R1,[R0] - -;**************************************************************** -;* shutdown interrupts -;**************************************************************** - MRS R0, CPSR - BIC R0, R0, #MASK_MODE - ORR R0, R0, #MODE_SVC32 - ORR R0, R0, #I_Bit - ORR R0, R0, #F_Bit - MSR CPSR_c, r0 - - LDR R0,=INTC_IER - LDR R1,=0x0 - STR R1,[R0] - LDR R0,=INTC_IMR - LDR R1,=0xFFFFFFFF - STR R1,[R0] - - LDR R0,=INTC_FIER - LDR R1,=0x0 - STR R1,[R0] - LDR R0,=INTC_FIMR - LDR R1,=0x0F - STR R1,[R0] - -;**************************************************************** -;* Initialize Stack Pointer -;**************************************************************** - - LDR SP, =Svc_Stack_Top ;init SP_svc - - MOV R4, #0xD2 ;chmod to irq and init SP_irq - MSR cpsr_c, R4 - LDR SP, =Irq_Stack_Top - - MOV R4, #0XD1 ;chomod to fiq and init SP_fiq - MSR cpsr_c, R4 - LDR SP, =Unused_Stack_Top - - MOV R4, #0XD7 ;chomod to abt and init SP_ABT - MSR cpsr_c, R4 - LDR SP, =Unused_Stack_Top - - MOV R4, #0XDB ;chomod to undf and init SP_UNDF - MSR cpsr_c, R4 - LDR SP, =Unused_Stack_Top - - ;chomod to abt and init SP_sys - MOV R4, #0xDF ;all interrupts disabled - MSR cpsr_c, R4 ;SYSTEM mode, @32-bit code mode - LDR SP, =Unused_Stack_Top - - MOV R4, #0XD3 ;chmod to svc modle, CPSR IRQ bit is disable - MSR cpsr_c, R4 - - - -;**************************************************************** -;* Initialize PMU & System Clock -;**************************************************************** - - LDR R4, =PMU_PCSR ; ´òËùÓÐÄ£¿éʱÖÓ - LDR R5, =0x0001ffff - STR R5, [ R4 ] - - LDR R4, =PMU_PLTR ; ÅäÖÃPLLÎȶ¨¹ý¶Èʱ¼äΪ±£ÊØÖµ50us*100M. - LDR R5, =0x00fa00fa - STR R5, [ R4 ] - - LDR R4, =PMU_PMDR ; ÓÉSLOWģʽ½øÈëNORMALģʽ - LDR R5, =0x00000001 - STR R5, [ R4 ] - - LDR R4, =PMU_PMCR ; ÅäÖÃϵͳʱÖÓΪ80MHz - LDR R5, =0x00004009 ; 400b -- 88M - STR R5, [ R4 ] - - ;PMU_PMCR¼Ä´æÆ÷µÚ15λÐèÒªÓдӵ͵½¸ßµÄ·­×ª£¬²ÅÄÜ´¥·¢PLLµÄʱÖÓÅäÖà - LDR R4, =PMU_PMCR - LDR R5, =0x0000c009 - STR R5, [ R4 ] - -;**************************************************************** -;* ³õʼ»¯EMI -;**************************************************************** - - IF :DEF:INIT_EMI - - LDR R4, =EMI_CSACONF ; CSAƬѡʱÐò²ÎÊýÅäÖà - LDR R5, =0x08a6a6a1 - STR R5, [ R4 ] - - LDR R4, =EMI_CSECONF ; CSEƬѡʱÐò²ÎÊýÅäÖÃ,×î±£ÊØÅäÖà - LDR R5, =0x8cfffff1 - STR R5, [ R4 ] - - LDR R4, =EMI_SDCONF1 ; SDRAM²ÎÊýÅäÖÃ1 - LDR R5, =0x1E104177 - STR R5, [ R4 ] - - LDR R4, =EMI_SDCONF2 ; SDRAM²ÎÊýÅäÖÃ2 - LDR R5, =0x80001860 - STR R5, [ R4 ] - - ENDIF - -; Copy Exception Vectors to Internal RAM - - IF :DEF:RAM_INTVEC - - ADR R8, Vectors ; Source - LDR R9, =RAM_BASE ; Destination - LDMIA R8!, {R0-R7} ; Load Vectors - STMIA R9!, {R0-R7} ; Store Vectors - LDMIA R8!, {R0-R7} ; Load Handler Addresses - STMIA R9!, {R0-R7} ; Store Handler Addresses - - ENDIF - -; Remap on-chip RAM to address 0 - - IF :DEF:REMAP - - LDR R0, =EMI_REMAPCONF - IF :DEF:RAM_INTVEC - MOV R1, #0x80000000 - ELSE - MOV R1, #0x0000000b - ENDIF - STR R1, [R0, #0] ; Remap - - ENDIF - -;*************************************************************** -;* Open irq interrupt -;*************************************************************** - - MRS R4, cpsr - BIC R4, R4, #0x80 ; set bit7 to zero - MSR cpsr_c, R4 - -; Enter the C code - IMPORT __main - LDR R0,=__main - BX R0 - - - IMPORT rt_interrupt_enter - IMPORT rt_interrupt_leave - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread - IMPORT rt_hw_trap_irq - -IRQ_Handler PROC - EXPORT IRQ_Handler - STMFD sp!, {r0-r12,lr} - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave - - ; if rt_thread_switch_interrupt_flag set, jump to - ; rt_hw_context_switch_interrupt_do and don't return - LDR r0, =rt_thread_switch_interrupt_flag - LDR r1, [r0] - CMP r1, #1 - BEQ rt_hw_context_switch_interrupt_do - - LDMFD sp!, {r0-r12,lr} - SUBS pc, lr, #4 - ENDP - -; /* -; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) -; */ -rt_hw_context_switch_interrupt_do PROC - EXPORT rt_hw_context_switch_interrupt_do - MOV r1, #0 ; clear flag - STR r1, [r0] - - LDMFD sp!, {r0-r12,lr}; reload saved registers - STMFD sp!, {r0-r3} ; save r0-r3 - MOV r1, sp - ADD sp, sp, #16 ; restore sp - SUB r2, lr, #4 ; save old task's pc to r2 - - MRS r3, spsr ; get cpsr of interrupt thread - - ; switch to SVC mode and no interrupt - MSR cpsr_c, #I_Bit :OR F_Bit :OR Mode_SVC - - STMFD sp!, {r2} ; push old task's pc - STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 - MOV r4, r1 ; Special optimised code below - MOV r5, r3 - LDMFD r4!, {r0-r3} - STMFD sp!, {r0-r3} ; push old task's r3-r0 - STMFD sp!, {r5} ; push old task's cpsr - MRS r4, spsr - STMFD sp!, {r4} ; push old task's spsr - - LDR r4, =rt_interrupt_from_thread - LDR r5, [r4] - STR sp, [r5] ; store sp in preempted tasks's TCB - - LDR r6, =rt_interrupt_to_thread - LDR r6, [r6] - LDR sp, [r6] ; get new task's stack pointer - - LDMFD sp!, {r4} ; pop new task's spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task's psr - MSR cpsr_cxsf, r4 - - LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc - ENDP - - - - ALIGN - IF :DEF:__MICROLIB - - EXPORT __heap_base - EXPORT __heap_limit - EXPORT __initial_sp - - ELSE ;__MICROLIB -; User Initial Stack & Heap - AREA |.text|, CODE, READONLY - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, = (Svc_Stack + Svc_Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Svc_Stack - BX LR - ALIGN - ENDIF - END diff --git a/rt-thread/libcpu/arm/sep4020/trap.c b/rt-thread/libcpu/arm/sep4020/trap.c deleted file mode 100644 index 441a55b..0000000 --- a/rt-thread/libcpu/arm/sep4020/trap.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - * 2006-05-27 Bernard add skyeye support - * 2007-11-19 Yi.Qiu fix rt_hw_trap_irq function - * 2013-03-29 aozima Modify the interrupt interface implementations. - */ - -#include -#include - -#include - -/** - * @addtogroup S3C24X0 - */ -/*@{*/ - -extern struct rt_thread *rt_current_thread; - -/** - * this function will show registers of CPU - * - * @param regs the registers point - */ - -void rt_hw_show_register (struct rt_hw_register *regs) -{ - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); -} - -/** - * When ARM7TDMI comes across an instruction which it cannot handle, - * it takes the undefined instruction trap. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_udef(struct rt_hw_register *regs) -{ - rt_hw_show_register(regs); - - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - - rt_hw_cpu_shutdown(); -} - -/** - * The software interrupt instruction (SWI) is used for entering - * Supervisor mode, usually to request a particular supervisor - * function. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_swi(struct rt_hw_register *regs) -{ - rt_hw_show_register(regs); - - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during an instruction prefetch. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_pabt(struct rt_hw_register *regs) -{ - rt_hw_show_register(regs); - - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during a data access. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_dabt(struct rt_hw_register *regs) -{ - rt_hw_show_register(regs); - - rt_kprintf("data abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - - rt_hw_cpu_shutdown(); -} - -/** - * Normally, system will never reach here - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_resv(struct rt_hw_register *regs) -{ - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); -} - -extern struct rt_irq_desc isr_table[]; - -void rt_hw_trap_irq(void) -{ - unsigned long intstat; - rt_uint32_t irq = 0; - rt_isr_handler_t isr_func; - void *param; - - /*Get the final intrrupt source*/ - intstat = *(RP)(INTC_IFSR);; - - /*Shift to get the intrrupt number*/ - while(intstat != 1) - { - intstat = intstat >> 1; - irq++; - } - - /* get interrupt service routine */ - isr_func = isr_table[irq].handler; - param = isr_table[irq].param; - - /* turn to interrupt service routine */ - isr_func(irq, param); - -#ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; -#endif /* RT_USING_INTERRUPT_INFO */ -} - -void rt_hw_trap_fiq(void) -{ - rt_kprintf("fast interrupt request\n"); -} - -/*@}*/ diff --git a/rt-thread/libcpu/arm/zynqmp-r5/SConscript b/rt-thread/libcpu/arm/zynqmp-r5/SConscript deleted file mode 100644 index a98862a..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM in ['gcc']: - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM in ['iccarm']: - src += Glob('*_iar.S') - -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/rt-thread/libcpu/arm/zynqmp-r5/armv7.h b/rt-thread/libcpu/arm/zynqmp-r5/armv7.h deleted file mode 100644 index c70d210..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/armv7.h +++ /dev/null @@ -1,54 +0,0 @@ -#ifndef __ARMV7_H__ -#define __ARMV7_H__ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -#ifndef VFP_DATA_NR -#define VFP_DATA_NR 32 -#endif - -/* the exception stack without VFP registers */ -struct rt_hw_exp_stack -{ - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; -}; - -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define MONITORMODE 0x16 -#define ABORTMODE 0x17 -#define HYPMODE 0x1b -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -#define T_Bit (1<<5) -#define F_Bit (1<<6) -#define I_Bit (1<<7) -#define A_Bit (1<<8) -#define E_Bit (1<<9) -#define J_Bit (1<<24) - -#endif diff --git a/rt-thread/libcpu/arm/zynqmp-r5/cache.c b/rt-thread/libcpu/arm/zynqmp-r5/cache.c deleted file mode 100644 index a6ee643..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/cache.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * Copyright (c) 2006 - 2021, RT-Thread Development Team - * Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved. - * Copyright (c) 2021 WangHuachen. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Change Logs: - * Date Author Notes - * 2020-03-19 WangHuachen first version - * 2021-05-10 WangHuachen add more functions - */ - -#include -#include -#include - -#include "xpseudo_asm_gcc.h" -#include "xreg_cortexr5.h" - -#define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */ - -typedef intptr_t INTPTR; -typedef rt_uint32_t u32; - -#if defined (__GNUC__) -#define asm_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ - XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) - -#define asm_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) - -#define asm_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) - -#define asm_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \ - XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) -#elif defined (__ICCARM__) -#define asm_inval_dc_line_mva_poc(param) __asm volatile("mcr " \ - XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) - -#define asm_clean_inval_dc_line_sw(param) __asm volatile("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) - -#define asm_clean_inval_dc_line_mva_poc(param) __asm volatile("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) - -#define asm_inval_ic_line_mva_pou(param) __asm volatile("mcr " \ - XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) -#endif - -void Xil_DCacheEnable(void); -void Xil_DCacheDisable(void); -void Xil_DCacheInvalidate(void); -void Xil_DCacheInvalidateRange(INTPTR adr, u32 len); -void Xil_DCacheFlush(void); -void Xil_DCacheFlushRange(INTPTR adr, u32 len); -void Xil_DCacheInvalidateLine(INTPTR adr); -void Xil_DCacheFlushLine(INTPTR adr); -void Xil_DCacheStoreLine(INTPTR adr); -void Xil_ICacheEnable(void); -void Xil_ICacheDisable(void); -void Xil_ICacheInvalidate(void); -void Xil_ICacheInvalidateRange(INTPTR adr, u32 len); -void Xil_ICacheInvalidateLine(INTPTR adr); - -void Xil_DCacheEnable(void) -{ - register u32 CtrlReg; - - /* enable caches only if they are disabled */ -#if defined (__GNUC__) - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); -#endif - if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) == 0x00000000U) - { - /* invalidate the Data cache */ - Xil_DCacheInvalidate(); - - /* enable the Data cache */ - CtrlReg |= (XREG_CP15_CONTROL_C_BIT); - - mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); - } -} - -void Xil_DCacheDisable(void) -{ - register u32 CtrlReg; - - /* clean and invalidate the Data cache */ - Xil_DCacheFlush(); - - /* disable the Data cache */ -#if defined (__GNUC__) - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); -#endif - - CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); - - mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); -} - -void Xil_DCacheInvalidate(void) -{ - u32 currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); - - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - - /*invalidate all D cache*/ - mtcp(XREG_CP15_INVAL_DC_ALL, 0); - - mtcpsr(currmask); -} - -void Xil_DCacheInvalidateLine(INTPTR adr) -{ - u32 currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); - - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F))); - - /* Wait for invalidate to complete */ - dsb(); - - mtcpsr(currmask); -} - -void Xil_DCacheInvalidateRange(INTPTR adr, u32 len) -{ - const u32 cacheline = 32U; - u32 end; - u32 tempadr = adr; - u32 tempend; - u32 currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); - - if (len != 0U) - { - end = tempadr + len; - tempend = end; - /* Select L1 Data cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); - - if ((tempadr & (cacheline - 1U)) != 0U) - { - tempadr &= (~(cacheline - 1U)); - - Xil_DCacheFlushLine(tempadr); - } - if ((tempend & (cacheline - 1U)) != 0U) - { - tempend &= (~(cacheline - 1U)); - - Xil_DCacheFlushLine(tempend); - } - - while (tempadr < tempend) - { - - /* Invalidate Data cache line */ - asm_inval_dc_line_mva_poc(tempadr); - - tempadr += cacheline; - } - } - - dsb(); - mtcpsr(currmask); -} - -void Xil_DCacheFlush(void) -{ - register u32 CsidReg, C7Reg; - u32 CacheSize, LineSize, NumWays; - u32 Way, WayIndex, Set, SetIndex, NumSet; - u32 currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); - - /* Select cache level 0 and D cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - -#if defined (__GNUC__) - CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg); -#endif - /* Determine Cache Size */ - - CacheSize = (CsidReg >> 13U) & 0x000001FFU; - CacheSize += 0x00000001U; - CacheSize *= (u32)128; /* to get number of bytes */ - - /* Number of Ways */ - NumWays = (CsidReg & 0x000003ffU) >> 3U; - NumWays += 0x00000001U; - - /* Get the cacheline size, way size, index size from csidr */ - LineSize = (CsidReg & 0x00000007U) + 0x00000004U; - - NumSet = CacheSize / NumWays; - NumSet /= (0x00000001U << LineSize); - - Way = 0U; - Set = 0U; - - /* Invalidate all the cachelines */ - for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) - { - for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) - { - C7Reg = Way | Set; - /* Flush by Set/Way */ - asm_clean_inval_dc_line_sw(C7Reg); - - Set += (0x00000001U << LineSize); - } - Set = 0U; - Way += 0x40000000U; - } - - /* Wait for flush to complete */ - dsb(); - mtcpsr(currmask); - - mtcpsr(currmask); -} - -void Xil_DCacheFlushLine(INTPTR adr) -{ - u32 currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); - - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - - mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F))); - - /* Wait for flush to complete */ - dsb(); - mtcpsr(currmask); -} - -void Xil_DCacheFlushRange(INTPTR adr, u32 len) -{ - u32 LocalAddr = adr; - const u32 cacheline = 32U; - u32 end; - u32 currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); - - if (len != 0x00000000U) - { - /* Back the starting address up to the start of a cache line - * perform cache operations until adr+len - */ - end = LocalAddr + len; - LocalAddr &= ~(cacheline - 1U); - - while (LocalAddr < end) - { - /* Flush Data cache line */ - asm_clean_inval_dc_line_mva_poc(LocalAddr); - - LocalAddr += cacheline; - } - } - dsb(); - mtcpsr(currmask); -} - -void Xil_DCacheStoreLine(INTPTR adr) -{ - u32 currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); - - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1F))); - - /* Wait for store to complete */ - dsb(); - isb(); - - mtcpsr(currmask); -} - -void Xil_ICacheEnable(void) -{ - register u32 CtrlReg; - - /* enable caches only if they are disabled */ -#if defined (__GNUC__) - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); -#endif - if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) == 0x00000000U) - { - /* invalidate the instruction cache */ - mtcp(XREG_CP15_INVAL_IC_POU, 0); - - /* enable the instruction cache */ - CtrlReg |= (XREG_CP15_CONTROL_I_BIT); - - mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); - } -} - -void Xil_ICacheDisable(void) -{ - register u32 CtrlReg; - - dsb(); - - /* invalidate the instruction cache */ - mtcp(XREG_CP15_INVAL_IC_POU, 0); - - /* disable the instruction cache */ -#if defined (__GNUC__) - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); -#endif - - CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT); - - mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); -} - -void Xil_ICacheInvalidate(void) -{ - u32 currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); - - mtcp(XREG_CP15_CACHE_SIZE_SEL, 1); - - /* invalidate the instruction cache */ - mtcp(XREG_CP15_INVAL_IC_POU, 0); - - /* Wait for invalidate to complete */ - dsb(); - mtcpsr(currmask); -} - -void Xil_ICacheInvalidateLine(INTPTR adr) -{ - u32 currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); - - mtcp(XREG_CP15_CACHE_SIZE_SEL, 1); - mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1F))); - - /* Wait for invalidate to complete */ - dsb(); - mtcpsr(currmask); -} - -void Xil_ICacheInvalidateRange(INTPTR adr, u32 len) -{ - u32 LocalAddr = adr; - const u32 cacheline = 32U; - u32 end; - u32 currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); - if (len != 0x00000000U) - { - /* Back the starting address up to the start of a cache line - * perform cache operations until adr+len - */ - end = LocalAddr + len; - LocalAddr = LocalAddr & ~(cacheline - 1U); - - /* Select cache L0 I-cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); - - while (LocalAddr < end) - { - - /* Invalidate L1 I-cache line */ - asm_inval_ic_line_mva_pou(LocalAddr); - - LocalAddr += cacheline; - } - } - - /* Wait for invalidate to complete */ - dsb(); - mtcpsr(currmask); -} - -void rt_hw_cpu_icache_ops(int ops, void *addr, int size) -{ - if (ops == RT_HW_CACHE_INVALIDATE) - Xil_ICacheInvalidateRange((INTPTR)addr, size); -} - -void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) -{ - if (ops == RT_HW_CACHE_FLUSH) - Xil_DCacheFlushRange((intptr_t)addr, size); - else if (ops == RT_HW_CACHE_INVALIDATE) - Xil_DCacheInvalidateRange((intptr_t)addr, size); -} - -rt_base_t rt_hw_cpu_icache_status(void) -{ - register u32 CtrlReg; -#if defined (__GNUC__) - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); -#endif - return CtrlReg & XREG_CP15_CONTROL_I_BIT; -} - -rt_base_t rt_hw_cpu_dcache_status(void) -{ - register u32 CtrlReg; -#if defined (__GNUC__) - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); -#endif - return CtrlReg & XREG_CP15_CONTROL_C_BIT; -} diff --git a/rt-thread/libcpu/arm/zynqmp-r5/context_gcc.S b/rt-thread/libcpu/arm/zynqmp-r5/context_gcc.S deleted file mode 100644 index a5eee0b..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/context_gcc.S +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-03-19 WangHuachen first version - */ - -.section .text, "ax" -/* - * rt_base_t rt_hw_interrupt_disable(); - */ -.globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mrs r0, cpsr - cpsid if - bx lr - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ -.globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - msr cpsr, r0 - bx lr - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to - */ -.globl rt_hw_context_switch_to -rt_hw_context_switch_to: - ldr sp, [r0] @ get new task stack pointer - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - ldmfd sp!, {r1} /* Restore floating point registers */ - vmsr FPEXC, r1 - ldmfd sp!, {r1} - vmsr FPSCR, r1 - vldmia sp!, {d0-d15} -#endif - - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc - - -.section .text.isr, "ax" -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to - */ -.globl rt_hw_context_switch -rt_hw_context_switch: - stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) - stmfd sp!, {r0-r12, lr} @ push lr & register file - - mrs r4, cpsr - tst lr, #0x01 - beq _ARM_MODE - orr r4, r4, #0x20 @ it's thumb code - -_ARM_MODE: - stmfd sp!, {r4} @ push cpsr - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - vstmdb sp!, {d0-d15} /* Store floating point registers */ - vmrs r4, FPSCR - stmfd sp!,{r4} - vmrs r4, FPEXC - stmfd sp!,{r4} -#endif - - str sp, [r0] @ store sp in preempted tasks TCB - ldr sp, [r1] @ get new task stack pointer - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - ldmfd sp!, {r1} /* Restore floating point registers */ - vmsr FPEXC, r1 - ldmfd sp!, {r1} - vmsr FPSCR, r1 - vldmia sp!, {d0-d15} -#endif - - ldmfd sp!, {r4} @ pop new task cpsr to spsr - msr spsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - */ -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -.globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - ldr r2, =rt_thread_switch_interrupt_flag - ldr r3, [r2] - cmp r3, #1 - beq _reswitch - mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 - str r3, [r2] - ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread - str r0, [r2] -_reswitch: - ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread - str r1, [r2] - bx lr diff --git a/rt-thread/libcpu/arm/zynqmp-r5/cpu.c b/rt-thread/libcpu/arm/zynqmp-r5/cpu.c deleted file mode 100644 index 788df69..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/cpu.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-03-19 WangHuachen first version - */ - -#include -#include -#include "zynqmp-r5.h" - -void rt_hw_cpu_reset() -{ - __REG32(ZynqMP_CRL_APB_BASEADDR + ZynqMP_CRL_APB_RESET_CTRL) |= ZynqMP_RESET_MASK; - while (1); /* loop forever and wait for reset to happen */ - /* NEVER REACHED */ -} - -/** - * shutdown CPU - * - */ -void rt_hw_cpu_shutdown() -{ - rt_base_t level; - rt_kprintf("shutdown...\n"); - - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } -} diff --git a/rt-thread/libcpu/arm/zynqmp-r5/gic.c b/rt-thread/libcpu/arm/zynqmp-r5/gic.c deleted file mode 100644 index 67360d9..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/gic.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-03-19 WangHuachen first version - */ - -#include -#include "board.h" -#include "gic.h" - -/* ZynqMP-RPU uses the Arm PL-390 generic interrupt controller that is - * compliant to the GICv1 architecture specification. */ - -struct arm_gic -{ - rt_uint32_t offset; - - rt_uint32_t dist_hw_base; - rt_uint32_t cpu_hw_base; -}; - -static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; - -#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00) -#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04) -#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08) -#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c) -#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10) -#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14) -#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18) - -#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000) -#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004) -#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4) -#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4) -#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) -#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) -#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4) -#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4) -#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4) -#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) -#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) -#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8) - -static unsigned int _gic_max_irq; - -int arm_gic_get_active_irq(rt_uint32_t index) -{ - int irq; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base); - irq += _gic_table[index].offset; - return irq; -} - -void arm_gic_ack(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; - GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; -} - -void arm_gic_mask(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; -} - -void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) -{ - rt_uint32_t old_tgt; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); - - old_tgt &= ~(0x0FFUL << ((irq % 4)*8)); - old_tgt |= cpumask << ((irq % 4)*8); - - GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; -} - -void arm_gic_umask(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; -} - -void arm_gic_dump_type(rt_uint32_t index) -{ - unsigned int gic_type; - - gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); - rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", - (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf, - _gic_table[index].dist_hw_base, - _gic_max_irq, - gic_type & (1 << 10) ? "has" : "no", - gic_type); -} - -int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) -{ - unsigned int gic_type, i; - rt_uint32_t cpumask = 1 << 0; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - _gic_table[index].dist_hw_base = dist_base; - _gic_table[index].offset = irq_start; - - /* Find out how many interrupts are supported. */ - gic_type = GIC_DIST_TYPE(dist_base); - _gic_max_irq = ((gic_type & 0x1f) + 1) * 32; - - /* - * The GIC only supports up to 1020 interrupt sources. - * Limit this to either the architected maximum, or the - * platform maximum. - */ - if (_gic_max_irq > 1020) - _gic_max_irq = 1020; - if (_gic_max_irq > ARM_GIC_NR_IRQS) - _gic_max_irq = ARM_GIC_NR_IRQS; - - cpumask |= cpumask << 8; - cpumask |= cpumask << 16; - - GIC_DIST_CTRL(dist_base) = 0x0; - - /* Set all global interrupts to be level triggered, active low. */ - for (i = 32; i < _gic_max_irq; i += 16) - GIC_DIST_CONFIG(dist_base, i) = 0x0; - - /* Set all global interrupts to this CPU only. */ - for (i = 32; i < _gic_max_irq; i += 4) - GIC_DIST_TARGET(dist_base, i) = cpumask; - - /* Set priority on all interrupts. */ - for (i = 0; i < _gic_max_irq; i += 4) - GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0; - - /* Disable all interrupts. */ - for (i = 0; i < _gic_max_irq; i += 32) - GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff; - - /* Enable interrupt. */ - GIC_DIST_CTRL(dist_base) = 0x01; - - return 0; -} - -int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - _gic_table[index].cpu_hw_base = cpu_base; - - GIC_CPU_PRIMASK(cpu_base) = 0xf0; - /* Enable CPU interrupt */ - GIC_CPU_CTRL(cpu_base) = 0x01; - - return 0; -} - -void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq) -{ - unsigned int reg; - - RT_ASSERT(irq <= 15); - RT_ASSERT(target_cpu <= 255); - - reg = (target_cpu << 16) | irq; - GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = reg; -} - -void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq) -{ - /* SGI will be cleared automatically. */ -} diff --git a/rt-thread/libcpu/arm/zynqmp-r5/gic.h b/rt-thread/libcpu/arm/zynqmp-r5/gic.h deleted file mode 100644 index 3f591c0..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/gic.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-03-19 WangHuachen first version - */ - -#ifndef __GIC_H__ -#define __GIC_H__ - -int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); -int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); - -void arm_gic_mask(rt_uint32_t index, int irq); -void arm_gic_umask(rt_uint32_t index, int irq); -void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); - -int arm_gic_get_active_irq(rt_uint32_t index); -void arm_gic_ack(rt_uint32_t index, int irq); - -void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq); -void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq); - -void arm_gic_dump_type(rt_uint32_t index); - -#endif - diff --git a/rt-thread/libcpu/arm/zynqmp-r5/interrupt.c b/rt-thread/libcpu/arm/zynqmp-r5/interrupt.c deleted file mode 100644 index fa37674..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/interrupt.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-03-19 WangHuachen first version - */ - -#include -#include -#include "zynqmp-r5.h" -#include "interrupt.h" -#include "gic.h" - -#define MAX_HANDLERS IRQ_ZynqMP_MAXNR - -extern volatile rt_uint8_t rt_interrupt_nest; - -/* exception and interrupt handler table */ -struct rt_irq_desc isr_table[MAX_HANDLERS]; -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - - -void rt_hw_interrupt_handle(int vector, void *param) -{ - rt_kprintf("UN-handled interrupt %d occurred!!!\n", vector); -} - -void rt_hw_interrupt_init(void) -{ - register rt_uint32_t idx; - - /* the initialization is done in fsbl */ - - /* init exceptions table */ - rt_memset(isr_table, 0x00, sizeof(isr_table)); - for (idx = 0; idx < MAX_HANDLERS; idx++) - { - isr_table[idx].handler = rt_hw_interrupt_handle; - } - - /* initialize ARM GIC */ - arm_gic_dist_init(0, ZynqMP_GIC_DIST_BASE, 0); - arm_gic_cpu_init(0, ZynqMP_GIC_CPU_BASE); - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - arm_gic_mask(0, vector); -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - arm_gic_umask(0, vector); -} - -/** - * This function returns the active interrupt number. - * @param none - */ -int rt_hw_interrupt_get_irq(void) -{ - return arm_gic_get_active_irq(0) & GIC_ACK_INTID_MASK; -} - -/** - * This function acknowledges the interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_ack(int vector) -{ - arm_gic_ack(0, vector); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param handler the interrupt service routine to be installed - * @param param the parameter for interrupt service routine - * @param name the interrupt name - * - * @return the old handler - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if (vector < MAX_HANDLERS) - { - old_handler = isr_table[vector].handler; - - if (handler != RT_NULL) - { -#ifdef RT_USING_INTERRUPT_INFO - rt_snprintf(isr_table[vector].name, RT_NAME_MAX, "%s", name); -#endif /* RT_USING_INTERRUPT_INFO */ - isr_table[vector].handler = handler; - isr_table[vector].param = param; - } - /* set the interrupt to this cpu */ - arm_gic_set_cpu(0, vector, 1 << rt_cpu_get_smp_id()); - } - - return old_handler; -} - -void rt_hw_interrupt_trigger(int vector) -{ - arm_gic_trigger(0, 1 << rt_cpu_get_smp_id(), vector); -} - -void rt_hw_interrupt_clear(int vector) -{ - /* SGI will be cleared automatically. */ -} diff --git a/rt-thread/libcpu/arm/zynqmp-r5/interrupt.h b/rt-thread/libcpu/arm/zynqmp-r5/interrupt.h deleted file mode 100644 index 35490a0..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/interrupt.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-03-19 WangHuachen first version - */ - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#include -#include - -void rt_hw_interrupt_init(void); -void rt_hw_interrupt_mask(int vector); -void rt_hw_interrupt_umask(int vector); -int rt_hw_interrupt_get_irq(void); -void rt_hw_interrupt_trigger(int vector); -void rt_hw_interrupt_clear(int vector); -void rt_hw_interrupt_ack(int vector); - -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name); - -#endif diff --git a/rt-thread/libcpu/arm/zynqmp-r5/mpu.c b/rt-thread/libcpu/arm/zynqmp-r5/mpu.c deleted file mode 100644 index fc2ae7d..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/mpu.c +++ /dev/null @@ -1,288 +0,0 @@ -/****************************************************************************** -* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved. -* SPDX-License-Identifier: MIT -******************************************************************************/ - -/*****************************************************************************/ -/** -* @file mpu.c -* -* This file contains initial configuration of the MPU. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00  pkp  02/20/14 First release
-* 5.04  pkp  12/18/15 Updated MPU initialization as per the proper address map
-* 6.00  pkp  06/27/16 moving the Init_MPU code to .boot section since it is a
-*                     part of processor boot process
-* 6.2   mus  01/27/17 Updated to support IAR compiler
-* 7.1   mus  09/11/19 Added warning message if DDR size is not in power of 2.
-*                     Fix for CR#1038577.
-* 7.2   asa  04/08/20 Fix warning in the function Init_MPU.
-*
-* -* @note -* -* None. -* -******************************************************************************/ -/***************************** Include Files *********************************/ -#include -#include "zynqmp-r5.h" -#include "xreg_cortexr5.h" -#include "xpseudo_asm_gcc.h" - -/***************** Macros (Inline Functions) Definitions *********************/ - -/**************************** Type Definitions *******************************/ -typedef rt_int32_t s32; -typedef rt_uint64_t u64; -typedef rt_uint32_t u32; -/************************** Constant Definitions *****************************/ - -/************************** Variable Definitions *****************************/ - -static const struct { - u64 size; - unsigned int encoding; -}region_size[] = { - { 0x20, REGION_32B }, - { 0x40, REGION_64B }, - { 0x80, REGION_128B }, - { 0x100, REGION_256B }, - { 0x200, REGION_512B }, - { 0x400, REGION_1K }, - { 0x800, REGION_2K }, - { 0x1000, REGION_4K }, - { 0x2000, REGION_8K }, - { 0x4000, REGION_16K }, - { 0x8000, REGION_32K }, - { 0x10000, REGION_64K }, - { 0x20000, REGION_128K }, - { 0x40000, REGION_256K }, - { 0x80000, REGION_512K }, - { 0x100000, REGION_1M }, - { 0x200000, REGION_2M }, - { 0x400000, REGION_4M }, - { 0x800000, REGION_8M }, - { 0x1000000, REGION_16M }, - { 0x2000000, REGION_32M }, - { 0x4000000, REGION_64M }, - { 0x8000000, REGION_128M }, - { 0x10000000, REGION_256M }, - { 0x20000000, REGION_512M }, - { 0x40000000, REGION_1G }, - { 0x80000000, REGION_2G }, - { 0x100000000, REGION_4G }, -}; - -/************************** Function Prototypes ******************************/ -#if defined (__GNUC__) -void Init_MPU(void) __attribute__((__section__(".boot"))); -static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) __attribute__((__section__(".boot"))); -static void Xil_DisableMPURegions(void) __attribute__((__section__(".boot"))); -#elif defined (__ICCARM__) -#pragma default_function_attributes = @ ".boot" -void Init_MPU(void); -static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib); -static void Xil_DisableMPURegions(void); -#endif -/***************************************************************************** -* -* Initialize MPU for a given address map and Enabled the background Region in -* MPU with default memory attributes for rest of address range for Cortex R5 -* processor. -* -* @param None. -* -* @return None. -* -* -******************************************************************************/ - -void Init_MPU(void) -{ - u32 Addr; - u32 RegSize = 0U; - u32 Attrib; - u32 RegNum = 0, i, Offset = 0; - u64 size; - - Xil_DisableMPURegions(); - - Addr = 0x00000000U; -#ifdef XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR - /* If the DDR is present, configure region as per DDR size */ - size = (XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR - XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR) + 1; - if (size < 0x80000000) { - /* Lookup the size. */ - for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) { - if (size <= region_size[i].size) { - RegSize = region_size[i].encoding; - - /* Check if DDR size is in power of 2*/ - if ( XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR == 0x100000) - Offset = XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR; - if (region_size[i].size > (size + Offset + 1)) { - rt_kprintf ("WARNING: DDR size mapped to Cortexr5 processor is not \ - in power of 2. As processor allocates MPU regions size \ - in power of 2, address range %llx to %x has been \ - incorrectly mapped as normal memory \n", \ - region_size[i].size - 1, ((u32)XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR + 1)); - } - break; - } - } - } else { - /* if the DDR size is > 2GB, truncate it to 2GB */ - RegSize = REGION_2G; - } -#else - /* For DDRless system, configure region for TCM */ - RegSize = REGION_256K; -#endif - Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; - - /* - * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL. - * 512 MB - LPD-PL interface - * 256 MB - FPD-PL (HPM0) interface - * 256 MB - FPD-PL (HPM1) interface - */ - Addr = 0x80000000; - RegSize = REGION_1G; - Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; - - /* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */ - Addr = 0xC0000000U; - RegSize = REGION_512M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; - - /* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */ - Addr = 0xE0000000U; - RegSize = REGION_256M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; - - /* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */ - Addr = 0xF8000000U; - RegSize = REGION_16M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; - - /* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */ - Addr = 0xF9000000U; - RegSize = REGION_1M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; - - /* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */ - Addr = 0xFD000000U; - RegSize = REGION_16M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; - - /* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */ - Addr = 0xFE000000U; - RegSize = REGION_16M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; - - /* - * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves, - * CSU, PMU, TCM, OCM - */ - Addr = 0xFF000000U; - RegSize = REGION_16M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; - - /* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */ - Addr = 0xFFFC0000U; - RegSize = REGION_256K; - Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - - /* A total of 10 MPU regions are allocated with another 6 being free for users */ - -} - -/***************************************************************************** -* -* Set the memory attributes for a section of memory with starting address addr -* of the region size defined by reg_size having attributes attrib of region number -* reg_num -* -* @param addr is the address for which attributes are to be set. -* @param attrib specifies the attributes for that memory region. -* @param reg_size specifies the size for that memory region. -* @param reg_num specifies the number for that memory region. -* @return None. -* -* -******************************************************************************/ -static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) -{ - u32 Local_reg_size = reg_size; - - Local_reg_size = Local_reg_size<<1U; - Local_reg_size |= REGION_EN; - dsb(); - mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num); - isb(); - mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */ - mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */ - mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size); /* set the region size and enable it*/ - dsb(); - isb(); /* synchronize context on this processor */ -} - - -/***************************************************************************** -* -* Disable all the MPU regions if any of them is enabled -* -* @param None. -* -* @return None. -* -* -******************************************************************************/ -static void Xil_DisableMPURegions(void) -{ - u32 Temp = 0U; - u32 Index = 0U; - for (Index = 0; Index <= 15; Index++) { - mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index); -#if defined (__GNUC__) - Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); -#endif - Temp &= (~REGION_EN); - dsb(); - mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); - dsb(); - isb(); - } - -} - -#if defined (__ICCARM__) -#pragma default_function_attributes = -#endif diff --git a/rt-thread/libcpu/arm/zynqmp-r5/stack.c b/rt-thread/libcpu/arm/zynqmp-r5/stack.c deleted file mode 100644 index 20a6e23..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/stack.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-09-23 Bernard the first version - * 2011-10-05 Bernard add thumb mode - * 2020-11-24 WangHuachen porting to zynqmp-r5 - */ -#include -#include "armv7.h" - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - - stack_addr += sizeof(rt_uint32_t); - stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); - stk = (rt_uint32_t *)stack_addr; - *(--stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0xdeadbeef; /* r12 */ - *(--stk) = 0xdeadbeef; /* r11 */ - *(--stk) = 0xdeadbeef; /* r10 */ - *(--stk) = 0xdeadbeef; /* r9 */ - *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = 0xdeadbeef; /* r4 */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = 0xdeadbeef; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - { - int i; - for (i = 0; i < VFP_DATA_NR; i++) - { - *(--stk) = 0; - } - /* FPSCR TODO: do we need to set the values other than 0? */ - *(--stk) = 0; - /* FPEXC. Enable the FVP if no lazy stacking. */ - *(--stk) = 0x40000000; - } -#endif - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - diff --git a/rt-thread/libcpu/arm/zynqmp-r5/start_gcc.S b/rt-thread/libcpu/arm/zynqmp-r5/start_gcc.S deleted file mode 100644 index 6d892c6..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/start_gcc.S +++ /dev/null @@ -1,428 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-03-19 WangHuachen first version - * 2021-05-11 WangHuachen Added call to Xil_InitializeExistingMPURegConfig to - * initialize the MPU configuration table with the MPU - * configurations already set in Init_Mpu function. - */ - -.equ Mode_USR, 0x10 -.equ Mode_FIQ, 0x11 -.equ Mode_IRQ, 0x12 -.equ Mode_SVC, 0x13 -.equ Mode_ABT, 0x17 -.equ Mode_UND, 0x1B -.equ Mode_SYS, 0x1F - -.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled -.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled - -.equ UND_Stack_Size, 0x00000000 -.equ SVC_Stack_Size, 0x00000000 -.equ ABT_Stack_Size, 0x00000000 -.equ FIQ_Stack_Size, 0x00000200 -.equ IRQ_Stack_Size, 0x00000200 -.equ USR_Stack_Size, 0x00000000 - -.set RPU_GLBL_CNTL, 0xFF9A0000 -.set RPU_ERR_INJ, 0xFF9A0020 -.set RPU_0_CFG, 0xFF9A0100 -.set RPU_1_CFG, 0xFF9A0200 -.set RST_LPD_DBG, 0xFF5E0240 -.set BOOT_MODE_USER, 0xFF5E0200 -.set fault_log_enable, 0x101 - -#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - -.section .data.share.isr -/* stack */ -.globl stack_start -.globl stack_top - -.align 3 -.bss -stack_start: -.rept ISR_Stack_Size -.long 0 -.endr -stack_top: - -.section .boot,"axS" -/* reset entry */ -.globl _reset -_reset: - - /* Initialize processor registers to 0 */ - mov r0,#0 - mov r1,#0 - mov r2,#0 - mov r3,#0 - mov r4,#0 - mov r5,#0 - mov r6,#0 - mov r7,#0 - mov r8,#0 - mov r9,#0 - mov r10,#0 - mov r11,#0 - mov r12,#0 - - /* set the cpu to SVC32 mode and disable interrupt */ - cpsid if, #Mode_SVC - - /* setup stack */ - bl stack_setup - - /* - * Enable access to VFP by enabling access to Coprocessors 10 and 11. - * Enables Full Access i.e. in both privileged and non privileged modes - */ - mrc p15, 0, r0, c1, c0, 2 /* Read Coprocessor Access Control Register (CPACR) */ - orr r0, r0, #(0xF << 20) /* Enable access to CP 10 & 11 */ - mcr p15, 0, r0, c1, c0, 2 /* Write Coprocessor Access Control Register (CPACR) */ - isb - - /* enable fpu access */ - vmrs r3, FPEXC - orr r1, r3, #(1<<30) - vmsr FPEXC, r1 - - /* clear the floating point register*/ - mov r1,#0 - vmov d0,r1,r1 - vmov d1,r1,r1 - vmov d2,r1,r1 - vmov d3,r1,r1 - vmov d4,r1,r1 - vmov d5,r1,r1 - vmov d6,r1,r1 - vmov d7,r1,r1 - vmov d8,r1,r1 - vmov d9,r1,r1 - vmov d10,r1,r1 - vmov d11,r1,r1 - vmov d12,r1,r1 - vmov d13,r1,r1 - vmov d14,r1,r1 - vmov d15,r1,r1 - -#ifdef __SOFTFP__ -/* Disable the FPU if SOFTFP is defined*/ - vmsr FPEXC,r3 -#endif - - /* Disable MPU and caches */ - mrc p15, 0, r0, c1, c0, 0 /* Read CP15 Control Register*/ - bic r0, r0, #0x05 /* Disable MPU (M bit) and data cache (C bit) */ - bic r0, r0, #0x1000 /* Disable instruction cache (I bit) */ - dsb /* Ensure all previous loads/stores have completed */ - mcr p15, 0, r0, c1, c0, 0 /* Write CP15 Control Register */ - isb /* Ensure subsequent insts execute wrt new MPU settings */ - - /* Disable Branch prediction, TCM ECC checks */ - mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR */ - orr r0, r0, #(0x1 << 17) /* Enable RSDIS bit 17 to disable the return stack */ - orr r0, r0, #(0x1 << 16) /* Clear BP bit 15 and set BP bit 16:*/ - bic r0, r0, #(0x1 << 15) /* Branch always not taken and history table updates disabled*/ - orr r0, r0, #(0x1 << 27) /* Enable B1TCM ECC check */ - orr r0, r0, #(0x1 << 26) /* Enable B0TCM ECC check */ - orr r0, r0, #(0x1 << 25) /* Enable ATCM ECC check */ - bic r0, r0, #(0x1 << 5) /* Generate abort on parity errors, with [5:3]=b 000*/ - bic r0, r0, #(0x1 << 4) - bic r0, r0, #(0x1 << 3) - mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ - dsb /* Complete all outstanding explicit memory operations*/ - - /* Invalidate caches */ - mov r0,#0 /* r0 = 0 */ - dsb - mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ - mcr p15, 0, r0, c15, c5, 0 /* Invalidate entire data cache*/ - isb - - /* enable fault log for lock step */ - ldr r0,=RPU_GLBL_CNTL - ldr r1, [r0] - ands r1, r1, #0x8 - /* branch to initialization if split mode*/ - bne init - /* check for boot mode if in lock step, branch to init if JTAG boot mode*/ - ldr r0,=BOOT_MODE_USER - ldr r1, [r0] - ands r1, r1, #0xF - beq init - /* reset the debug logic */ - ldr r0,=RST_LPD_DBG - ldr r1, [r0] - orr r1, r1, #(0x1 << 4) - orr r1, r1, #(0x1 << 5) - str r1, [r0] - /* enable fault log */ - ldr r0,=RPU_ERR_INJ - ldr r1,=fault_log_enable - ldr r2, [r0] - orr r2, r2, r1 - str r2, [r0] - nop - nop - -init: - bl Init_MPU /* Initialize MPU */ - - /* Enable Branch prediction */ - mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/ - bic r0, r0, #(0x1 << 17) /* Clear RSDIS bit 17 to enable return stack*/ - bic r0, r0, #(0x1 << 16) /* Clear BP bit 15 and BP bit 16:*/ - bic r0, r0, #(0x1 << 15) /* Normal operation, BP is taken from the global history table.*/ - orr r0, r0, #(0x1 << 14) /* Disable DBWR for errata 780125 */ - mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ - - /* Enable icahce and dcache */ - mrc p15,0,r1,c1,c0,0 - ldr r0, =0x1005 - orr r1,r1,r0 - dsb - mcr p15,0,r1,c1,c0,0 /* Enable cache */ - isb /* isb flush prefetch buffer */ - - /* Set vector table in TCM/LOVEC */ - mrc p15, 0, r0, c1, c0, 0 - mvn r1, #0x2000 - and r0, r0, r1 - mcr p15, 0, r0, c1, c0, 0 - - /* Clear VINITHI to enable LOVEC on reset */ -#if 1 - ldr r0, =RPU_0_CFG -#else - ldr r0, =RPU_1_CFG -#endif - ldr r1, [r0] - bic r1, r1, #(0x1 << 2) - str r1, [r0] - - /* enable asynchronous abort exception */ - mrs r0, cpsr - bic r0, r0, #0x100 - msr cpsr_xsf, r0 - - /* clear .bss */ - mov r0,#0 /* get a zero */ - ldr r1,=__bss_start /* bss start */ - ldr r2,=__bss_end /* bss end */ - -bss_loop: - cmp r1,r2 /* check if data to clear */ - strlo r0,[r1],#4 /* clear 4 bytes */ - blo bss_loop /* loop until done */ - - /* call C++ constructors of global objects */ - ldr r0, =__ctors_start__ - ldr r1, =__ctors_end__ - -ctor_loop: - cmp r0, r1 - beq ctor_end - ldr r2, [r0], #4 - stmfd sp!, {r0-r1} - mov lr, pc - bx r2 - ldmfd sp!, {r0-r1} - b ctor_loop -ctor_end: - - bl Xil_InitializeExistingMPURegConfig /* Initialize MPU config */ - /* start RT-Thread Kernel */ - ldr pc, _entry - -_entry: - .word entry - -stack_setup: - ldr r0, =stack_top - - @ Set the startup stack for svc - mov sp, r0 - - @ Enter Undefined Instruction Mode and set its Stack Pointer - msr cpsr_c, #Mode_UND|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #UND_Stack_Size - - @ Enter Abort Mode and set its Stack Pointer - msr cpsr_c, #Mode_ABT|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #ABT_Stack_Size - - @ Enter FIQ Mode and set its Stack Pointer - msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #FIQ_Stack_Size - - @ Enter IRQ Mode and set its Stack Pointer - msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #IRQ_Stack_Size - - @ Switch back to SVC - msr cpsr_c, #Mode_SVC|I_Bit|F_Bit - - bx lr - -.section .text.isr, "ax" -/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */ - .align 5 -.globl vector_fiq -vector_fiq: - stmfd sp!,{r0-r7,lr} - bl rt_hw_trap_fiq - ldmfd sp!,{r0-r7,lr} - subs pc,lr,#4 - -.globl rt_interrupt_enter -.globl rt_interrupt_leave -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread - - .align 5 -.globl vector_irq -vector_irq: - stmfd sp!, {r0-r12,lr} -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - vstmdb sp!, {d0-d15} /* Store floating point registers */ - vmrs r1, FPSCR - stmfd sp!,{r1} - vmrs r1, FPEXC - stmfd sp!,{r1} -#endif - - bl rt_interrupt_enter - bl rt_hw_trap_irq - bl rt_interrupt_leave - - @ if rt_thread_switch_interrupt_flag set, jump to - @ rt_hw_context_switch_interrupt_do and don't return - ldr r0, =rt_thread_switch_interrupt_flag - ldr r1, [r0] - cmp r1, #1 - beq rt_hw_context_switch_interrupt_do - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - ldmfd sp!, {r1} /* Restore floating point registers */ - vmsr FPEXC, r1 - ldmfd sp!, {r1} - vmsr FPSCR, r1 - vldmia sp!, {d0-d15} -#endif - ldmfd sp!, {r0-r12,lr} - subs pc, lr, #4 - -rt_hw_context_switch_interrupt_do: - mov r1, #0 @ clear flag - str r1, [r0] - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - ldmfd sp!, {r1} /* Restore floating point registers */ - vmsr FPEXC, r1 - ldmfd sp!, {r1} - vmsr FPSCR, r1 - vldmia sp!, {d0-d15} -#endif - - mov r1, sp @ r1 point to {r0-r3} in stack - add sp, sp, #4*4 - ldmfd sp!, {r4-r12,lr}@ reload saved registers - mrs r0, spsr @ get cpsr of interrupt thread - sub r2, lr, #4 @ save old task's pc to r2 - - @ Switch to SVC mode with no interrupt. - msr cpsr_c, #I_Bit|F_Bit|Mode_SVC - - stmfd sp!, {r2} @ push old task's pc - stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4 - ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread - stmfd sp!, {r1-r4} @ push old task's r0-r3 - stmfd sp!, {r0} @ push old task's cpsr - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - vstmdb sp!, {d0-d15} /* Store floating point registers */ - vmrs r1, FPSCR - stmfd sp!,{r1} - vmrs r1, FPEXC - stmfd sp!,{r1} -#endif - - ldr r4, =rt_interrupt_from_thread - ldr r5, [r4] - str sp, [r5] @ store sp in preempted tasks's TCB - - ldr r6, =rt_interrupt_to_thread - ldr r7, [r6] - ldr sp, [r7] @ get new task's stack pointer - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - ldmfd sp!, {r1} /* Restore floating point registers */ - vmsr FPEXC, r1 - ldmfd sp!, {r1} - vmsr FPSCR, r1 - vldmia sp!, {d0-d15} -#endif - - ldmfd sp!, {r4} @ pop new task's cpsr to spsr - msr spsr_cxsf, r4 - - ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr - -.macro push_svc_reg - sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ - stmia sp, {r0 - r12} @/* Calling r0-r12 */ - mov r0, sp - mrs r6, spsr @/* Save CPSR */ - str lr, [r0, #15*4] @/* Push PC */ - str r6, [r0, #16*4] @/* Push CPSR */ - cps #Mode_SVC - str sp, [r0, #13*4] @/* Save calling SP */ - str lr, [r0, #14*4] @/* Save calling PC */ -.endm - - .align 5 - .globl vector_swi -vector_swi: - push_svc_reg - bl rt_hw_trap_swi - b . - - .align 5 - .globl vector_undef -vector_undef: - push_svc_reg - bl rt_hw_trap_undef - b . - - .align 5 - .globl vector_pabt -vector_pabt: - push_svc_reg - bl rt_hw_trap_pabt - b . - - .align 5 - .globl vector_dabt -vector_dabt: - push_svc_reg - bl rt_hw_trap_dabt - b . - - .align 5 - .globl vector_resv -vector_resv: - push_svc_reg - bl rt_hw_trap_resv - b . diff --git a/rt-thread/libcpu/arm/zynqmp-r5/trap.c b/rt-thread/libcpu/arm/zynqmp-r5/trap.c deleted file mode 100644 index 5db5a0c..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/trap.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - * 2020-11-24 WangHuachen porting to zynqmp-r5 - */ - -#include -#include -#include - -#include "armv7.h" -#include "interrupt.h" - -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) -extern long list_thread(void); -#endif - -/** - * this function will show registers of CPU - * - * @param regs the registers point - */ -void rt_hw_show_register (struct rt_hw_exp_stack *regs) -{ - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); -} - -/** - * When comes across an instruction which it cannot handle, - * it takes the undefined instruction trap. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("undefined instruction:\n"); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * The software interrupt instruction (SWI) is used for entering - * Supervisor mode, usually to request a particular supervisor - * function. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_swi(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("software interrupt:\n"); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during an instruction prefetch. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("prefetch abort:\n"); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during a data access. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("data abort:"); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * Normally, system will never reach here - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("reserved trap:\n"); - rt_hw_show_register(regs); -#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -void rt_hw_trap_irq(void) -{ - void *param; - int ir; - rt_isr_handler_t isr_func; - extern struct rt_irq_desc isr_table[]; - - ir = rt_hw_interrupt_get_irq(); - - if (ir == 1023) - { - /* Spurious interrupt */ - return; - } - - /* get interrupt service routine */ - isr_func = isr_table[ir].handler; -#ifdef RT_USING_INTERRUPT_INFO - isr_table[ir].counter++; -#endif - if (isr_func) - { - /* Interrupt for myself. */ - param = isr_table[ir].param; - /* turn to interrupt service routine */ - isr_func(ir, param); - } - - /* end of interrupt */ - rt_hw_interrupt_ack(ir); -} - -void rt_hw_trap_fiq(void) -{ - void *param; - int ir; - rt_isr_handler_t isr_func; - extern struct rt_irq_desc isr_table[]; - - ir = rt_hw_interrupt_get_irq(); - - /* get interrupt service routine */ - isr_func = isr_table[ir].handler; - param = isr_table[ir].param; - - /* turn to interrupt service routine */ - isr_func(ir, param); - - /* end of interrupt */ - rt_hw_interrupt_ack(ir); -} - diff --git a/rt-thread/libcpu/arm/zynqmp-r5/vector_gcc.S b/rt-thread/libcpu/arm/zynqmp-r5/vector_gcc.S deleted file mode 100644 index 9c30f62..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/vector_gcc.S +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - */ - -.section .vectors, "ax" -.code 32 - -.globl system_vectors -system_vectors: - ldr pc, _vector_reset - ldr pc, _vector_undef - ldr pc, _vector_swi - ldr pc, _vector_pabt - ldr pc, _vector_dabt - ldr pc, _vector_resv - ldr pc, _vector_irq - ldr pc, _vector_fiq - -.globl _reset -.globl vector_undef -.globl vector_swi -.globl vector_pabt -.globl vector_dabt -.globl vector_resv -.globl vector_irq -.globl vector_fiq - -_vector_reset: - .word _reset -_vector_undef: - .word vector_undef -_vector_swi: - .word vector_swi -_vector_pabt: - .word vector_pabt -_vector_dabt: - .word vector_dabt -_vector_resv: - .word vector_resv -_vector_irq: - .word vector_irq -_vector_fiq: - .word vector_fiq - -.balignl 16,0xdeadbeef diff --git a/rt-thread/libcpu/arm/zynqmp-r5/xil_mmu.h b/rt-thread/libcpu/arm/zynqmp-r5/xil_mmu.h deleted file mode 100644 index 99e019c..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/xil_mmu.h +++ /dev/null @@ -1,54 +0,0 @@ -/****************************************************************************** -* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved. -* SPDX-License-Identifier: MIT -******************************************************************************/ - -/*****************************************************************************/ -/** -* @file xil_mmu.h -* This file only includes xil_mpu.h which contains Xil_SetTlbAttributes API -* defined for MPU in R5. R5 does not have mmu and for usage of similar API -* the file has been created. -* -* -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.0    pkp  2/12/15 Initial version
-*
-* -* @note -* -* None. -* -******************************************************************************/ - -#ifndef XIL_MMU_H -#define XIL_MMU_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/***************************** Include Files *********************************/ - -#include "xil_mpu.h" - -/***************** Macros (Inline Functions) Definitions *********************/ - -/**************************** Type Definitions *******************************/ - -/************************** Constant Definitions *****************************/ - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* XIL_MMU_H */ diff --git a/rt-thread/libcpu/arm/zynqmp-r5/xil_mpu.c b/rt-thread/libcpu/arm/zynqmp-r5/xil_mpu.c deleted file mode 100644 index 9ab94a4..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/xil_mpu.c +++ /dev/null @@ -1,637 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. -* Copyright (C) 2021 WangHuachen. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -* THE SOFTWARE. -* -* -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xil_mpu.c -* -* This file provides APIs for enabling/disabling MPU and setting the memory -* attributes for sections, in the MPU translation table. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00  pkp  02/10/14 Initial version
-* 6.2   mus  01/27/17 Updated to support IAR compiler
-* 6.4   asa  08/16/17 Added many APIs for MPU access to make MPU usage
-*                       user-friendly. The APIs added are: Xil_UpdateMPUConfig,
-*                       Xil_GetMPUConfig, Xil_GetNumOfFreeRegions,
-*                       Xil_GetNextMPURegion, Xil_DisableMPURegionByRegNum,
-*                       Xil_GetMPUFreeRegMask, Xil_SetMPURegionByRegNum, and
-*                       Xil_InitializeExistingMPURegConfig.
-*                       Added a new array of structure of type XMpuConfig to
-*                       represent the MPU configuration table.
-* 6.8  aru  07/02/18 Returned the pointer instead of address
-*            of that pointer in Xil_MemMap().
-*
-* -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xil_cache.h" -#include "xpseudo_asm_gcc.h" -#include "xil_types.h" -#include "xil_mpu.h" -// #include "xdebug.h" -#include "xreg_cortexr5.h" -#include "xstatus.h" - -#include -#define DBG_TAG "xil_mpu" -#define DBG_LVL DBG_INFO -#include - -extern void Xil_DCacheFlush(void); -extern void Xil_ICacheInvalidate(void); -extern void Xil_DCacheDisable(void); -extern void Xil_ICacheDisable(void); -extern void Xil_DCacheEnable(void); -extern void Xil_ICacheEnable(void); - -/***************** Macros (Inline Functions) Definitions *********************/ - -/**************************** Type Definitions *******************************/ - -/************************** Constant Definitions *****************************/ -#define MPU_REGION_SIZE_MIN 0x20 -/************************** Variable Definitions *****************************/ - -static const struct { - u64 size; - unsigned int encoding; -}region_size[] = { - { 0x20, REGION_32B }, - { 0x40, REGION_64B }, - { 0x80, REGION_128B }, - { 0x100, REGION_256B }, - { 0x200, REGION_512B }, - { 0x400, REGION_1K }, - { 0x800, REGION_2K }, - { 0x1000, REGION_4K }, - { 0x2000, REGION_8K }, - { 0x4000, REGION_16K }, - { 0x8000, REGION_32K }, - { 0x10000, REGION_64K }, - { 0x20000, REGION_128K }, - { 0x40000, REGION_256K }, - { 0x80000, REGION_512K }, - { 0x100000, REGION_1M }, - { 0x200000, REGION_2M }, - { 0x400000, REGION_4M }, - { 0x800000, REGION_8M }, - { 0x1000000, REGION_16M }, - { 0x2000000, REGION_32M }, - { 0x4000000, REGION_64M }, - { 0x8000000, REGION_128M }, - { 0x10000000, REGION_256M }, - { 0x20000000, REGION_512M }, - { 0x40000000, REGION_1G }, - { 0x80000000, REGION_2G }, - { 0x100000000, REGION_4G }, -}; - -XMpu_Config Mpu_Config; - -/************************** Function Prototypes ******************************/ -void Xil_InitializeExistingMPURegConfig(void); -/*****************************************************************************/ -/** -* @brief This function sets the memory attributes for a section covering -* 1MB, of memory in the translation table. -* -* @param Addr: 32-bit address for which memory attributes need to be set. -* @param attrib: Attribute for the given memory region. -* @return None. -* -* -******************************************************************************/ -void Xil_SetTlbAttributes(INTPTR addr, u32 attrib) -{ - INTPTR Localaddr = addr; - Localaddr &= (~(0xFFFFFU)); - /* Setting the MPU region with given attribute with 1MB size */ - Xil_SetMPURegion(Localaddr, 0x100000, attrib); -} - -/*****************************************************************************/ -/** -* @brief Set the memory attributes for a section of memory in the -* translation table. -* -* @param Addr: 32-bit address for which memory attributes need to be set.. -* @param size: size is the size of the region. -* @param attrib: Attribute for the given memory region. -* @return None. -* -* -******************************************************************************/ -u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib) -{ - u32 Regionsize = 0; - INTPTR Localaddr = addr; - u32 NextAvailableMemRegion; - unsigned int i; - - NextAvailableMemRegion = Xil_GetNextMPURegion(); - if (NextAvailableMemRegion == 0xFF) { - LOG_E("No regions available\r\n"); - return XST_FAILURE; - } - - Xil_DCacheFlush(); - Xil_ICacheInvalidate(); - - mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,NextAvailableMemRegion); - isb(); - - /* Lookup the size. */ - for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) { - if (size <= region_size[i].size) { - Regionsize = region_size[i].encoding; - break; - } - } - - Localaddr &= ~(region_size[i].size - 1); - - Regionsize <<= 1; - Regionsize |= REGION_EN; - dsb(); - mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr); /* Set base address of a region */ - mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib); /* Set the control attribute */ - mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize); /* set the region size and enable it*/ - dsb(); - isb(); - Xil_UpdateMPUConfig(NextAvailableMemRegion, Localaddr, Regionsize, attrib); - return XST_SUCCESS; -} -/*****************************************************************************/ -/** -* @brief Enable MPU for Cortex R5 processor. This function invalidates I -* cache and flush the D Caches, and then enables the MPU. -* -* -* @param None. -* @return None. -* -******************************************************************************/ -void Xil_EnableMPU(void) -{ - u32 CtrlReg, Reg; - s32 DCacheStatus=0, ICacheStatus=0; - /* enable caches only if they are disabled */ -#if defined (__GNUC__) - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); -#endif - if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { - DCacheStatus=1; - } - if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { - ICacheStatus=1; - } - - if(DCacheStatus != 0) { - Xil_DCacheDisable(); - } - if(ICacheStatus != 0){ - Xil_ICacheDisable(); - } -#if defined (__GNUC__) - Reg = mfcp(XREG_CP15_SYS_CONTROL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL,Reg); -#endif - Reg |= 0x00000001U; - dsb(); - mtcp(XREG_CP15_SYS_CONTROL, Reg); - isb(); - /* enable caches only if they are disabled in routine*/ - if(DCacheStatus != 0) { - Xil_DCacheEnable(); - } - if(ICacheStatus != 0) { - Xil_ICacheEnable(); - } -} - -/*****************************************************************************/ -/** -* @brief Disable MPU for Cortex R5 processors. This function invalidates I -* cache and flush the D Caches, and then disabes the MPU. -* -* @param None. -* -* @return None. -* -******************************************************************************/ -void Xil_DisableMPU(void) -{ - u32 CtrlReg, Reg; - s32 DCacheStatus=0, ICacheStatus=0; - /* enable caches only if they are disabled */ - -#if defined (__GNUC__) - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); -#endif - if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { - DCacheStatus=1; - } - if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { - ICacheStatus=1; - } - - if(DCacheStatus != 0) { - Xil_DCacheDisable(); - } - if(ICacheStatus != 0){ - Xil_ICacheDisable(); - } - - mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0); -#if defined (__GNUC__) - Reg = mfcp(XREG_CP15_SYS_CONTROL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL,Reg); -#endif - Reg &= ~(0x00000001U); - dsb(); - mtcp(XREG_CP15_SYS_CONTROL, Reg); - isb(); - /* enable caches only if they are disabled in routine*/ - if(DCacheStatus != 0) { - Xil_DCacheEnable(); - } - if(ICacheStatus != 0) { - Xil_ICacheEnable(); - } -} - -/*****************************************************************************/ -/** -* @brief Update the MPU configuration for the requested region number in -* the global MPU configuration table. -* -* @param reg_num: The requested region number to be updated information for. -* @param address: 32 bit address for start of the region. -* @param size: Requested size of the region. -* @param attrib: Attribute for the corresponding region. -* @return XST_FAILURE: When the requested region number if 16 or more. -* XST_SUCCESS: When the MPU configuration table is updated. -* -* -******************************************************************************/ -u32 Xil_UpdateMPUConfig(u32 reg_num, INTPTR address, u32 size, u32 attrib) -{ - u32 ReturnVal = XST_SUCCESS; - u32 Tempsize = size; - u32 Index; - - if (reg_num >= MAX_POSSIBLE_MPU_REGS) { - LOG_E("Invalid region number\r\n"); - ReturnVal = XST_FAILURE; - goto exit; - } - - if (size & REGION_EN) { - Mpu_Config[reg_num].RegionStatus = MPU_REG_ENABLED; - Mpu_Config[reg_num].BaseAddress = address; - Tempsize &= (~REGION_EN); - Tempsize >>= 1; - /* Lookup the size. */ - for (Index = 0; Index < - sizeof region_size / sizeof region_size[0]; Index++) { - if (Tempsize <= region_size[Index].encoding) { - Mpu_Config[reg_num].Size = region_size[Index].size; - break; - } - } - Mpu_Config[reg_num].Attribute = attrib; - } else { - Mpu_Config[reg_num].RegionStatus = 0U; - Mpu_Config[reg_num].BaseAddress = 0U; - Mpu_Config[reg_num].Size = 0U; - Mpu_Config[reg_num].Attribute = 0U; - } - -exit: - return ReturnVal; -} - -/*****************************************************************************/ -/** -* @brief The MPU configuration table is passed to the caller. -* -* @param mpuconfig: This is of type XMpu_Config which is an array of -* 16 entries of type structure representing the MPU config table -* @return none -* -* -******************************************************************************/ -void Xil_GetMPUConfig (XMpu_Config mpuconfig) { - u32 Index = 0U; - - while (Index < MAX_POSSIBLE_MPU_REGS) { - mpuconfig[Index].RegionStatus = Mpu_Config[Index].RegionStatus; - mpuconfig[Index].BaseAddress = Mpu_Config[Index].BaseAddress; - mpuconfig[Index].Attribute = Mpu_Config[Index].Attribute; - mpuconfig[Index].Size = Mpu_Config[Index].Size; - Index++; - } -} - -/*****************************************************************************/ -/** -* @brief Returns the total number of free MPU regions available. -* -* @param none -* @return Number of free regions available to users -* -* -******************************************************************************/ -u32 Xil_GetNumOfFreeRegions (void) { - u32 Index = 0U; - int NumofFreeRegs = 0U; - - while (Index < MAX_POSSIBLE_MPU_REGS) { - if (MPU_REG_DISABLED == Mpu_Config[Index].RegionStatus) { - NumofFreeRegs++; - } - Index++; - } - return NumofFreeRegs; -} - -/*****************************************************************************/ -/** -* @brief Returns the total number of free MPU regions available in the form -* of a mask. A bit of 1 in the returned 16 bit value represents the -* corresponding region number to be available. -* For example, if this function returns 0xC0000, this would mean, the -* regions 14 and 15 are available to users. -* -* @param none -* @return The free region mask as a 16 bit value -* -* -******************************************************************************/ -u16 Xil_GetMPUFreeRegMask (void) { - u32 Index = 0U; - u16 FreeRegMask = 0U; - - while (Index < MAX_POSSIBLE_MPU_REGS) { - if (MPU_REG_DISABLED == Mpu_Config[Index].RegionStatus) { - FreeRegMask |= (1U << Index); - } - Index++; - } - return FreeRegMask; -} - -/*****************************************************************************/ -/** -* @brief Disables the corresponding region number as passed by the user. -* -* @param reg_num: The region number to be disabled -* @return XST_SUCCESS: If the region could be disabled successfully -* XST_FAILURE: If the requested region number is 16 or more. -* -* -******************************************************************************/ -u32 Xil_DisableMPURegionByRegNum (u32 reg_num) { - u32 Temp = 0U; - u32 ReturnVal = XST_FAILURE; - - if (reg_num >= 16U) { - LOG_E("Invalid region number\r\n"); - goto exit1; - } - Xil_DCacheFlush(); - Xil_ICacheInvalidate(); - - mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num); -#if defined (__GNUC__) - Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); -#endif - Temp &= (~REGION_EN); - dsb(); - mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); - dsb(); - isb(); - Xil_UpdateMPUConfig(reg_num, 0U, 0U, 0U); - ReturnVal = XST_SUCCESS; - -exit1: - return ReturnVal; -} - -/*****************************************************************************/ -/** -* @brief Enables the corresponding region number as passed by the user. -* -* @param reg_num: The region number to be enabled -* @param address: 32 bit address for start of the region. -* @param size: Requested size of the region. -* @param attrib: Attribute for the corresponding region. -* @return XST_SUCCESS: If the region could be created successfully -* XST_FAILURE: If the requested region number is 16 or more. -* -* -******************************************************************************/ -u32 Xil_SetMPURegionByRegNum (u32 reg_num, INTPTR addr, u64 size, u32 attrib) -{ - u32 ReturnVal = XST_SUCCESS; - INTPTR Localaddr = addr; - u32 Regionsize = 0; - u32 Index; - - if (reg_num >= 16U) { - LOG_E("Invalid region number\r\n"); - ReturnVal = XST_FAILURE; - goto exit2; - } - - if (Mpu_Config[reg_num].RegionStatus == MPU_REG_ENABLED) { - LOG_E("Region already enabled\r\n"); - ReturnVal = XST_FAILURE; - goto exit2; - } - - Xil_DCacheFlush(); - Xil_ICacheInvalidate(); - mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num); - isb(); - - /* Lookup the size. */ - for (Index = 0; Index < - sizeof region_size / sizeof region_size[0]; Index++) { - if (size <= region_size[Index].size) { - Regionsize = region_size[Index].encoding; - break; - } - } - - Localaddr &= ~(region_size[Index].size - 1); - Regionsize <<= 1; - Regionsize |= REGION_EN; - dsb(); - mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr); - mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib); - mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize); - dsb(); - isb(); - Xil_UpdateMPUConfig(reg_num, Localaddr, Regionsize, attrib); -exit2: - return ReturnVal; - -} - -/*****************************************************************************/ -/** -* @brief Initializes the MPU configuration table that are setup in the -* R5 boot code in the Init_Mpu function called before C main. -* -* @param none -* @return none -* -* -******************************************************************************/ -void Xil_InitializeExistingMPURegConfig(void) -{ - u32 Index = 0U; - u32 Index1 = 0U; - u32 MPURegSize; - INTPTR MPURegBA; - u32 MPURegAttrib; - u32 Tempsize; - - while (Index < MAX_POSSIBLE_MPU_REGS) { - mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index); -#if defined (__GNUC__) - MPURegSize = mfcp(XREG_CP15_MPU_REG_SIZE_EN); - MPURegBA = mfcp(XREG_CP15_MPU_REG_BASEADDR); - MPURegAttrib = mfcp(XREG_CP15_MPU_REG_ACCESS_CTRL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_MPU_REG_SIZE_EN,MPURegSize); - mfcp(XREG_CP15_MPU_REG_BASEADDR, MPURegBA); - mfcp(XREG_CP15_MPU_REG_ACCESS_CTRL, MPURegAttrib); -#endif - if (MPURegSize & REGION_EN) { - Mpu_Config[Index].RegionStatus = MPU_REG_ENABLED; - Mpu_Config[Index].BaseAddress = MPURegBA; - Mpu_Config[Index].Attribute = MPURegAttrib; - Tempsize = MPURegSize & (~REGION_EN); - Tempsize >>= 1; - for (Index1 = 0; Index1 < - (sizeof (region_size) / sizeof (region_size[0])); Index1++) { - if (Tempsize <= region_size[Index1].encoding) { - Mpu_Config[Index].Size = region_size[Index1].size; - break; - } - } - } - Index++; - } -} - -/*****************************************************************************/ -/** -* @brief Returns the next available free MPU region -* -* @param none -* @return The free MPU region available -* -* -******************************************************************************/ -u32 Xil_GetNextMPURegion(void) -{ - u32 Index = 0U; - u32 NextAvailableReg = 0xFF; - while (Index < MAX_POSSIBLE_MPU_REGS) { - if (Mpu_Config[Index].RegionStatus != MPU_REG_ENABLED) { - NextAvailableReg = Index; - break; - } - Index++; - } - return NextAvailableReg; -} - -/*****************************************************************************/ -/** -* @brief Memory mapping for Cortex r5. -* -* @param Physaddr is base physical address at which to start mapping. -* NULL in Physaddr masks possible mapping errors. -* @param size of region to be mapped. -* @param flags used to set translation table. -* -* @return Physaddr on success, NULL on error. Ambiguous if Physaddr==NULL -* -* @note: u32overflow() is defined for readability and (for __GNUC__) to -* - force the type of the check to be the same as the first argument -* - hide the otherwise unused third argument of the builtin -* - improve safety by choosing the explicit _uadd_ version. -* Consider __builtin_add_overflow_p() when available. -* Use an alternative (less optimal?) for compilers w/o the builtin. -* -******************************************************************************/ -#ifdef __GNUC__ -#define u32overflow(a, b) ({typeof(a) s; __builtin_uadd_overflow(a, b, &s); }) -#else -#define u32overflow(a, b) ((a) > ((a) + (b))) -#endif /* __GNUC__ */ -void *Xil_MemMap(UINTPTR Physaddr, size_t size, u32 flags) -{ - size_t Regionsize = MPU_REGION_SIZE_MIN; - UINTPTR Basephysaddr = 0, end = Physaddr + size; - - if (!flags) - return (void *)Physaddr; - if (u32overflow(Physaddr, size)) - return NULL; - for ( ; Regionsize != 0; Regionsize <<= 1) { - if (Regionsize >= size) { - Basephysaddr = Physaddr & ~(Regionsize - 1); - if (u32overflow(Basephysaddr, Regionsize)) - break; - if ((Basephysaddr + Regionsize) >= end) - return Xil_SetMPURegion(Basephysaddr, - Regionsize, flags) == XST_SUCCESS ? - (void *)Physaddr : NULL; - } - } - return NULL; -} diff --git a/rt-thread/libcpu/arm/zynqmp-r5/xil_mpu.h b/rt-thread/libcpu/arm/zynqmp-r5/xil_mpu.h deleted file mode 100644 index 1afa6f7..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/xil_mpu.h +++ /dev/null @@ -1,129 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -* THE SOFTWARE. -* -* -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xil_mmu.h -* -* @addtogroup r5_mpu_apis Cortex R5 Processor MPU specific APIs -* -* MPU functions provides access to MPU operations such as enable MPU, disable -* MPU and set attribute for section of memory. -* Boot code invokes Init_MPU function to configure the MPU. A total of 10 MPU -* regions are allocated with another 6 being free for users. Overview of the -* memory attributes for different MPU regions is as given below, -* -*| | Memory Range | Attributes of MPURegion | -*|-----------------------|-------------------------|-----------------------------| -*| DDR | 0x00000000 - 0x7FFFFFFF | Normal write-back Cacheable | -*| PL | 0x80000000 - 0xBFFFFFFF | Strongly Ordered | -*| QSPI | 0xC0000000 - 0xDFFFFFFF | Device Memory | -*| PCIe | 0xE0000000 - 0xEFFFFFFF | Device Memory | -*| STM_CORESIGHT | 0xF8000000 - 0xF8FFFFFF | Device Memory | -*| RPU_R5_GIC | 0xF9000000 - 0xF90FFFFF | Device memory | -*| FPS | 0xFD000000 - 0xFDFFFFFF | Device Memory | -*| LPS | 0xFE000000 - 0xFFFFFFFF | Device Memory | -*| OCM | 0xFFFC0000 - 0xFFFFFFFF | Normal write-back Cacheable | -* -* -* @note -* For a system where DDR is less than 2GB, region after DDR and before PL is -* marked as undefined in translation table. Memory range 0xFE000000-0xFEFFFFFF is -* allocated for upper LPS slaves, where as memory region 0xFF000000-0xFFFFFFFF is -* allocated for lower LPS slaves. -* -* @{ -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00  pkp  02/10/14 Initial version
-* 6.4   asa  08/16/17 Added many APIs for MPU access to make MPU usage
-*                       user-friendly. The APIs added are: Xil_UpdateMPUConfig,
-*                       Xil_GetMPUConfig, Xil_GetNumOfFreeRegions,
-*                       Xil_GetNextMPURegion, Xil_DisableMPURegionByRegNum,
-*                       Xil_GetMPUFreeRegMask, Xil_SetMPURegionByRegNum, and
-*                       Xil_InitializeExistingMPURegConfig.
-*                       Added a new array of structure of type XMpuConfig to
-*                       represent the MPU configuration table.
-*
-* - -* -* -******************************************************************************/ - -#ifndef XIL_MPU_H -#define XIL_MPU_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ -#include "xil_types.h" -/***************************** Include Files *********************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ -#define MPU_REG_DISABLED 0U -#define MPU_REG_ENABLED 1U -#define MAX_POSSIBLE_MPU_REGS 16U -/**************************** Type Definitions *******************************/ -struct XMpuConfig{ - u32 RegionStatus; /* Enabled or disabled */ - INTPTR BaseAddress;/* MPU region base address */ - u64 Size; /* MPU region size address */ - u32 Attribute; /* MPU region size attribute */ -}; - -typedef struct XMpuConfig XMpu_Config[MAX_POSSIBLE_MPU_REGS]; - -extern XMpu_Config Mpu_Config; -/************************** Constant Definitions *****************************/ - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib); -void Xil_EnableMPU(void); -void Xil_DisableMPU(void); -u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib); -u32 Xil_UpdateMPUConfig(u32 reg_num, INTPTR address, u32 size, u32 attrib); -void Xil_GetMPUConfig (XMpu_Config mpuconfig); -u32 Xil_GetNumOfFreeRegions (void); -u32 Xil_GetNextMPURegion(void); -u32 Xil_DisableMPURegionByRegNum (u32 reg_num); -u16 Xil_GetMPUFreeRegMask (void); -u32 Xil_SetMPURegionByRegNum (u32 reg_num, INTPTR addr, u64 size, u32 attrib); -void* Xil_MemMap(UINTPTR Physaddr, size_t size, u32 flags); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* XIL_MPU_H */ -/** -* @} End of "addtogroup r5_mpu_apis". -*/ diff --git a/rt-thread/libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h b/rt-thread/libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h deleted file mode 100644 index 7a65ef6..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h +++ /dev/null @@ -1,249 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -* THE SOFTWARE. -* -* -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xpseudo_asm_gcc.h -* -* This header file contains macros for using inline assembler code. It is -* written specifically for the GNU compiler. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00  pkp      05/21/14 First release
-* 6.0   mus      07/27/16 Consolidated file for a53,a9 and r5 processors
-*
-* -******************************************************************************/ - -#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */ -#define XPSEUDO_ASM_GCC_H /* by using protection macros */ - -/***************************** Include Files ********************************/ -#include - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/* necessary for pre-processor */ -#define stringify(s) tostring(s) -#define tostring(s) #s - -#if defined (__aarch64__) -/* pseudo assembler instructions */ -#define mfcpsr() ({rt_uint32_t rval = 0U; \ - asm volatile("mrs %0, DAIF" : "=r" (rval));\ - rval;\ - }) - -#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v)) - -#define cpsiei() //__asm__ __volatile__("cpsie i\n") -#define cpsidi() //__asm__ __volatile__("cpsid i\n") - -#define cpsief() //__asm__ __volatile__("cpsie f\n") -#define cpsidf() //__asm__ __volatile__("cpsid f\n") - - - -#define mtgpr(rn, v) /*__asm__ __volatile__(\ - "mov r" stringify(rn) ", %0 \n"\ - : : "r" (v)\ - )*/ - -#define mfgpr(rn) /*({rt_uint32_t rval; \ - __asm__ __volatile__(\ - "mov %0,r" stringify(rn) "\n"\ - : "=r" (rval)\ - );\ - rval;\ - })*/ - -/* memory synchronization operations */ - -/* Instruction Synchronization Barrier */ -#define isb() __asm__ __volatile__ ("isb sy") - -/* Data Synchronization Barrier */ -#define dsb() __asm__ __volatile__("dsb sy") - -/* Data Memory Barrier */ -#define dmb() __asm__ __volatile__("dmb sy") - - -/* Memory Operations */ -#define ldr(adr) ({u64 rval; \ - __asm__ __volatile__(\ - "ldr %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) - -#define mfelrel3() ({u64 rval = 0U; \ - asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\ - rval;\ - }) - -#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v)) - -#else - -/* pseudo assembler instructions */ -#define mfcpsr() ({rt_uint32_t rval = 0U; \ - __asm__ __volatile__(\ - "mrs %0, cpsr\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) - -#define mtcpsr(v) __asm__ __volatile__(\ - "msr cpsr,%0\n"\ - : : "r" (v)\ - ) - -#define cpsiei() __asm__ __volatile__("cpsie i\n") -#define cpsidi() __asm__ __volatile__("cpsid i\n") - -#define cpsief() __asm__ __volatile__("cpsie f\n") -#define cpsidf() __asm__ __volatile__("cpsid f\n") - - - -#define mtgpr(rn, v) __asm__ __volatile__(\ - "mov r" stringify(rn) ", %0 \n"\ - : : "r" (v)\ - ) - -#define mfgpr(rn) ({rt_uint32_t rval; \ - __asm__ __volatile__(\ - "mov %0,r" stringify(rn) "\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) - -/* memory synchronization operations */ - -/* Instruction Synchronization Barrier */ -#define isb() __asm__ __volatile__ ("isb" : : : "memory") - -/* Data Synchronization Barrier */ -#define dsb() __asm__ __volatile__ ("dsb" : : : "memory") - -/* Data Memory Barrier */ -#define dmb() __asm__ __volatile__ ("dmb" : : : "memory") - - -/* Memory Operations */ -#define ldr(adr) ({rt_uint32_t rval; \ - __asm__ __volatile__(\ - "ldr %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) - -#endif - -#define ldrb(adr) ({rt_uint8_t rval; \ - __asm__ __volatile__(\ - "ldrb %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) - -#define str(adr, val) __asm__ __volatile__(\ - "str %0,[%1]\n"\ - : : "r" (val), "r" (adr)\ - ) - -#define strb(adr, val) __asm__ __volatile__(\ - "strb %0,[%1]\n"\ - : : "r" (val), "r" (adr)\ - ) - -/* Count leading zeroes (clz) */ -#define clz(arg) ({rt_uint8_t rval; \ - __asm__ __volatile__(\ - "clz %0,%1"\ - : "=r" (rval) : "r" (arg)\ - );\ - rval;\ - }) - -#if defined (__aarch64__) -#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) -#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val)) - -#define mtcpicall(reg) __asm__ __volatile__("ic " #reg) -#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg) -#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) -/* CP15 operations */ -#define mfcp(reg) ({u64 rval = 0U;\ - __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ - rval;\ - }) - -#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) - -#else -/* CP15 operations */ -#define mtcp(rn, v) __asm__ __volatile__(\ - "mcr " rn "\n"\ - : : "r" (v)\ - ); - -#define mfcp(rn) ({rt_uint32_t rval = 0U; \ - __asm__ __volatile__(\ - "mrc " rn "\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) -#endif - -/************************** Variable Definitions ****************************/ - -/************************** Function Prototypes *****************************/ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* XPSEUDO_ASM_GCC_H */ diff --git a/rt-thread/libcpu/arm/zynqmp-r5/xreg_cortexr5.h b/rt-thread/libcpu/arm/zynqmp-r5/xreg_cortexr5.h deleted file mode 100644 index 9c0ae2b..0000000 --- a/rt-thread/libcpu/arm/zynqmp-r5/xreg_cortexr5.h +++ /dev/null @@ -1,419 +0,0 @@ -/****************************************************************************** -* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved. -* SPDX-License-Identifier: MIT -******************************************************************************/ - -/*****************************************************************************/ -/** -* -* @file xreg_cortexr5.h -* -* This header file contains definitions for using inline assembler code. It is -* written specifically for the GNU, IAR, ARMCC compiler. -* -* All of the ARM Cortex R5 GPRs, SPRs, and Debug Registers are defined along -* with the positions of the bits within the registers. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00  pkp  02/10/14 Initial version
-*
-* -******************************************************************************/ -#ifndef XREG_CORTEXR5_H /* prevent circular inclusions */ -#define XREG_CORTEXR5_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* GPRs */ -#define XREG_GPR0 r0 -#define XREG_GPR1 r1 -#define XREG_GPR2 r2 -#define XREG_GPR3 r3 -#define XREG_GPR4 r4 -#define XREG_GPR5 r5 -#define XREG_GPR6 r6 -#define XREG_GPR7 r7 -#define XREG_GPR8 r8 -#define XREG_GPR9 r9 -#define XREG_GPR10 r10 -#define XREG_GPR11 r11 -#define XREG_GPR12 r12 -#define XREG_GPR13 r13 -#define XREG_GPR14 r14 -#define XREG_GPR15 r15 -#define XREG_CPSR cpsr - -/* Coprocessor number defines */ -#define XREG_CP0 0 -#define XREG_CP1 1 -#define XREG_CP2 2 -#define XREG_CP3 3 -#define XREG_CP4 4 -#define XREG_CP5 5 -#define XREG_CP6 6 -#define XREG_CP7 7 -#define XREG_CP8 8 -#define XREG_CP9 9 -#define XREG_CP10 10 -#define XREG_CP11 11 -#define XREG_CP12 12 -#define XREG_CP13 13 -#define XREG_CP14 14 -#define XREG_CP15 15 - -/* Coprocessor control register defines */ -#define XREG_CR0 cr0 -#define XREG_CR1 cr1 -#define XREG_CR2 cr2 -#define XREG_CR3 cr3 -#define XREG_CR4 cr4 -#define XREG_CR5 cr5 -#define XREG_CR6 cr6 -#define XREG_CR7 cr7 -#define XREG_CR8 cr8 -#define XREG_CR9 cr9 -#define XREG_CR10 cr10 -#define XREG_CR11 cr11 -#define XREG_CR12 cr12 -#define XREG_CR13 cr13 -#define XREG_CR14 cr14 -#define XREG_CR15 cr15 - -/* Current Processor Status Register (CPSR) Bits */ -#define XREG_CPSR_THUMB_MODE 0x20U -#define XREG_CPSR_MODE_BITS 0x1FU -#define XREG_CPSR_SYSTEM_MODE 0x1FU -#define XREG_CPSR_UNDEFINED_MODE 0x1BU -#define XREG_CPSR_DATA_ABORT_MODE 0x17U -#define XREG_CPSR_SVC_MODE 0x13U -#define XREG_CPSR_IRQ_MODE 0x12U -#define XREG_CPSR_FIQ_MODE 0x11U -#define XREG_CPSR_USER_MODE 0x10U - -#define XREG_CPSR_IRQ_ENABLE 0x80U -#define XREG_CPSR_FIQ_ENABLE 0x40U - -#define XREG_CPSR_N_BIT 0x80000000U -#define XREG_CPSR_Z_BIT 0x40000000U -#define XREG_CPSR_C_BIT 0x20000000U -#define XREG_CPSR_V_BIT 0x10000000U - -/*MPU region definitions*/ -#define REGION_32B 0x00000004U -#define REGION_64B 0x00000005U -#define REGION_128B 0x00000006U -#define REGION_256B 0x00000007U -#define REGION_512B 0x00000008U -#define REGION_1K 0x00000009U -#define REGION_2K 0x0000000AU -#define REGION_4K 0x0000000BU -#define REGION_8K 0x0000000CU -#define REGION_16K 0x0000000DU -#define REGION_32K 0x0000000EU -#define REGION_64K 0x0000000FU -#define REGION_128K 0x00000010U -#define REGION_256K 0x00000011U -#define REGION_512K 0x00000012U -#define REGION_1M 0x00000013U -#define REGION_2M 0x00000014U -#define REGION_4M 0x00000015U -#define REGION_8M 0x00000016U -#define REGION_16M 0x00000017U -#define REGION_32M 0x00000018U -#define REGION_64M 0x00000019U -#define REGION_128M 0x0000001AU -#define REGION_256M 0x0000001BU -#define REGION_512M 0x0000001CU -#define REGION_1G 0x0000001DU -#define REGION_2G 0x0000001EU -#define REGION_4G 0x0000001FU - -#define REGION_EN 0x00000001U - - - -#define SHAREABLE 0x00000004U /*shareable */ -#define STRONG_ORDERD_SHARED 0x00000000U /*strongly ordered, always shareable*/ - -#define DEVICE_SHARED 0x00000001U /*device, shareable*/ -#define DEVICE_NONSHARED 0x00000010U /*device, non shareable*/ - -#define NORM_NSHARED_WT_NWA 0x00000002U /*Outer and Inner write-through, no write-allocate non-shareable*/ -#define NORM_SHARED_WT_NWA 0x00000006U /*Outer and Inner write-through, no write-allocate shareable*/ - -#define NORM_NSHARED_WB_NWA 0x00000003U /*Outer and Inner write-back, no write-allocate non shareable*/ -#define NORM_SHARED_WB_NWA 0x00000007U /*Outer and Inner write-back, no write-allocate shareable*/ - -#define NORM_NSHARED_NCACHE 0x00000008U /*Outer and Inner Non cacheable non shareable*/ -#define NORM_SHARED_NCACHE 0x0000000CU /*Outer and Inner Non cacheable shareable*/ - -#define NORM_NSHARED_WB_WA 0x0000000BU /*Outer and Inner write-back non shared*/ -#define NORM_SHARED_WB_WA 0x0000000FU /*Outer and Inner write-back shared*/ - -/* inner and outer cache policies can be combined for different combinations */ - -#define NORM_IN_POLICY_NCACHE 0x00000020U /*inner non cacheable*/ -#define NORM_IN_POLICY_WB_WA 0x00000021U /*inner write back write allocate*/ -#define NORM_IN_POLICY_WT_NWA 0x00000022U /*inner write through no write allocate*/ -#define NORM_IN_POLICY_WB_NWA 0x00000023U /*inner write back no write allocate*/ - -#define NORM_OUT_POLICY_NCACHE 0x00000020U /*outer non cacheable*/ -#define NORM_OUT_POLICY_WB_WA 0x00000028U /*outer write back write allocate*/ -#define NORM_OUT_POLICY_WT_NWA 0x00000030U /*outer write through no write allocate*/ -#define NORM_OUT_POLICY_WB_NWA 0x00000038U /*outer write back no write allocate*/ - -#define NO_ACCESS (0x00000000U<<8U) /*No access*/ -#define PRIV_RW_USER_NA (0x00000001U<<8U) /*Privileged access only*/ -#define PRIV_RW_USER_RO (0x00000002U<<8U) /*Writes in User mode generate permission faults*/ -#define PRIV_RW_USER_RW (0x00000003U<<8U) /*Full Access*/ -#define PRIV_RO_USER_NA (0x00000005U<<8U) /*Privileged eead only*/ -#define PRIV_RO_USER_RO (0x00000006U<<8U) /*Privileged/User read-only*/ - -#define EXECUTE_NEVER (0x00000001U<<12U) /* Bit 12*/ - - -/* CP15 defines */ - -/* C0 Register defines */ -#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" -#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" -#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" -#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" -#define XREG_CP15_MPU_TYPE "p15, 0, %0, c0, c0, 4" -#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" - -#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" -#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" -#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" -#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" -#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" -#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" -#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" - -#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" -#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" -#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" -#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" -#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" -#define XREG_CP15_INST_FEATURE_5 "p15, 0, %0, c0, c2, 5" - -#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" -#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" -#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" - -#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" - -/* C1 Register Defines */ -#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" -#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" -#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" - - -/* XREG_CP15_CONTROL bit defines */ -#define XREG_CP15_CONTROL_TE_BIT 0x40000000U -#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U -#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U -#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U -#define XREG_CP15_CONTROL_EE_BIT 0x02000000U -#define XREG_CP15_CONTROL_HA_BIT 0x00020000U -#define XREG_CP15_CONTROL_RR_BIT 0x00004000U -#define XREG_CP15_CONTROL_V_BIT 0x00002000U -#define XREG_CP15_CONTROL_I_BIT 0x00001000U -#define XREG_CP15_CONTROL_Z_BIT 0x00000800U -#define XREG_CP15_CONTROL_SW_BIT 0x00000400U -#define XREG_CP15_CONTROL_B_BIT 0x00000080U -#define XREG_CP15_CONTROL_C_BIT 0x00000004U -#define XREG_CP15_CONTROL_A_BIT 0x00000002U -#define XREG_CP15_CONTROL_M_BIT 0x00000001U -/* C2 Register Defines */ -/* Not Used */ - -/* C3 Register Defines */ -/* Not Used */ - -/* C4 Register Defines */ -/* Not Used */ - -/* C5 Register Defines */ -#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" -#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" - -#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" -#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" - -/* C6 Register Defines */ -#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" -#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" - -#define XREG_CP15_MPU_REG_BASEADDR "p15, 0, %0, c6, c1, 0" -#define XREG_CP15_MPU_REG_SIZE_EN "p15, 0, %0, c6, c1, 2" -#define XREG_CP15_MPU_REG_ACCESS_CTRL "p15, 0, %0, c6, c1, 4" - -#define XREG_CP15_MPU_MEMORY_REG_NUMBER "p15, 0, %0, c6, c2, 0" - -/* C7 Register Defines */ -#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" - -#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" -#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" - -/* The CP15 register access below has been deprecated in favor of the new - * isb instruction in Cortex R5. - */ -#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" -#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" -#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE "p15, 0, %0, c7, c5, 7" - -#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" -#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" - - -#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" -#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" - -#define XREG_CP15_INVAL_DC_ALL "p15, 0, %0, c15, c5, 0" -/* The next two CP15 register accesses below have been deprecated in favor - * of the new dsb and dmb instructions in Cortex R5. - */ -#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" -#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" - -#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" - -#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" - -#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" -#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" - -/* C8 Register Defines */ -/* Not Used */ - - -/* C9 Register Defines */ - -#define XREG_CP15_ATCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 1" -#define XREG_CP15_BTCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 0" -#define XREG_CP15_TCM_SELECTION "p15, 0, %0, c9, c2, 0" - -#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" -#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" -#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" -#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" -#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" -#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" - -#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" -#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" -#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" - -#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" -#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" -#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" - -/* C10 Register Defines */ -/* Not used */ - -/* C11 Register Defines */ -/* Not used */ - -/* C12 Register Defines */ -/* Not used */ - -/* C13 Register Defines */ -#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" -#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" -#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" -#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" - -/* C14 Register Defines */ -/* not used */ - -/* C15 Register Defines */ -#define XREG_CP15_SEC_AUX_CTRL "p15, 0, %0, c15, c0, 0" - - - - -/* MPE register definitions */ -#define XREG_FPSID c0 -#define XREG_FPSCR c1 -#define XREG_MVFR1 c6 -#define XREG_MVFR0 c7 -#define XREG_FPEXC c8 -#define XREG_FPINST c9 -#define XREG_FPINST2 c10 - -/* FPSID bits */ -#define XREG_FPSID_IMPLEMENTER_BIT (24U) -#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT) -#define XREG_FPSID_SOFTWARE (0X00000001U << 23U) -#define XREG_FPSID_ARCH_BIT (16U) -#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT) -#define XREG_FPSID_PART_BIT (8U) -#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT) -#define XREG_FPSID_VARIANT_BIT (4U) -#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT) -#define XREG_FPSID_REV_BIT (0U) -#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT) - -/* FPSCR bits */ -#define XREG_FPSCR_N_BIT (0X00000001U << 31U) -#define XREG_FPSCR_Z_BIT (0X00000001U << 30U) -#define XREG_FPSCR_C_BIT (0X00000001U << 29U) -#define XREG_FPSCR_V_BIT (0X00000001U << 28U) -#define XREG_FPSCR_QC (0X00000001U << 27U) -#define XREG_FPSCR_AHP (0X00000001U << 26U) -#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U) -#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U) -#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U) -#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U) -#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U) -#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U) -#define XREG_FPSCR_RMODE_BIT (22U) -#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT) -#define XREG_FPSCR_STRIDE_BIT (20U) -#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT) -#define XREG_FPSCR_LENGTH_BIT (16U) -#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT) -#define XREG_FPSCR_IDC (0X00000001U << 7U) -#define XREG_FPSCR_IXC (0X00000001U << 4U) -#define XREG_FPSCR_UFC (0X00000001U << 3U) -#define XREG_FPSCR_OFC (0X00000001U << 2U) -#define XREG_FPSCR_DZC (0X00000001U << 1U) -#define XREG_FPSCR_IOC (0X00000001U << 0U) - -/* MVFR0 bits */ -#define XREG_MVFR0_RMODE_BIT (28U) -#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT) -#define XREG_MVFR0_SHORT_VEC_BIT (24U) -#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT) -#define XREG_MVFR0_SQRT_BIT (20U) -#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT) -#define XREG_MVFR0_DIVIDE_BIT (16U) -#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT) -#define XREG_MVFR0_EXEC_TRAP_BIT (12U) -#define XREG_MVFR0_EXEC_TRAP_MASK (0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT) -#define XREG_MVFR0_DP_BIT (8U) -#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT) -#define XREG_MVFR0_SP_BIT (4U) -#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT) -#define XREG_MVFR0_A_SIMD_BIT (0U) -#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT) - -/* FPEXC bits */ -#define XREG_FPEXC_EX (0X00000001U << 31U) -#define XREG_FPEXC_EN (0X00000001U << 30U) -#define XREG_FPEXC_DEX (0X00000001U << 29U) - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* XREG_CORTEXR5_H */ diff --git a/template.uvprojx b/template.uvprojx index 4593f0a..3445a8b 100644 --- a/template.uvprojx +++ b/template.uvprojx @@ -48,10 +48,10 @@ 0 1 - .\build\keil\Obj\ - rt-thread - 1 - 0 + .\build\ + F413_RTT + 0 + 1 0 1 0 @@ -82,7 +82,7 @@ 1 0 - fromelf --bin !L --output rtthread.bin + E:\xyfc\413\work\stm32f413\move_lib.bat 0 0