@@ -151,18 +151,30 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
/* DMA2 stream0 */
|
||||
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
|
||||
#if defined(BSP_UART9_TX_USING_DMA) && !defined(UART9_TX_DMA_INSTANCE)
|
||||
#define UART9_DMA_TX_IRQHandler DMA2_Stream0_IRQHandler
|
||||
#define UART9_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define UART9_TX_DMA_INSTANCE DMA2_Stream0
|
||||
#define UART9_TX_DMA_CHANNEL DMA_CHANNEL_1
|
||||
#define UART9_TX_DMA_IRQ DMA2_Stream0_IRQn
|
||||
#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
|
||||
#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
|
||||
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define SPI1_RX_DMA_INSTANCE DMA2_Stream0
|
||||
#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
|
||||
#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
|
||||
#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
|
||||
#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
|
||||
#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define SPI4_RX_DMA_INSTANCE DMA2_Stream0
|
||||
#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_4
|
||||
#define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn
|
||||
#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
|
||||
#define SPI4_DMA_TX_IRQHandler DMA2_Stream0_IRQHandler
|
||||
#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define SPI4_TX_DMA_INSTANCE DMA2_Stream0
|
||||
#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4
|
||||
#define SPI4_TX_DMA_IRQ DMA2_Stream0_IRQn
|
||||
#elif defined(BSP_UART10_RX_USING_DMA) && !defined(UART10_RX_DMA_INSTANCE)
|
||||
#define UART10_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
|
||||
#define UART10_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define UART10_RX_DMA_INSTANCE DMA2_Stream0
|
||||
#define UART10_RX_DMA_CHANNEL DMA_CHANNEL_5
|
||||
#define UART10_RX_DMA_IRQ DMA2_Stream0_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA2 stream1 */
|
||||
@@ -208,12 +220,18 @@ extern "C" {
|
||||
#define SPI1_TX_DMA_INSTANCE DMA2_Stream3
|
||||
#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
|
||||
#define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn
|
||||
#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
|
||||
#define SPI4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
|
||||
#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define SPI4_RX_DMA_INSTANCE DMA2_Stream3
|
||||
#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_5
|
||||
#define SPI4_RX_DMA_IRQ DMA2_Stream3_IRQn
|
||||
#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
|
||||
#define SPI4_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler
|
||||
#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define SPI4_TX_DMA_INSTANCE DMA2_Stream3
|
||||
#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5
|
||||
#define SPI4_TX_DMA_IRQ DMA2_Stream3_IRQn
|
||||
#elif defined(BSP_UART10_RX_USING_DMA) && !defined(UART10_RX_DMA_INSTANCE)
|
||||
#define UART10_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
|
||||
#define UART10_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define UART10_RX_DMA_INSTANCE DMA2_Stream3
|
||||
#define UART10_RX_DMA_CHANNEL DMA_CHANNEL_9
|
||||
#define UART10_RX_DMA_IRQ DMA2_Stream3_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA2 stream4 */
|
||||
@@ -250,6 +268,12 @@ extern "C" {
|
||||
#define SPI5_RX_DMA_INSTANCE DMA2_Stream5
|
||||
#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7
|
||||
#define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn
|
||||
#elif defined(BSP_UART10_TX_USING_DMA) && !defined(UART10_TX_DMA_INSTANCE)
|
||||
#define UART10_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler
|
||||
#define UART10_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define UART10_TX_DMA_INSTANCE DMA2_Stream5
|
||||
#define UART10_TX_DMA_CHANNEL DMA_CHANNEL_9
|
||||
#define UART10_TX_DMA_IRQ DMA2_Stream5_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA2 stream6 */
|
||||
@@ -259,7 +283,7 @@ extern "C" {
|
||||
#define SPI5_TX_DMA_INSTANCE DMA2_Stream6
|
||||
#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7
|
||||
#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn
|
||||
#elif defined(BSP_UART6_TX_USING_DMA) && !defined(BSP_USING_SDIO) && !defined(UART6_TX_DMA_INSTANCE)
|
||||
#elif defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
|
||||
#define UART6_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler
|
||||
#define UART6_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define UART6_TX_DMA_INSTANCE DMA2_Stream6
|
||||
@@ -268,18 +292,24 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
/* DMA2 stream7 */
|
||||
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
|
||||
#if defined(BSP_UART9_RX_USING_DMA) && !defined(UART9_RX_DMA_INSTANCE)
|
||||
#define UART9_DMA_RX_IRQHandler DMA2_Stream7_IRQHandler
|
||||
#define UART9_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define UART9_RX_DMA_INSTANCE DMA2_Stream7
|
||||
#define UART9_RX_DMA_CHANNEL DMA_CHANNEL_0
|
||||
#define UART9_RX_DMA_IRQ DMA2_Stream7_IRQn
|
||||
#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
|
||||
#define UART1_DMA_TX_IRQHandler DMA2_Stream7_IRQHandler
|
||||
#define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define UART1_TX_DMA_INSTANCE DMA2_Stream7
|
||||
#define UART1_TX_DMA_CHANNEL DMA_CHANNEL_4
|
||||
#define UART1_TX_DMA_IRQ DMA2_Stream7_IRQn
|
||||
#elif defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
|
||||
#define UART6_DMA_TX_IRQHandler DMA2_Stream7_IRQHandler
|
||||
#define UART6_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define UART6_TX_DMA_INSTANCE DMA2_Stream7
|
||||
#define UART6_TX_DMA_CHANNEL DMA_CHANNEL_5
|
||||
#define UART6_TX_DMA_IRQ DMA2_Stream7_IRQn
|
||||
#elif defined(BSP_UART10_TX_USING_DMA) && !defined(UART10_TX_DMA_INSTANCE)
|
||||
#define UART10_DMA_TX_IRQHandler DMA2_Stream7_IRQHandler
|
||||
#define UART10_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define UART10_TX_DMA_INSTANCE DMA2_Stream7
|
||||
#define UART10_TX_DMA_CHANNEL DMA_CHANNEL_6
|
||||
#define UART10_TX_DMA_IRQ DMA2_Stream7_IRQn
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
@@ -298,6 +298,76 @@ extern "C" {
|
||||
#endif /* BSP_UART8_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART8 */
|
||||
|
||||
#if defined(BSP_USING_UART9)
|
||||
#ifndef UART9_CONFIG
|
||||
#define UART9_CONFIG \
|
||||
{ \
|
||||
.name = "uart9", \
|
||||
.Instance = UART9, \
|
||||
.irq_type = UART9_IRQn, \
|
||||
}
|
||||
#endif /* UART8_CONFIG */
|
||||
|
||||
#if defined(BSP_UART9_RX_USING_DMA)
|
||||
#ifndef UART9_DMA_RX_CONFIG
|
||||
#define UART9_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART8_RX_DMA_INSTANCE, \
|
||||
.channel = UART8_RX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART8_RX_DMA_RCC, \
|
||||
.dma_irq = UART8_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART9_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART9_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART9_TX_USING_DMA)
|
||||
#ifndef UART9_DMA_TX_CONFIG
|
||||
#define UART9_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART9_TX_DMA_INSTANCE, \
|
||||
.channel = UART9_TX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART9_TX_DMA_RCC, \
|
||||
.dma_irq = UART9_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART9_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART9_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART9 */
|
||||
|
||||
#if defined(BSP_USING_UART10)
|
||||
#ifndef UART10_CONFIG
|
||||
#define UART10_CONFIG \
|
||||
{ \
|
||||
.name = "uart10", \
|
||||
.Instance = UART10, \
|
||||
.irq_type = UART10_IRQn, \
|
||||
}
|
||||
#endif /* UART8_CONFIG */
|
||||
|
||||
#if defined(BSP_UART10_RX_USING_DMA)
|
||||
#ifndef UART10_DMA_RX_CONFIG
|
||||
#define UART10_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART10_RX_DMA_INSTANCE, \
|
||||
.channel = UART10_RX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART10_RX_DMA_RCC, \
|
||||
.dma_irq = UART10_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART10_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART10_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART10_TX_USING_DMA)
|
||||
#ifndef UART10_DMA_TX_CONFIG
|
||||
#define UART10_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART10_TX_DMA_INSTANCE, \
|
||||
.channel = UART10_TX_DMA_CHANNEL, \
|
||||
.dma_rcc = UART10_TX_DMA_RCC, \
|
||||
.dma_irq = UART10_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART10_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART10_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART10 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
@@ -113,6 +113,14 @@ static struct stm32_can drv_can2 =
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_CAN3
|
||||
static struct stm32_can drv_can3 =
|
||||
{
|
||||
"can3",
|
||||
.CanHandle.Instance = CAN3,
|
||||
};
|
||||
#endif
|
||||
|
||||
static rt_uint32_t get_can_baud_index(rt_uint32_t baud)
|
||||
{
|
||||
rt_uint32_t len, index;
|
||||
@@ -206,6 +214,13 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
|
||||
HAL_NVIC_DisableIRQ(CAN2_RX0_IRQn);
|
||||
HAL_NVIC_DisableIRQ(CAN2_RX1_IRQn);
|
||||
}
|
||||
#endif
|
||||
#ifdef CAN3
|
||||
if (CAN3 == drv_can->CanHandle.Instance)
|
||||
{
|
||||
HAL_NVIC_DisableIRQ(CAN3_RX0_IRQn);
|
||||
HAL_NVIC_DisableIRQ(CAN3_RX1_IRQn);
|
||||
}
|
||||
#endif
|
||||
__HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_MSG_PENDING);
|
||||
__HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_FULL);
|
||||
@@ -225,6 +240,12 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
|
||||
{
|
||||
HAL_NVIC_DisableIRQ(CAN2_TX_IRQn);
|
||||
}
|
||||
#endif
|
||||
#ifdef CAN3
|
||||
if (CAN3 == drv_can->CanHandle.Instance)
|
||||
{
|
||||
HAL_NVIC_DisableIRQ(CAN3_TX_IRQn);
|
||||
}
|
||||
#endif
|
||||
__HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_TX_MAILBOX_EMPTY);
|
||||
}
|
||||
@@ -239,6 +260,12 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
|
||||
{
|
||||
NVIC_DisableIRQ(CAN2_SCE_IRQn);
|
||||
}
|
||||
#endif
|
||||
#ifdef CAN3
|
||||
if (CAN3 == drv_can->CanHandle.Instance)
|
||||
{
|
||||
NVIC_DisableIRQ(CAN3_SCE_IRQn);
|
||||
}
|
||||
#endif
|
||||
__HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR_WARNING);
|
||||
__HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR_PASSIVE);
|
||||
@@ -273,6 +300,15 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
|
||||
HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 1, 0);
|
||||
HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn);
|
||||
}
|
||||
#endif
|
||||
#ifdef CAN3
|
||||
if (CAN3 == drv_can->CanHandle.Instance)
|
||||
{
|
||||
HAL_NVIC_SetPriority(CAN3_RX0_IRQn, 1, 0);
|
||||
HAL_NVIC_EnableIRQ(CAN3_RX0_IRQn);
|
||||
HAL_NVIC_SetPriority(CAN3_RX1_IRQn, 1, 0);
|
||||
HAL_NVIC_EnableIRQ(CAN3_RX1_IRQn);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else if (argval == RT_DEVICE_FLAG_INT_TX)
|
||||
@@ -290,6 +326,13 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
|
||||
HAL_NVIC_SetPriority(CAN2_TX_IRQn, 1, 0);
|
||||
HAL_NVIC_EnableIRQ(CAN2_TX_IRQn);
|
||||
}
|
||||
#endif
|
||||
#ifdef CAN3
|
||||
if (CAN3 == drv_can->CanHandle.Instance)
|
||||
{
|
||||
HAL_NVIC_SetPriority(CAN3_TX_IRQn, 1, 0);
|
||||
HAL_NVIC_EnableIRQ(CAN3_TX_IRQn);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else if (argval == RT_DEVICE_CAN_INT_ERR)
|
||||
@@ -311,6 +354,13 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
|
||||
HAL_NVIC_SetPriority(CAN2_SCE_IRQn, 1, 0);
|
||||
HAL_NVIC_EnableIRQ(CAN2_SCE_IRQn);
|
||||
}
|
||||
#endif
|
||||
#ifdef CAN3
|
||||
if (CAN3 == drv_can->CanHandle.Instance)
|
||||
{
|
||||
HAL_NVIC_SetPriority(CAN3_SCE_IRQn, 1, 0);
|
||||
HAL_NVIC_EnableIRQ(CAN3_SCE_IRQn);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
break;
|
||||
@@ -623,6 +673,12 @@ static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
|
||||
pmsg->hdr = (rxheader.FilterMatchIndex >> 1) + 14;
|
||||
}
|
||||
#endif
|
||||
#ifdef CAN3
|
||||
else if (hcan->Instance == CAN3)
|
||||
{
|
||||
pmsg->hdr = (rxheader.FilterMatchIndex + 1) >> 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
@@ -937,6 +993,126 @@ void CAN2_SCE_IRQHandler(void)
|
||||
}
|
||||
#endif /* BSP_USING_CAN2 */
|
||||
|
||||
#ifdef BSP_USING_CAN3
|
||||
/**
|
||||
* @brief This function handles CAN3 TX interrupts. transmit fifo0/1/2 is empty can trigger this interrupt
|
||||
*/
|
||||
void CAN3_TX_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
CAN_HandleTypeDef *hcan;
|
||||
hcan = &drv_can3.CanHandle;
|
||||
if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP0))
|
||||
{
|
||||
if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0))
|
||||
{
|
||||
rt_hw_can_isr(&drv_can3.device, RT_CAN_EVENT_TX_DONE | 0 << 8);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_hw_can_isr(&drv_can3.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
|
||||
}
|
||||
/* Write 0 to Clear transmission status flag RQCPx */
|
||||
SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0);
|
||||
}
|
||||
else if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP1))
|
||||
{
|
||||
if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1))
|
||||
{
|
||||
rt_hw_can_isr(&drv_can3.device, RT_CAN_EVENT_TX_DONE | 1 << 8);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_hw_can_isr(&drv_can3.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
|
||||
}
|
||||
/* Write 0 to Clear transmission status flag RQCPx */
|
||||
SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP1);
|
||||
}
|
||||
else if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP2))
|
||||
{
|
||||
if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2))
|
||||
{
|
||||
rt_hw_can_isr(&drv_can3.device, RT_CAN_EVENT_TX_DONE | 2 << 8);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_hw_can_isr(&drv_can3.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
|
||||
}
|
||||
/* Write 0 to Clear transmission status flag RQCPx */
|
||||
SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP2);
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles CAN3 RX0 interrupts.
|
||||
*/
|
||||
void CAN3_RX0_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
_can_rx_isr(&drv_can3.device, CAN_RX_FIFO0);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles CAN3 RX1 interrupts.
|
||||
*/
|
||||
void CAN3_RX1_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
_can_rx_isr(&drv_can3.device, CAN_RX_FIFO1);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles CAN3 SCE interrupts.
|
||||
*/
|
||||
void CAN3_SCE_IRQHandler(void)
|
||||
{
|
||||
rt_uint32_t errtype;
|
||||
CAN_HandleTypeDef *hcan;
|
||||
|
||||
hcan = &drv_can3.CanHandle;
|
||||
errtype = hcan->Instance->ESR;
|
||||
|
||||
rt_interrupt_enter();
|
||||
HAL_CAN_IRQHandler(hcan);
|
||||
|
||||
switch ((errtype & 0x70) >> 4)
|
||||
{
|
||||
case RT_CAN_BUS_BIT_PAD_ERR:
|
||||
drv_can3.device.status.bitpaderrcnt++;
|
||||
break;
|
||||
case RT_CAN_BUS_FORMAT_ERR:
|
||||
drv_can3.device.status.formaterrcnt++;
|
||||
break;
|
||||
case RT_CAN_BUS_ACK_ERR:/* attention !!! test ack err's unit is transmit unit */
|
||||
drv_can3.device.status.ackerrcnt++;
|
||||
if (!READ_BIT(drv_can3.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
|
||||
rt_hw_can_isr(&drv_can3.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
|
||||
else if (!READ_BIT(drv_can3.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
|
||||
rt_hw_can_isr(&drv_can3.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
|
||||
else if (!READ_BIT(drv_can3.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
|
||||
rt_hw_can_isr(&drv_can3.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
|
||||
break;
|
||||
case RT_CAN_BUS_IMPLICIT_BIT_ERR:
|
||||
case RT_CAN_BUS_EXPLICIT_BIT_ERR:
|
||||
drv_can3.device.status.biterrcnt++;
|
||||
break;
|
||||
case RT_CAN_BUS_CRC_ERR:
|
||||
drv_can3.device.status.crcerrcnt++;
|
||||
break;
|
||||
}
|
||||
|
||||
drv_can3.device.status.lasterrtype = errtype & 0x70;
|
||||
drv_can3.device.status.rcverrcnt = errtype >> 24;
|
||||
drv_can3.device.status.snderrcnt = (errtype >> 16 & 0xFF);
|
||||
drv_can3.device.status.errcode = errtype & 0x07;
|
||||
hcan->Instance->MSR |= CAN_MSR_ERRI;
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* BSP_USING_CAN3 */
|
||||
|
||||
/**
|
||||
* @brief Error CAN callback.
|
||||
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
||||
@@ -1007,6 +1183,18 @@ int rt_hw_can_init(void)
|
||||
&drv_can2);
|
||||
#endif /* BSP_USING_CAN2 */
|
||||
|
||||
#ifdef BSP_USING_CAN3
|
||||
filterConf.FilterBank = 0;
|
||||
|
||||
drv_can3.FilterConfig = filterConf;
|
||||
drv_can3.device.config = config;
|
||||
/* register CAN3 device */
|
||||
rt_hw_can_register(&drv_can3.device,
|
||||
drv_can3.name,
|
||||
&_can_ops,
|
||||
&drv_can3);
|
||||
#endif /* BSP_USING_CAN3 */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@@ -25,7 +25,8 @@
|
||||
|
||||
#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
|
||||
!defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
|
||||
!defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1)
|
||||
!defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_UART9) && \
|
||||
!defined(BSP_USING_UART10) && !defined(BSP_USING_LPUART1)
|
||||
#error "Please define at least one BSP_USING_UARTx"
|
||||
/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
|
||||
#endif
|
||||
@@ -60,6 +61,12 @@ enum
|
||||
#ifdef BSP_USING_UART8
|
||||
UART8_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART9
|
||||
UART9_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART10
|
||||
UART10_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_LPUART1
|
||||
LPUART1_INDEX,
|
||||
#endif
|
||||
@@ -91,6 +98,12 @@ static struct stm32_uart_config uart_config[] =
|
||||
#ifdef BSP_USING_UART8
|
||||
UART8_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART9
|
||||
UART9_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART10
|
||||
UART10_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_LPUART1
|
||||
LPUART1_CONFIG,
|
||||
#endif
|
||||
@@ -795,6 +808,80 @@ void UART8_DMA_TX_IRQHandler(void)
|
||||
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */
|
||||
#endif /* BSP_USING_UART8*/
|
||||
|
||||
#if defined(BSP_USING_UART9)
|
||||
void UART9_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
uart_isr(&(uart_obj[UART9_INDEX].serial));
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART9_RX_USING_DMA)
|
||||
void UART9_DMA_RX_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_DMA_IRQHandler(&uart_obj[UART9_INDEX].dma_rx.handle);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART9_RX_USING_DMA) */
|
||||
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART9_TX_USING_DMA)
|
||||
void UART9_DMA_TX_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_DMA_IRQHandler(&uart_obj[UART9_INDEX].dma_tx.handle);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART9_TX_USING_DMA) */
|
||||
#endif /* BSP_USING_UART9*/
|
||||
|
||||
#if defined(BSP_USING_UART10)
|
||||
void UART10_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
uart_isr(&(uart_obj[UART10_INDEX].serial));
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART10_RX_USING_DMA)
|
||||
void UART10_DMA_RX_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_DMA_IRQHandler(&uart_obj[UART10_INDEX].dma_rx.handle);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART10_RX_USING_DMA) */
|
||||
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART10_TX_USING_DMA)
|
||||
void UART10_DMA_TX_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_DMA_IRQHandler(&uart_obj[UART10_INDEX].dma_tx.handle);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART10_TX_USING_DMA) */
|
||||
#endif /* BSP_USING_UART10*/
|
||||
|
||||
#if defined(BSP_USING_LPUART1)
|
||||
void LPUART1_IRQHandler(void)
|
||||
{
|
||||
@@ -820,6 +907,8 @@ void LPUART1_DMA_RX_IRQHandler(void)
|
||||
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
|
||||
#endif /* BSP_USING_LPUART1*/
|
||||
|
||||
#ifdef RT_SERIAL_USING_DMA
|
||||
|
||||
static void stm32_uart_get_dma_config(void)
|
||||
{
|
||||
#ifdef BSP_USING_UART1
|
||||
@@ -933,9 +1022,36 @@ static void stm32_uart_get_dma_config(void)
|
||||
uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART9
|
||||
uart_obj[UART8_INDEX].uart_dma_flag = 0;
|
||||
#ifdef BSP_UART9_RX_USING_DMA
|
||||
uart_obj[UART9_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
||||
static struct dma_config uart9_dma_rx = UART9_DMA_RX_CONFIG;
|
||||
uart_config[UART9_INDEX].dma_rx = &uart8_dma_rx;
|
||||
#endif
|
||||
#ifdef BSP_UART9_TX_USING_DMA
|
||||
uart_obj[UART9_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
||||
static struct dma_config uart9_dma_tx = UART9_DMA_TX_CONFIG;
|
||||
uart_config[UART9_INDEX].dma_tx = &uart9_dma_tx;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART10
|
||||
uart_obj[UART10_INDEX].uart_dma_flag = 0;
|
||||
#ifdef BSP_UART10_RX_USING_DMA
|
||||
uart_obj[UART10_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
||||
static struct dma_config uart10_dma_rx = UART10_DMA_RX_CONFIG;
|
||||
uart_config[UART10_INDEX].dma_rx = &uart10_dma_rx;
|
||||
#endif
|
||||
#ifdef BSP_UART10_TX_USING_DMA
|
||||
uart_obj[UART10_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
||||
static struct dma_config uart10_dma_tx = UART10_DMA_TX_CONFIG;
|
||||
uart_config[UART10_INDEX].dma_tx = &uart10_dma_tx;
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef RT_SERIAL_USING_DMA
|
||||
static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
|
||||
{
|
||||
struct rt_serial_rx_fifo *rx_fifo;
|
||||
|
Reference in New Issue
Block a user