107 lines
2.7 KiB
C
107 lines
2.7 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-06 SummerGift first version
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*/
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#include "board.h"
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/**
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* @brief System Clock Configuration
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* @retval None
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*/
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void SystemClock_Config(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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/** Configure the main internal regulator output voltage
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*/
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__HAL_RCC_PWR_CLK_ENABLE();
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 8;
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RCC_OscInitStruct.PLL.PLLN = 200;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = 2;
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RCC_OscInitStruct.PLL.PLLR = 2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
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{
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Error_Handler();
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}
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/** Enables the Clock Security System
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*/
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HAL_RCC_EnableCSS();
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}
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// init ports
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extern int cplusplus_system_init(void);
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INIT_COMPONENT_EXPORT(cplusplus_system_init);
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extern void fal(uint8_t argc, char **argv);
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MSH_CMD_EXPORT(fal, FAL (Flash Abstraction Layer) operate.);
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extern int fal_init(void);
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INIT_ENV_EXPORT(fal_init);
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extern int iap_main_entry(void);
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INIT_ENV_EXPORT(iap_main_entry);
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#include <stdlib.h>
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static void reset_fc(int argc, char **argv)
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{
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int second = 20; // default 20s
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if (argc > 1)
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{
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second = atoi(argv[1]);
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}
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rt_kprintf("\n the system will be reset after %ds\n", second);
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rt_enter_critical();
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rt_console_set_device(RT_NULL);
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rt_exit_critical();
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rt_thread_delay(1000 * second);
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rt_hw_cpu_reset();
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}
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MSH_CMD_EXPORT(reset_fc, resetfc cmd);
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extern int ulog_console_backend_init(void);
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INIT_PREV_EXPORT(ulog_console_backend_init);
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extern int rt_hw_can_init(void);
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INIT_BOARD_EXPORT(rt_hw_can_init);
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extern int stm32_pwm_init(void);
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INIT_DEVICE_EXPORT(stm32_pwm_init);
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extern int stm32_adc_init(void);
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INIT_BOARD_EXPORT(stm32_adc_init);
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